翻译文档
STM32G4xx HAL Drivers
Modules
uwTick
uwTickFreq
uwTickFreq
uwTickPrio
uwTickPrio
HAL Exported Functions
HAL_Init
HAL_InitTick
HAL_MspDeInit
HAL_MspInit
HAL Control functions
HAL_GetDEVID
HAL_GetHalVersion
HAL_GetREVID
HAL_GetTick
HAL_GetTickFreq
HAL_GetTickPrio
HAL_GetUIDw0
HAL_GetUIDw1
HAL_GetUIDw2
HAL_IncTick
HAL_ResumeTick
HAL_SetTickFreq
HAL_SuspendTick
HAL Debug functions
HAL_DBGMCU_DisableDBGStandbyMode
HAL_DBGMCU_DisableDBGStopMode
HAL_DBGMCU_EnableDBGSleepMode
HAL_DBGMCU_EnableDBGStandbyMode
HAL_DBGMCU_EnableDBGStopMode
HAL SYSCFG configuration functions
HAL_SYSCFG_CCMSRAMErase
HAL_SYSCFG_DisableIOSwitchBooster
HAL_SYSCFG_DisableIOSwitchVDD
HAL_SYSCFG_DisableMemorySwappingBank
HAL_SYSCFG_DisableVREFBUF
HAL_SYSCFG_EnableIOSwitchBooster
HAL_SYSCFG_EnableIOSwitchVDD
HAL_SYSCFG_EnableMemorySwappingBank
HAL_SYSCFG_EnableVREFBUF
HAL_SYSCFG_VREFBUF_HighImpedanceConfig
HAL_SYSCFG_VREFBUF_TrimmingConfig
HAL_SYSCFG_VREFBUF_VoltageScalingConfig
HAL Exported Variables
uwTick
uwTickFreq
uwTickFreq
uwTickPrio
uwTickPrio
HAL Exported Constants
HAL_TICK_FREQ_10HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
SYSCFG Exported Constants
SYSCFG_BOOT_MAINFLASH
SYSCFG_BOOT_QUADSPI
SYSCFG_BOOT_SRAM
SYSCFG_BOOT_SYSTEMFLASH
FPU Interrupts
SYSCFG_IT_FPU_IDC
SYSCFG_IT_FPU_IOC
SYSCFG_IT_FPU_IXC
SYSCFG_IT_FPU_OFC
SYSCFG_IT_FPU_UFC
CCM Write protection
SYSCFG_CCMSRAMWRP_PAGE1
SYSCFG_CCMSRAMWRP_PAGE10
SYSCFG_CCMSRAMWRP_PAGE11
SYSCFG_CCMSRAMWRP_PAGE12
SYSCFG_CCMSRAMWRP_PAGE13
SYSCFG_CCMSRAMWRP_PAGE14
SYSCFG_CCMSRAMWRP_PAGE15
SYSCFG_CCMSRAMWRP_PAGE16
SYSCFG_CCMSRAMWRP_PAGE17
SYSCFG_CCMSRAMWRP_PAGE18
SYSCFG_CCMSRAMWRP_PAGE19
SYSCFG_CCMSRAMWRP_PAGE2
SYSCFG_CCMSRAMWRP_PAGE20
SYSCFG_CCMSRAMWRP_PAGE21
SYSCFG_CCMSRAMWRP_PAGE22
SYSCFG_CCMSRAMWRP_PAGE23
SYSCFG_CCMSRAMWRP_PAGE24
SYSCFG_CCMSRAMWRP_PAGE25
SYSCFG_CCMSRAMWRP_PAGE26
SYSCFG_CCMSRAMWRP_PAGE27
SYSCFG_CCMSRAMWRP_PAGE28
SYSCFG_CCMSRAMWRP_PAGE29
SYSCFG_CCMSRAMWRP_PAGE3
SYSCFG_CCMSRAMWRP_PAGE30
SYSCFG_CCMSRAMWRP_PAGE31
SYSCFG_CCMSRAMWRP_PAGE4
SYSCFG_CCMSRAMWRP_PAGE5
SYSCFG_CCMSRAMWRP_PAGE6
SYSCFG_CCMSRAMWRP_PAGE7
SYSCFG_CCMSRAMWRP_PAGE8
SYSCFG_CCMSRAMWRP_PAGE9
VREFBUF Voltage Scale
SYSCFG_VREFBUF_VOLTAGE_SCALE1
SYSCFG_VREFBUF_VOLTAGE_SCALE2
VREFBUF High Impedance
SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE
Flags
SYSCFG_FLAG_SRAM_PE
Fast-mode Plus on GPIO
SYSCFG_FASTMODEPLUS_PB7
SYSCFG_FASTMODEPLUS_PB8
SYSCFG_FASTMODEPLUS_PB9
DBGMCU Exported Macros
__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C4_TIMEOUT
__HAL_DBGMCU_FREEZE_IWDG
__HAL_DBGMCU_FREEZE_LPTIM1
__HAL_DBGMCU_FREEZE_RTC
__HAL_DBGMCU_FREEZE_TIM1
__HAL_DBGMCU_FREEZE_TIM15
__HAL_DBGMCU_FREEZE_TIM16
__HAL_DBGMCU_FREEZE_TIM17
__HAL_DBGMCU_FREEZE_TIM2
__HAL_DBGMCU_FREEZE_TIM20
__HAL_DBGMCU_FREEZE_TIM3
__HAL_DBGMCU_FREEZE_TIM4
__HAL_DBGMCU_FREEZE_TIM5
__HAL_DBGMCU_FREEZE_TIM6
__HAL_DBGMCU_FREEZE_TIM7
__HAL_DBGMCU_FREEZE_TIM8
__HAL_DBGMCU_FREEZE_WWDG
__HAL_DBGMCU_UNFREEZE_HRTIM1
__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT
__HAL_DBGMCU_UNFREEZE_IWDG
__HAL_DBGMCU_UNFREEZE_LPTIM1
__HAL_DBGMCU_UNFREEZE_RTC
__HAL_DBGMCU_UNFREEZE_TIM1
__HAL_DBGMCU_UNFREEZE_TIM15
__HAL_DBGMCU_UNFREEZE_TIM16
__HAL_DBGMCU_UNFREEZE_TIM17
__HAL_DBGMCU_UNFREEZE_TIM2
__HAL_DBGMCU_UNFREEZE_TIM20
__HAL_DBGMCU_UNFREEZE_TIM3
__HAL_DBGMCU_UNFREEZE_TIM4
__HAL_DBGMCU_UNFREEZE_TIM5
__HAL_DBGMCU_UNFREEZE_TIM6
__HAL_DBGMCU_UNFREEZE_TIM7
__HAL_DBGMCU_UNFREEZE_TIM8
__HAL_DBGMCU_UNFREEZE_WWDG
SYSCFG Exported Macros
__HAL_SYSCFG_BREAK_LOCKUP_LOCK
__HAL_SYSCFG_BREAK_PVD_LOCK
__HAL_SYSCFG_BREAK_SRAMPARITY_LOCK
__HAL_SYSCFG_CCMSRAM_ERASE
__HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
__HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE
__HAL_SYSCFG_CCMSRAM_WRP_UNLOCK
__HAL_SYSCFG_CLEAR_FLAG
__HAL_SYSCFG_FASTMODEPLUS_DISABLE
__HAL_SYSCFG_FASTMODEPLUS_ENABLE
__HAL_SYSCFG_FPU_INTERRUPT_DISABLE
__HAL_SYSCFG_FPU_INTERRUPT_ENABLE
__HAL_SYSCFG_GET_BOOT_MODE
__HAL_SYSCFG_GET_FLAG
__HAL_SYSCFG_REMAPMEMORY_FLASH
__HAL_SYSCFG_REMAPMEMORY_FMC
__HAL_SYSCFG_REMAPMEMORY_QUADSPI
__HAL_SYSCFG_REMAPMEMORY_SRAM
__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
SYSCFG Private Macros
IS_SYSCFG_CCMSRAMWRP_PAGE
IS_SYSCFG_FASTMODEPLUS
IS_SYSCFG_FPU_INTERRUPT
IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE
IS_SYSCFG_VREFBUF_TRIMMING
IS_SYSCFG_VREFBUF_VOLTAGE_SCALE
HAL Private Macros
Defines
__STM32G4xx_HAL_VERSION_MAIN
__STM32G4xx_HAL_VERSION_RC
__STM32G4xx_HAL_VERSION_SUB1
__STM32G4xx_HAL_VERSION_SUB2
CCMER_BitNumber
FB_MODE_BB
FB_MODE_BitNumber
MEMRMP_OFFSET
SCSR_CCMER_BB
SCSR_OFFSET
SYSCFG_OFFSET
VREFBUF_TIMEOUT_VALUE
ADC
ADC_CONVERSION_TIME_MAX_CPU_CYCLES
ADC_DISABLE_TIMEOUT
ADC_ENABLE_TIMEOUT
ADC_STOP_CONVERSION_TIMEOUT
ADC_TEMPSENSOR_DELAY_US
ADC Exported Functions
HAL_ADC_Init
HAL_ADC_MspDeInit
HAL_ADC_MspInit
HAL_ADC_RegisterCallback
HAL_ADC_UnRegisterCallback
ADC Input and Output operation functions
HAL_ADC_ConvHalfCpltCallback
HAL_ADC_ErrorCallback
HAL_ADC_GetValue
HAL_ADC_IRQHandler
HAL_ADC_LevelOutOfWindowCallback
HAL_ADC_PollForConversion
HAL_ADC_PollForEvent
HAL_ADC_Start
HAL_ADC_Start_DMA
HAL_ADC_Start_IT
HAL_ADC_StartSampling
HAL_ADC_Stop
HAL_ADC_Stop_DMA
HAL_ADC_Stop_IT
HAL_ADC_StopSampling
Peripheral Control functions
HAL_ADC_ConfigChannel
Peripheral State functions
HAL_ADC_GetState
ADC Private Functions
ADC_Disable
ADC_DMAConvCplt
ADC_DMAError
ADC_DMAHalfConvCplt
ADC_Enable
ADC Exported Types
HAL_ADC_STATE_AWD2
HAL_ADC_STATE_AWD3
HAL_ADC_STATE_BUSY_INTERNAL
HAL_ADC_STATE_ERROR_CONFIG
HAL_ADC_STATE_ERROR_DMA
HAL_ADC_STATE_ERROR_INTERNAL
HAL_ADC_STATE_INJ_BUSY
HAL_ADC_STATE_INJ_EOC
HAL_ADC_STATE_INJ_JQOVF
HAL_ADC_STATE_MULTIMODE_SLAVE
HAL_ADC_STATE_READY
HAL_ADC_STATE_REG_BUSY
HAL_ADC_STATE_REG_EOC
HAL_ADC_STATE_REG_EOSMP
HAL_ADC_STATE_REG_OVR
HAL_ADC_STATE_RESET
HAL_ADC_STATE_TIMEOUT
Typedefs
pADC_CallbackTypeDef
Enumerations
Data Structures
ADC_InitTypeDef
ADC_ChannelConfTypeDef
ADC_AnalogWDGConfTypeDef
ADC_InjectionConfigTypeDef
__ADC_HandleTypeDef
ADC Exported Constants
HAL_ADC_ERROR_INTERNAL
HAL_ADC_ERROR_INVALID_CALLBACK
HAL_ADC_ERROR_JQOVF
HAL_ADC_ERROR_NONE
HAL_ADC_ERROR_OVR
ADC common - Clock source
ADC_CLOCK_ASYNC_DIV10
ADC_CLOCK_ASYNC_DIV12
ADC_CLOCK_ASYNC_DIV128
ADC_CLOCK_ASYNC_DIV16
ADC_CLOCK_ASYNC_DIV2
ADC_CLOCK_ASYNC_DIV256
ADC_CLOCK_ASYNC_DIV32
ADC_CLOCK_ASYNC_DIV4
ADC_CLOCK_ASYNC_DIV6
ADC_CLOCK_ASYNC_DIV64
ADC_CLOCK_ASYNC_DIV8
ADC_CLOCK_SYNC_PCLK_DIV1
ADC_CLOCK_SYNC_PCLK_DIV2
ADC_CLOCK_SYNC_PCLK_DIV4
ADC instance - Resolution
ADC_RESOLUTION_12B
ADC_RESOLUTION_6B
ADC_RESOLUTION_8B
ADC conversion data alignment
ADC_DATAALIGN_RIGHT
ADC sequencer scan mode
ADC_SCAN_ENABLE
ADC group regular trigger source
ADC_EXTERNALTRIG_EXT_IT2
ADC_EXTERNALTRIG_HRTIM_TRG1
ADC_EXTERNALTRIG_HRTIM_TRG10
ADC_EXTERNALTRIG_HRTIM_TRG2
ADC_EXTERNALTRIG_HRTIM_TRG3
ADC_EXTERNALTRIG_HRTIM_TRG4
ADC_EXTERNALTRIG_HRTIM_TRG5
ADC_EXTERNALTRIG_HRTIM_TRG6
ADC_EXTERNALTRIG_HRTIM_TRG7
ADC_EXTERNALTRIG_HRTIM_TRG8
ADC_EXTERNALTRIG_HRTIM_TRG9
ADC_EXTERNALTRIG_LPTIM_OUT
ADC_EXTERNALTRIG_T15_TRGO
ADC_EXTERNALTRIG_T1_CC1
ADC_EXTERNALTRIG_T1_CC2
ADC_EXTERNALTRIG_T1_CC3
ADC_EXTERNALTRIG_T1_TRGO
ADC_EXTERNALTRIG_T1_TRGO2
ADC_EXTERNALTRIG_T20_CC1
ADC_EXTERNALTRIG_T20_CC2
ADC_EXTERNALTRIG_T20_CC3
ADC_EXTERNALTRIG_T20_TRGO
ADC_EXTERNALTRIG_T20_TRGO2
ADC_EXTERNALTRIG_T2_CC1
ADC_EXTERNALTRIG_T2_CC2
ADC_EXTERNALTRIG_T2_CC3
ADC_EXTERNALTRIG_T2_TRGO
ADC_EXTERNALTRIG_T3_CC1
ADC_EXTERNALTRIG_T3_CC4
ADC_EXTERNALTRIG_T3_TRGO
ADC_EXTERNALTRIG_T4_CC1
ADC_EXTERNALTRIG_T4_CC4
ADC_EXTERNALTRIG_T4_TRGO
ADC_EXTERNALTRIG_T6_TRGO
ADC_EXTERNALTRIG_T7_TRGO
ADC_EXTERNALTRIG_T8_CC1
ADC_EXTERNALTRIG_T8_TRGO
ADC_EXTERNALTRIG_T8_TRGO2
ADC_SOFTWARE_START
ADC group regular trigger edge (when external trigger is selected)
ADC_EXTERNALTRIGCONVEDGE_NONE
ADC_EXTERNALTRIGCONVEDGE_RISING
ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
ADC group regular sampling mode
ADC_SAMPLING_MODE_NORMAL
ADC_SAMPLING_MODE_TRIGGER_CONTROLED
ADC sequencer end of unitary conversion or sequence conversions
ADC_EOC_SINGLE_CONV
ADC group regular - Overrun behavior on conversion data
ADC_OVR_DATA_PRESERVED
ADC group regular - Sequencer ranks
ADC_REGULAR_RANK_10
ADC_REGULAR_RANK_11
ADC_REGULAR_RANK_12
ADC_REGULAR_RANK_13
ADC_REGULAR_RANK_14
ADC_REGULAR_RANK_15
ADC_REGULAR_RANK_16
ADC_REGULAR_RANK_2
ADC_REGULAR_RANK_3
ADC_REGULAR_RANK_4
ADC_REGULAR_RANK_5
ADC_REGULAR_RANK_6
ADC_REGULAR_RANK_7
ADC_REGULAR_RANK_8
ADC_REGULAR_RANK_9
Channel - Sampling time
ADC_SAMPLETIME_247CYCLES_5
ADC_SAMPLETIME_24CYCLES_5
ADC_SAMPLETIME_2CYCLES_5
ADC_SAMPLETIME_3CYCLES_5
ADC_SAMPLETIME_47CYCLES_5
ADC_SAMPLETIME_640CYCLES_5
ADC_SAMPLETIME_6CYCLES_5
ADC_SAMPLETIME_92CYCLES_5
ADC instance - Channel number
ADC_CHANNEL_1
ADC_CHANNEL_10
ADC_CHANNEL_11
ADC_CHANNEL_12
ADC_CHANNEL_13
ADC_CHANNEL_14
ADC_CHANNEL_15
ADC_CHANNEL_16
ADC_CHANNEL_17
ADC_CHANNEL_18
ADC_CHANNEL_2
ADC_CHANNEL_3
ADC_CHANNEL_4
ADC_CHANNEL_5
ADC_CHANNEL_6
ADC_CHANNEL_7
ADC_CHANNEL_8
ADC_CHANNEL_9
ADC_CHANNEL_TEMPSENSOR_ADC1
ADC_CHANNEL_TEMPSENSOR_ADC5
ADC_CHANNEL_VBAT
ADC_CHANNEL_VOPAMP1
ADC_CHANNEL_VOPAMP2
ADC_CHANNEL_VOPAMP3_ADC2
ADC_CHANNEL_VOPAMP3_ADC3
ADC_CHANNEL_VOPAMP4
ADC_CHANNEL_VOPAMP5
ADC_CHANNEL_VOPAMP6
ADC_CHANNEL_VREFINT
Analog watchdog - ADC analog watchdog (AWD) number
ADC_ANALOGWATCHDOG_2
ADC_ANALOGWATCHDOG_3
ADC analog watchdog (AWD) filtering configuration
ADC_AWD_FILTERING_3SAMPLES
ADC_AWD_FILTERING_4SAMPLES
ADC_AWD_FILTERING_5SAMPLES
ADC_AWD_FILTERING_6SAMPLES
ADC_AWD_FILTERING_7SAMPLES
ADC_AWD_FILTERING_8SAMPLES
ADC_AWD_FILTERING_NONE
ADC analog watchdog (AWD) mode
ADC_ANALOGWATCHDOG_ALL_REG
ADC_ANALOGWATCHDOG_ALL_REGINJEC
ADC_ANALOGWATCHDOG_NONE
ADC_ANALOGWATCHDOG_SINGLE_INJEC
ADC_ANALOGWATCHDOG_SINGLE_REG
ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
Oversampling - Ratio
ADC_OVERSAMPLING_RATIO_16
ADC_OVERSAMPLING_RATIO_2
ADC_OVERSAMPLING_RATIO_256
ADC_OVERSAMPLING_RATIO_32
ADC_OVERSAMPLING_RATIO_4
ADC_OVERSAMPLING_RATIO_64
ADC_OVERSAMPLING_RATIO_8
Oversampling - Data shift
ADC_RIGHTBITSHIFT_2
ADC_RIGHTBITSHIFT_3
ADC_RIGHTBITSHIFT_4
ADC_RIGHTBITSHIFT_5
ADC_RIGHTBITSHIFT_6
ADC_RIGHTBITSHIFT_7
ADC_RIGHTBITSHIFT_8
ADC_RIGHTBITSHIFT_NONE
Oversampling - Discontinuous mode
ADC_TRIGGEREDMODE_SINGLE_TRIGGER
Oversampling - Oversampling scope for ADC group regular
ADC_REGOVERSAMPLING_RESUMED_MODE
ADC Event type
ADC_AWD2_EVENT
ADC_AWD3_EVENT
ADC_EOSMP_EVENT
ADC_JQOVF_EVENT
ADC_OVR_EVENT
ADC interrupts definition
ADC_IT_AWD2
ADC_IT_AWD3
ADC_IT_EOC
ADC_IT_EOS
ADC_IT_EOSMP
ADC_IT_JEOC
ADC_IT_JEOS
ADC_IT_JQOVF
ADC_IT_OVR
ADC_IT_RDY
ADC flags definition
ADC_FLAG_AWD2
ADC_FLAG_AWD3
ADC_FLAG_EOC
ADC_FLAG_EOS
ADC_FLAG_EOSMP
ADC_FLAG_JEOC
ADC_FLAG_JEOS
ADC_FLAG_JQOVF
ADC_FLAG_OVR
ADC_FLAG_RDY
Defines
ADC Private Macros
ADC_GET_RESOLUTION
ADC_STATE_CLR_SET
IS_ADC_CLOCKPRESCALER
IS_ADC_DATA_ALIGN
IS_ADC_EOC_SELECTION
IS_ADC_EXTTRIG
IS_ADC_EXTTRIG_EDGE
IS_ADC_GAIN_COMPENSATION
IS_ADC_OVERRUN
IS_ADC_RANGE
IS_ADC_REGULAR_DISCONT_NUMBER
IS_ADC_REGULAR_NB_CONV
IS_ADC_REGULAR_RANK
IS_ADC_RESOLUTION
IS_ADC_RESOLUTION_8_6_BITS
IS_ADC_SAMPLE_TIME
IS_ADC_SAMPLINGMODE
IS_ADC_SCAN_MODE
ADC Exported Macros
__HAL_ADC_DISABLE_IT
__HAL_ADC_ENABLE_IT
__HAL_ADC_GET_FLAG
__HAL_ADC_GET_IT_SOURCE
__HAL_ADC_RESET_HANDLE_STATE
HAL ADC helper macro
__HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE
__HAL_ADC_CALC_TEMPERATURE
__HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS
__HAL_ADC_CALC_VREFANALOG_VOLTAGE
__HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL
__HAL_ADC_CHANNEL_TO_DECIMAL_NB
__HAL_ADC_COMMON_INSTANCE
__HAL_ADC_CONVERT_DATA_RESOLUTION
__HAL_ADC_DECIMAL_NB_TO_CHANNEL
__HAL_ADC_DIGITAL_SCALE
__HAL_ADC_IS_CHANNEL_INTERNAL
__HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE
__HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE
__HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE
ADCEx
ADC_JSQR_FIELDS
ADC Extended Exported Functions
HAL_ADCEx_Calibration_SetValue
HAL_ADCEx_Calibration_Start
HAL_ADCEx_EndOfSamplingCallback
HAL_ADCEx_InjectedConvCpltCallback
HAL_ADCEx_InjectedGetValue
HAL_ADCEx_InjectedPollForConversion
HAL_ADCEx_InjectedQueueOverflowCallback
HAL_ADCEx_InjectedStart
HAL_ADCEx_InjectedStart_IT
HAL_ADCEx_InjectedStop
HAL_ADCEx_InjectedStop_IT
HAL_ADCEx_LevelOutOfWindow2Callback
HAL_ADCEx_LevelOutOfWindow3Callback
HAL_ADCEx_MultiModeGetValue
HAL_ADCEx_MultiModeStart_DMA
HAL_ADCEx_MultiModeStop_DMA
HAL_ADCEx_RegularMultiModeStop_DMA
HAL_ADCEx_RegularStop
HAL_ADCEx_RegularStop_DMA
HAL_ADCEx_RegularStop_IT
ADC Extended Peripheral Control functions
HAL_ADCEx_DisableVoltageRegulator
HAL_ADCEx_EnableInjectedQueue
HAL_ADCEx_EnterADCDeepPowerDownMode
HAL_ADCEx_InjectedConfigChannel
HAL_ADCEx_MultiModeConfigChannel
ADC Extended Exported Types
ADC_InjectionConfTypeDef
ADC_MultiModeTypeDef
ADC Extended Exported Constants
ADC_EXTERNALTRIGINJEC_EXT_IT3
ADC_EXTERNALTRIGINJEC_HRTIM_TRG1
ADC_EXTERNALTRIGINJEC_HRTIM_TRG10
ADC_EXTERNALTRIGINJEC_HRTIM_TRG2
ADC_EXTERNALTRIGINJEC_HRTIM_TRG3
ADC_EXTERNALTRIGINJEC_HRTIM_TRG4
ADC_EXTERNALTRIGINJEC_HRTIM_TRG5
ADC_EXTERNALTRIGINJEC_HRTIM_TRG6
ADC_EXTERNALTRIGINJEC_HRTIM_TRG7
ADC_EXTERNALTRIGINJEC_HRTIM_TRG8
ADC_EXTERNALTRIGINJEC_HRTIM_TRG9
ADC_EXTERNALTRIGINJEC_LPTIM_OUT
ADC_EXTERNALTRIGINJEC_T15_TRGO
ADC_EXTERNALTRIGINJEC_T16_CC1
ADC_EXTERNALTRIGINJEC_T1_CC3
ADC_EXTERNALTRIGINJEC_T1_CC4
ADC_EXTERNALTRIGINJEC_T1_TRGO
ADC_EXTERNALTRIGINJEC_T1_TRGO2
ADC_EXTERNALTRIGINJEC_T20_CC2
ADC_EXTERNALTRIGINJEC_T20_CC4
ADC_EXTERNALTRIGINJEC_T20_TRGO
ADC_EXTERNALTRIGINJEC_T20_TRGO2
ADC_EXTERNALTRIGINJEC_T2_CC1
ADC_EXTERNALTRIGINJEC_T2_TRGO
ADC_EXTERNALTRIGINJEC_T3_CC1
ADC_EXTERNALTRIGINJEC_T3_CC3
ADC_EXTERNALTRIGINJEC_T3_CC4
ADC_EXTERNALTRIGINJEC_T3_TRGO
ADC_EXTERNALTRIGINJEC_T4_CC3
ADC_EXTERNALTRIGINJEC_T4_CC4
ADC_EXTERNALTRIGINJEC_T4_TRGO
ADC_EXTERNALTRIGINJEC_T6_TRGO
ADC_EXTERNALTRIGINJEC_T7_TRGO
ADC_EXTERNALTRIGINJEC_T8_CC2
ADC_EXTERNALTRIGINJEC_T8_CC4
ADC_EXTERNALTRIGINJEC_T8_TRGO
ADC_EXTERNALTRIGINJEC_T8_TRGO2
ADC_INJECTED_SOFTWARE_START
ADC group injected trigger edge (when external trigger is selected)
ADC_EXTERNALTRIGINJECCONV_EDGE_NONE
ADC_EXTERNALTRIGINJECCONV_EDGE_RISING
ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING
Channel - Single or differential ending
ADC_SINGLE_ENDED
ADC instance - Offset number
ADC_OFFSET_2
ADC_OFFSET_3
ADC_OFFSET_4
ADC_OFFSET_NONE
ADC Extended Offset Sign
ADC_OFFSET_SIGN_POSITIVE
ADC group injected - Sequencer ranks
ADC_INJECTED_RANK_2
ADC_INJECTED_RANK_3
ADC_INJECTED_RANK_4
Multimode - Mode
ADC_DMAACCESSMODE_8_6_BITS
ADC_DMAACCESSMODE_DISABLED
Multimode - Delay between two sampling phases
ADC_TWOSAMPLINGDELAY_11CYCLES
ADC_TWOSAMPLINGDELAY_12CYCLES
ADC_TWOSAMPLINGDELAY_1CYCLE
ADC_TWOSAMPLINGDELAY_2CYCLES
ADC_TWOSAMPLINGDELAY_3CYCLES
ADC_TWOSAMPLINGDELAY_4CYCLES
ADC_TWOSAMPLINGDELAY_5CYCLES
ADC_TWOSAMPLINGDELAY_6CYCLES
ADC_TWOSAMPLINGDELAY_7CYCLES
ADC_TWOSAMPLINGDELAY_8CYCLES
ADC_TWOSAMPLINGDELAY_9CYCLES
Defines
ADC_DUALMODE_INJECSIMULT
ADC_DUALMODE_INTERL
ADC_DUALMODE_REGINTERL_INJECSIMULT
ADC_DUALMODE_REGSIMULT
ADC_DUALMODE_REGSIMULT_ALTERTRIG
ADC_DUALMODE_REGSIMULT_INJECSIMULT
ADC_MODE_INDEPENDENT
ADC instance - Groups
ADC_REGULAR_GROUP
ADC_REGULAR_INJECTED_GROUP
ADCx CFGR fields
ADCx SMPR1 fields
ADCx CFGR sub fields
ADC Extended Exported Macros
ADC Extended Private Macros
ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
ADC_BATTERY_VOLTAGE_INSTANCE
ADC_CCR_MULTI_DMACONTREQ
ADC_CFGR_AUTOWAIT
ADC_CFGR_CONTINUOUS
ADC_CFGR_DFSDM
ADC_CFGR_DISCONTINUOUS_NUM
ADC_CFGR_DMACONTREQ
ADC_CFGR_INJECT_CONTEXT_QUEUE
ADC_CFGR_INJECT_DISCCONTINUOUS
ADC_CFGR_REG_DISCONTINUOUS
ADC_CLEAR_COMMON_CONTROL_REGISTER
ADC_IS_INDEPENDENT
ADC_IS_SOFTWARE_START_INJECTED
ADC_JSQR_RK
ADC_MULTI_SLAVE
ADC_OFFSET_SHIFT_RESOLUTION
ADC_TEMPERATURE_SENSOR_INSTANCE
ADC_VREFINT_INSTANCE
IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE
IS_ADC_ANALOG_WATCHDOG_MODE
IS_ADC_ANALOG_WATCHDOG_NUMBER
IS_ADC_CALFACT
IS_ADC_CHANNEL
IS_ADC_CONVERSION_GROUP
IS_ADC_DFSDMCFG_MODE
IS_ADC_DIFF_CHANNEL
IS_ADC_DMA_ACCESS_MULTIMODE
IS_ADC_EVENT_TYPE
IS_ADC_EXTTRIGINJEC
IS_ADC_EXTTRIGINJEC_EDGE
IS_ADC_INJECTED_NB_CONV
IS_ADC_INJECTED_RANK
IS_ADC_MULTIMODE
IS_ADC_OFFSET_NUMBER
IS_ADC_OFFSET_SIGN
IS_ADC_OVERSAMPLING_RATIO
IS_ADC_REGOVERSAMPLING_MODE
IS_ADC_RIGHT_BIT_SHIFT
IS_ADC_SAMPLING_DELAY
IS_ADC_SINGLE_DIFFERENTIAL
IS_ADC_TRIGGERED_OVERSAMPLING_MODE
COMP
HAL_COMP_Init
HAL_COMP_MspDeInit
HAL_COMP_MspInit
HAL_COMP_RegisterCallback
HAL_COMP_UnRegisterCallback
Start-Stop operation functions
HAL_COMP_Start
HAL_COMP_Stop
Peripheral Control functions
HAL_COMP_Lock
HAL_COMP_TriggerCallback
Peripheral State functions
HAL_COMP_GetState
COMP Exported Types
Typedefs
pCOMP_CallbackTypeDef
Enumerations
HAL_COMP_StateTypeDef
Data Structures
__COMP_HandleTypeDef
COMP Exported Constants
HAL_COMP_ERROR_NONE
COMP input plus (non-inverting input)
COMP_INPUT_PLUS_IO2
COMP input minus (inverting input)
COMP_INPUT_MINUS_1_4VREFINT
COMP_INPUT_MINUS_3_4VREFINT
COMP_INPUT_MINUS_DAC1_CH1
COMP_INPUT_MINUS_DAC1_CH2
COMP_INPUT_MINUS_DAC2_CH1
COMP_INPUT_MINUS_DAC3_CH1
COMP_INPUT_MINUS_DAC3_CH2
COMP_INPUT_MINUS_DAC4_CH1
COMP_INPUT_MINUS_DAC4_CH2
COMP_INPUT_MINUS_IO1
COMP_INPUT_MINUS_IO2
COMP_INPUT_MINUS_VREFINT
COMP hysteresis
COMP_HYSTERESIS_20MV
COMP_HYSTERESIS_30MV
COMP_HYSTERESIS_40MV
COMP_HYSTERESIS_50MV
COMP_HYSTERESIS_60MV
COMP_HYSTERESIS_70MV
COMP_HYSTERESIS_HIGH
COMP_HYSTERESIS_LOW
COMP_HYSTERESIS_MEDIUM
COMP_HYSTERESIS_NONE
COMP output Polarity
COMP_OUTPUTPOL_NONINVERTED
COMP blanking source
COMP_BLANKINGSRC_TIM15_OC1
COMP_BLANKINGSRC_TIM15_OC1_COMP4
COMP_BLANKINGSRC_TIM15_OC2_COMP6
COMP_BLANKINGSRC_TIM15_OC2_COMP7
COMP_BLANKINGSRC_TIM1_OC5_COMP1
COMP_BLANKINGSRC_TIM1_OC5_COMP2
COMP_BLANKINGSRC_TIM1_OC5_COMP3
COMP_BLANKINGSRC_TIM1_OC5_COMP4
COMP_BLANKINGSRC_TIM1_OC5_COMP5
COMP_BLANKINGSRC_TIM1_OC5_COMP6
COMP_BLANKINGSRC_TIM1_OC5_COMP7
COMP_BLANKINGSRC_TIM20_OC5
COMP_BLANKINGSRC_TIM2_OC3_COMP1
COMP_BLANKINGSRC_TIM2_OC3_COMP2
COMP_BLANKINGSRC_TIM2_OC3_COMP5
COMP_BLANKINGSRC_TIM2_OC4_COMP3
COMP_BLANKINGSRC_TIM2_OC4_COMP6
COMP_BLANKINGSRC_TIM3_OC3_COMP1
COMP_BLANKINGSRC_TIM3_OC3_COMP2
COMP_BLANKINGSRC_TIM3_OC3_COMP3
COMP_BLANKINGSRC_TIM3_OC3_COMP5
COMP_BLANKINGSRC_TIM3_OC3_COMP7
COMP_BLANKINGSRC_TIM3_OC4_COMP4
COMP_BLANKINGSRC_TIM4_OC3
COMP_BLANKINGSRC_TIM8_OC5_COMP1
COMP_BLANKINGSRC_TIM8_OC5_COMP2
COMP_BLANKINGSRC_TIM8_OC5_COMP3
COMP_BLANKINGSRC_TIM8_OC5_COMP4
COMP_BLANKINGSRC_TIM8_OC5_COMP5
COMP_BLANKINGSRC_TIM8_OC5_COMP6
COMP_BLANKINGSRC_TIM8_OC5_COMP7
COMP Output Level
COMP_OUTPUT_LEVEL_LOW
COMP output to EXTI
COMP_TRIGGERMODE_EVENT_RISING
COMP_TRIGGERMODE_EVENT_RISING_FALLING
COMP_TRIGGERMODE_IT_FALLING
COMP_TRIGGERMODE_IT_RISING
COMP_TRIGGERMODE_IT_RISING_FALLING
COMP_TRIGGERMODE_NONE
COMP Exported Macros
__HAL_COMP_ENABLE
__HAL_COMP_IS_LOCKED
__HAL_COMP_LOCK
__HAL_COMP_RESET_HANDLE_STATE
COMP_CLEAR_ERRORCODE
COMP external interrupt line management
__HAL_COMP_COMP1_EXTI_DISABLE_EVENT
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_DISABLE_IT
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_EVENT
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_IT
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_GENERATE_SWIT
__HAL_COMP_COMP1_EXTI_GET_FLAG
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG
__HAL_COMP_COMP2_EXTI_DISABLE_EVENT
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_DISABLE_IT
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_EVENT
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_IT
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_GENERATE_SWIT
__HAL_COMP_COMP2_EXTI_GET_FLAG
__HAL_COMP_COMP3_EXTI_CLEAR_FLAG
__HAL_COMP_COMP3_EXTI_DISABLE_EVENT
__HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_DISABLE_IT
__HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_EVENT
__HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_IT
__HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_GENERATE_SWIT
__HAL_COMP_COMP3_EXTI_GET_FLAG
__HAL_COMP_COMP4_EXTI_CLEAR_FLAG
__HAL_COMP_COMP4_EXTI_DISABLE_EVENT
__HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_DISABLE_IT
__HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_EVENT
__HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_IT
__HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_GENERATE_SWIT
__HAL_COMP_COMP4_EXTI_GET_FLAG
__HAL_COMP_COMP5_EXTI_CLEAR_FLAG
__HAL_COMP_COMP5_EXTI_DISABLE_EVENT
__HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_DISABLE_IT
__HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_EVENT
__HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_IT
__HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_GENERATE_SWIT
__HAL_COMP_COMP5_EXTI_GET_FLAG
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG
__HAL_COMP_COMP6_EXTI_DISABLE_EVENT
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_DISABLE_IT
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_EVENT
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_IT
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_GENERATE_SWIT
__HAL_COMP_COMP6_EXTI_GET_FLAG
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG
__HAL_COMP_COMP7_EXTI_DISABLE_EVENT
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_DISABLE_IT
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_EVENT
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_IT
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_GENERATE_SWIT
__HAL_COMP_COMP7_EXTI_GET_FLAG
COMP Private Constants
COMP_EXTI_FALLING
COMP_EXTI_IT
COMP_EXTI_LINE_COMP1
COMP_EXTI_LINE_COMP2
COMP_EXTI_LINE_COMP3
COMP_EXTI_LINE_COMP4
COMP_EXTI_LINE_COMP5
COMP_EXTI_LINE_COMP6
COMP_EXTI_LINE_COMP7
COMP_EXTI_RISING
Defines
COMP_DELAY_VOLTAGE_SCALER_STAB_US
COMP_OUTPUT_LEVEL_BITOFFSET_POS
COMP Private Macros
COMP private macros to check input parameters
IS_COMP_BLANKINGSRCE
IS_COMP_HYSTERESIS
IS_COMP_INPUT_MINUS
IS_COMP_INPUT_PLUS
IS_COMP_OUTPUT_LEVEL
IS_COMP_OUTPUTPOL
IS_COMP_TRIGGERMODE
CORDIC
CORDIC_DMAInCplt
CORDIC_DMAOutCplt
CORDIC_ReadOutDataIncrementPtr
CORDIC_WriteInDataIncrementPtr
CORDIC Exported Functions
HAL_CORDIC_Init
HAL_CORDIC_MspDeInit
HAL_CORDIC_MspInit
HAL_CORDIC_RegisterCallback
HAL_CORDIC_RegisterCallback
HAL_CORDIC_UnRegisterCallback
Peripheral Control functions
HAL_CORDIC_Calculate_DMA
HAL_CORDIC_Calculate_IT
HAL_CORDIC_CalculateZO
HAL_CORDIC_Configure
Callback functions
HAL_CORDIC_ErrorCallback
IRQ handler management
Peripheral State functions
HAL_CORDIC_GetState
CORDIC Exported Types
pCORDIC_CallbackTypeDef
Enumerations
HAL_CORDIC_StateTypeDef
Data Structures
CORDIC_ConfigTypeDef
CORDIC Exported Constants
HAL_CORDIC_ERROR_INVALID_CALLBACK
HAL_CORDIC_ERROR_NONE
HAL_CORDIC_ERROR_NOT_READY
HAL_CORDIC_ERROR_PARAM
HAL_CORDIC_ERROR_TIMEOUT
CORDIC Function
CORDIC_FUNCTION_COSINE
CORDIC_FUNCTION_HARCTANGENT
CORDIC_FUNCTION_HCOSINE
CORDIC_FUNCTION_HSINE
CORDIC_FUNCTION_MODULUS
CORDIC_FUNCTION_NATURALLOG
CORDIC_FUNCTION_PHASE
CORDIC_FUNCTION_SINE
CORDIC_FUNCTION_SQUAREROOT
CORDIC Precision in Cycles Number
CORDIC_PRECISION_11CYCLES
CORDIC_PRECISION_12CYCLES
CORDIC_PRECISION_13CYCLES
CORDIC_PRECISION_14CYCLES
CORDIC_PRECISION_15CYCLES
CORDIC_PRECISION_1CYCLE
CORDIC_PRECISION_2CYCLES
CORDIC_PRECISION_3CYCLES
CORDIC_PRECISION_4CYCLES
CORDIC_PRECISION_5CYCLES
CORDIC_PRECISION_6CYCLES
CORDIC_PRECISION_7CYCLES
CORDIC_PRECISION_8CYCLES
CORDIC_PRECISION_9CYCLES
CORDIC Scaling factor
CORDIC_SCALE_1
CORDIC_SCALE_2
CORDIC_SCALE_3
CORDIC_SCALE_4
CORDIC_SCALE_5
CORDIC_SCALE_6
CORDIC_SCALE_7
CORDIC Interrupts Enable bit
DMA Read Request Enable bit
DMA Write Request Enable bit
CORDIC Number of 32-bit write required for one calculation
CORDIC_NBWRITE_2
CORDIC Number of 32-bit read required after one calculation
CORDIC_NBREAD_2
CORDIC input data size
CORDIC_INSIZE_32BITS
CORDIC Results Size
CORDIC_OUTSIZE_32BITS
CORDIC status flags
CORDIC DMA direction
CORDIC_DMA_DIR_IN_OUT
CORDIC_DMA_DIR_NONE
CORDIC_DMA_DIR_OUT
CORDIC Exported Macros
__HAL_CORDIC_CLEAR_IT
__HAL_CORDIC_DISABLE_IT
__HAL_CORDIC_ENABLE_IT
__HAL_CORDIC_GET_FLAG
__HAL_CORDIC_GET_IT
__HAL_CORDIC_GET_IT_SOURCE
__HAL_CORDIC_RESET_HANDLE_STATE
CORDIC Private Macros
IS_CORDIC_FUNCTION
IS_CORDIC_INSIZE
IS_CORDIC_NBREAD
IS_CORDIC_NBWRITE
IS_CORDIC_OUTSIZE
IS_CORDIC_PRECISION
IS_CORDIC_SCALE
CORTEX
CORTEX Exported Constants
NVIC_PRIORITYGROUP_1
NVIC_PRIORITYGROUP_2
NVIC_PRIORITYGROUP_3
NVIC_PRIORITYGROUP_4
CORTEX SysTick clock source
SYSTICK_CLKSOURCE_HCLK_DIV8
CORTEX MPU HFNMI and PRIVILEGED Access control
MPU_HFNMI_PRIVDEF
MPU_HFNMI_PRIVDEF_NONE
MPU_PRIVILEGED_DEFAULT
CORTEX MPU Region Enable
MPU_REGION_ENABLE
CORTEX MPU Instruction Access
MPU_INSTRUCTION_ACCESS_ENABLE
CORTEX MPU Instruction Access Shareable
MPU_ACCESS_SHAREABLE
CORTEX MPU Instruction Access Cacheable
MPU_ACCESS_NOT_CACHEABLE
CORTEX MPU Instruction Access Bufferable
MPU_ACCESS_NOT_BUFFERABLE
CORTEX MPU TEX Levels
MPU_TEX_LEVEL1
MPU_TEX_LEVEL2
MPU_TEX_LEVEL4
CORTEX MPU Region Size
MPU_REGION_SIZE_128KB
MPU_REGION_SIZE_128MB
MPU_REGION_SIZE_16KB
MPU_REGION_SIZE_16MB
MPU_REGION_SIZE_1GB
MPU_REGION_SIZE_1KB
MPU_REGION_SIZE_1MB
MPU_REGION_SIZE_256B
MPU_REGION_SIZE_256KB
MPU_REGION_SIZE_256MB
MPU_REGION_SIZE_2GB
MPU_REGION_SIZE_2KB
MPU_REGION_SIZE_2MB
MPU_REGION_SIZE_32B
MPU_REGION_SIZE_32KB
MPU_REGION_SIZE_32MB
MPU_REGION_SIZE_4GB
MPU_REGION_SIZE_4KB
MPU_REGION_SIZE_4MB
MPU_REGION_SIZE_512B
MPU_REGION_SIZE_512KB
MPU_REGION_SIZE_512MB
MPU_REGION_SIZE_64B
MPU_REGION_SIZE_64KB
MPU_REGION_SIZE_64MB
MPU_REGION_SIZE_8KB
MPU_REGION_SIZE_8MB
CORTEX MPU Region Permission Attributes
MPU_REGION_NO_ACCESS
MPU_REGION_PRIV_RO
MPU_REGION_PRIV_RO_URO
MPU_REGION_PRIV_RW
MPU_REGION_PRIV_RW_URO
CORTEX MPU Region Number
MPU_REGION_NUMBER1
MPU_REGION_NUMBER2
MPU_REGION_NUMBER3
MPU_REGION_NUMBER4
MPU_REGION_NUMBER5
MPU_REGION_NUMBER6
MPU_REGION_NUMBER7
CORTEX Exported Macros
CORTEX Exported Functions
HAL_NVIC_EnableIRQ
HAL_NVIC_SetPriority
HAL_NVIC_SetPriorityGrouping
HAL_NVIC_SystemReset
HAL_SYSTICK_Config
Peripheral Control functions
HAL_MPU_Disable
HAL_MPU_DisableRegion
HAL_MPU_Enable
HAL_MPU_EnableRegion
HAL_NVIC_ClearPendingIRQ
HAL_NVIC_GetActive
HAL_NVIC_GetPendingIRQ
HAL_NVIC_GetPriority
HAL_NVIC_GetPriorityGrouping
HAL_NVIC_SetPendingIRQ
HAL_SYSTICK_Callback
HAL_SYSTICK_CLKSourceConfig
HAL_SYSTICK_IRQHandler
CORTEX Private Macros
IS_MPU_ACCESS_CACHEABLE
IS_MPU_ACCESS_SHAREABLE
IS_MPU_INSTRUCTION_ACCESS
IS_MPU_REGION_ENABLE
IS_MPU_REGION_NUMBER
IS_MPU_REGION_PERMISSION_ATTRIBUTE
IS_MPU_REGION_SIZE
IS_MPU_SUB_REGION_DISABLE
IS_MPU_TEX_LEVEL
IS_NVIC_DEVICE_IRQ
IS_NVIC_PREEMPTION_PRIORITY
IS_NVIC_PRIORITY_GROUP
IS_NVIC_SUB_PRIORITY
IS_SYSTICK_CLK_SOURCE
CRC
CRC_Handle_8
CRC Exported Functions
HAL_CRC_Init
HAL_CRC_MspDeInit
HAL_CRC_MspInit
Peripheral Control functions
HAL_CRC_Calculate
Peripheral State functions
CRC Exported Types
Data Structures
CRC_HandleTypeDef
CRC Exported Constants
Default CRC computation initialization value
Indicates whether or not default polynomial is used
DEFAULT_POLYNOMIAL_ENABLE
Indicates whether or not default init value is used
DEFAULT_INIT_VALUE_ENABLE
Polynomial sizes to configure the peripheral
CRC_POLYLENGTH_32B
CRC_POLYLENGTH_7B
CRC_POLYLENGTH_8B
CRC polynomial possible sizes actual definitions
HAL_CRC_LENGTH_32B
HAL_CRC_LENGTH_7B
HAL_CRC_LENGTH_8B
Input Buffer Format
CRC_INPUTDATA_FORMAT_HALFWORDS
CRC_INPUTDATA_FORMAT_UNDEFINED
CRC_INPUTDATA_FORMAT_WORDS
CRC Exported Macros
__HAL_CRC_GET_IDR
__HAL_CRC_INITIALCRCVALUE_CONFIG
__HAL_CRC_RESET_HANDLE_STATE
__HAL_CRC_SET_IDR
CRC Private Macros
IS_CRC_POL_LENGTH
IS_DEFAULT_INIT_VALUE
IS_DEFAULT_POLYNOMIAL
CRCEx
HAL_CRCEx_Output_Data_Reverse
HAL_CRCEx_Polynomial_Set
CRC Extended Exported Constants
CRC_INPUTDATA_INVERSION_HALFWORD
CRC_INPUTDATA_INVERSION_NONE
CRC_INPUTDATA_INVERSION_WORD
Output Data Inversion Modes
CRC_OUTPUTDATA_INVERSION_ENABLE
CRC Extended Exported Macros
__HAL_CRC_OUTPUTREVERSAL_ENABLE
__HAL_CRC_POLYNOMIAL_CONFIG
CRC Extended Private Macros
IS_CRC_OUTPUTDATA_INVERSION_MODE
DAC
HAL_DAC_Init
HAL_DAC_MspDeInit
HAL_DAC_MspInit
HAL_DAC_RegisterCallback
HAL_DAC_UnRegisterCallback
IO operation functions
HAL_DAC_ConvHalfCpltCallbackCh1
HAL_DAC_DMAUnderrunCallbackCh1
HAL_DAC_ErrorCallbackCh1
HAL_DAC_IRQHandler
HAL_DAC_RegisterCallback
HAL_DAC_SetValue
HAL_DAC_Start
HAL_DAC_Start_DMA
HAL_DAC_Stop
HAL_DAC_Stop_DMA
HAL_DAC_UnRegisterCallback
Peripheral Control functions
HAL_DAC_GetValue
Peripheral State and Errors functions
HAL_DAC_GetState
DAC Exported Types
pDAC_CallbackTypeDef
Enumerations
HAL_DAC_StateTypeDef
Data Structures
DAC_SampleAndHoldConfTypeDef
DAC_ChannelConfTypeDef
DAC Exported Constants
HAL_DAC_ERROR_DMAUNDERRUNCH1
HAL_DAC_ERROR_DMAUNDERRUNCH2
HAL_DAC_ERROR_INVALID_CALLBACK
HAL_DAC_ERROR_NONE
HAL_DAC_ERROR_TIMEOUT
DAC trigger selection
DAC_TRIGGER_EXT_IT9
DAC_TRIGGER_HRTIM_RST_TRG1
DAC_TRIGGER_HRTIM_RST_TRG2
DAC_TRIGGER_HRTIM_RST_TRG3
DAC_TRIGGER_HRTIM_RST_TRG4
DAC_TRIGGER_HRTIM_RST_TRG5
DAC_TRIGGER_HRTIM_RST_TRG6
DAC_TRIGGER_HRTIM_STEP_TRG1
DAC_TRIGGER_HRTIM_STEP_TRG2
DAC_TRIGGER_HRTIM_STEP_TRG3
DAC_TRIGGER_HRTIM_STEP_TRG4
DAC_TRIGGER_HRTIM_STEP_TRG5
DAC_TRIGGER_HRTIM_STEP_TRG6
DAC_TRIGGER_HRTIM_TRG01
DAC_TRIGGER_HRTIM_TRG02
DAC_TRIGGER_HRTIM_TRG03
DAC_TRIGGER_NONE
DAC_TRIGGER_SOFTWARE
DAC_TRIGGER_T15_TRGO
DAC_TRIGGER_T1_TRGO
DAC_TRIGGER_T2_TRGO
DAC_TRIGGER_T3_TRGO
DAC_TRIGGER_T4_TRGO
DAC_TRIGGER_T6_TRGO
DAC_TRIGGER_T7_TRGO
DAC_TRIGGER_T8_TRGO
DAC output buffer
DAC_OUTPUTBUFFER_ENABLE
DAC Channel selection
DAC_CHANNEL_2
DAC data alignment
DAC_ALIGN_12B_R
DAC_ALIGN_8B_R
DAC flags definition
DAC_FLAG_DAC2RDY
DAC_FLAG_DMAUDR1
DAC_FLAG_DMAUDR2
DAC IT definition
DAC_IT_DMAUDR2
DAC ConnectOnChipPeripheral
DAC_CHIPCONNECT_EXTERNAL
DAC_CHIPCONNECT_INTERNAL
DAC User Trimming
DAC_TRIMMING_USER
DAC power mode
DAC_SAMPLEANDHOLD_ENABLE
DAC high frequency interface mode
DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ
DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC
DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE
DAC Exported Macros
__HAL_DAC_DISABLE
__HAL_DAC_DISABLE_IT
__HAL_DAC_ENABLE
__HAL_DAC_ENABLE_IT
__HAL_DAC_GET_FLAG
__HAL_DAC_GET_IT_SOURCE
__HAL_DAC_RESET_HANDLE_STATE
DAC_DHR12R1_ALIGNMENT
DAC_DHR12R2_ALIGNMENT
DAC_DHR12RD_ALIGNMENT
DAC Private Macros
IS_DAC_CHANNEL
IS_DAC_DATA
IS_DAC_OUTPUT_BUFFER_STATE
IS_DAC_REFRESHTIME
DAC Private Functions
DAC_DMAErrorCh1
DAC_DMAHalfConvCpltCh1
DAC Private Constants
HFSEL_ENABLE_THRESHOLD_80MHZ
TIMEOUT_DAC_CALIBCONFIG
Defines
DACEx
HAL_DACEx_ConvHalfCpltCallbackCh2
HAL_DACEx_DMAUnderrunCallbackCh2
HAL_DACEx_DualGetValue
HAL_DACEx_DualSetValue
HAL_DACEx_DualStart
HAL_DACEx_DualStart_DMA
HAL_DACEx_DualStop
HAL_DACEx_DualStop_DMA
HAL_DACEx_ErrorCallbackCh2
HAL_DACEx_GetTrimOffset
HAL_DACEx_NoiseWaveGenerate
HAL_DACEx_SawtoothWaveDataReset
HAL_DACEx_SawtoothWaveDataStep
HAL_DACEx_SawtoothWaveGenerate
HAL_DACEx_SelfCalibrate
HAL_DACEx_SetUserTrimming
HAL_DACEx_TriangleWaveGenerate
Peripheral Control functions
HAL_DACEx_GetTrimOffset
HAL_DACEx_SelfCalibrate
HAL_DACEx_SetUserTrimming
DACEx private functions
DAC_DMAErrorCh2
DAC_DMAHalfConvCpltCh2
DACEx Exported Constants
DAC_LFSRUNMASK_BITS10_0
DAC_LFSRUNMASK_BITS11_0
DAC_LFSRUNMASK_BITS1_0
DAC_LFSRUNMASK_BITS2_0
DAC_LFSRUNMASK_BITS3_0
DAC_LFSRUNMASK_BITS4_0
DAC_LFSRUNMASK_BITS5_0
DAC_LFSRUNMASK_BITS6_0
DAC_LFSRUNMASK_BITS7_0
DAC_LFSRUNMASK_BITS8_0
DAC_LFSRUNMASK_BITS9_0
DAC_TRIANGLEAMPLITUDE_1
DAC_TRIANGLEAMPLITUDE_1023
DAC_TRIANGLEAMPLITUDE_127
DAC_TRIANGLEAMPLITUDE_15
DAC_TRIANGLEAMPLITUDE_2047
DAC_TRIANGLEAMPLITUDE_255
DAC_TRIANGLEAMPLITUDE_3
DAC_TRIANGLEAMPLITUDE_31
DAC_TRIANGLEAMPLITUDE_4095
DAC_TRIANGLEAMPLITUDE_511
DAC_TRIANGLEAMPLITUDE_63
DAC_TRIANGLEAMPLITUDE_7
DAC Sawtooth polarity mode
DAC_SAWTOOTH_POLARITY_INCREMENT
DACEx Private Macros
IS_DAC_HIGH_FREQUENCY_MODE
IS_DAC_HOLDTIME
IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE
IS_DAC_NEWTRIMMINGVALUE
IS_DAC_RESET_DATA
IS_DAC_SAMPLEANDHOLD
IS_DAC_SAMPLETIME
IS_DAC_SAWTOOTH_POLARITY
IS_DAC_STEP_DATA
IS_DAC_TRIGGER
IS_DAC_TRIGGER2
IS_DAC_TRIMMING
IS_DAC_TRIMMINGVALUE
Defines
DMA
DMA_CalcDMAMUXRequestGenBaseAndMask
DMA_SetConfig
DMA Exported Functions
HAL_DMA_Init
Input and Output operation functions
HAL_DMA_Abort_IT
HAL_DMA_IRQHandler
HAL_DMA_PollForTransfer
HAL_DMA_RegisterCallback
HAL_DMA_Start
HAL_DMA_Start_IT
HAL_DMA_UnRegisterCallback
Peripheral State and Errors functions
HAL_DMA_GetState
DMA Exported Types
Enumerations
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_StateTypeDef
Data Structures
__DMA_HandleTypeDef
DMA Exported Constants
HAL_DMA_ERROR_NONE
HAL_DMA_ERROR_NOT_SUPPORTED
HAL_DMA_ERROR_REQGEN
HAL_DMA_ERROR_SYNC
HAL_DMA_ERROR_TE
HAL_DMA_ERROR_TIMEOUT
DMA request
DMA_REQUEST_ADC2
DMA_REQUEST_ADC3
DMA_REQUEST_ADC4
DMA_REQUEST_ADC5
DMA_REQUEST_AES_IN
DMA_REQUEST_AES_OUT
DMA_REQUEST_CORDIC_READ
DMA_REQUEST_CORDIC_WRITE
DMA_REQUEST_DAC1_CHANNEL1
DMA_REQUEST_DAC1_CHANNEL2
DMA_REQUEST_DAC2_CHANNEL1
DMA_REQUEST_DAC3_CHANNEL1
DMA_REQUEST_DAC3_CHANNEL2
DMA_REQUEST_DAC4_CHANNEL1
DMA_REQUEST_DAC4_CHANNEL2
DMA_REQUEST_FMAC_READ
DMA_REQUEST_FMAC_WRITE
DMA_REQUEST_GENERATOR0
DMA_REQUEST_GENERATOR1
DMA_REQUEST_GENERATOR2
DMA_REQUEST_GENERATOR3
DMA_REQUEST_HRTIM1_A
DMA_REQUEST_HRTIM1_B
DMA_REQUEST_HRTIM1_C
DMA_REQUEST_HRTIM1_D
DMA_REQUEST_HRTIM1_E
DMA_REQUEST_HRTIM1_F
DMA_REQUEST_HRTIM1_M
DMA_REQUEST_I2C1_RX
DMA_REQUEST_I2C1_TX
DMA_REQUEST_I2C2_RX
DMA_REQUEST_I2C2_TX
DMA_REQUEST_I2C3_RX
DMA_REQUEST_I2C3_TX
DMA_REQUEST_I2C4_RX
DMA_REQUEST_I2C4_TX
DMA_REQUEST_LPUART1_RX
DMA_REQUEST_LPUART1_TX
DMA_REQUEST_MEM2MEM
DMA_REQUEST_QUADSPI
DMA_REQUEST_SAI1_A
DMA_REQUEST_SAI1_B
DMA_REQUEST_SPI1_RX
DMA_REQUEST_SPI1_TX
DMA_REQUEST_SPI2_RX
DMA_REQUEST_SPI2_TX
DMA_REQUEST_SPI3_RX
DMA_REQUEST_SPI3_TX
DMA_REQUEST_SPI4_RX
DMA_REQUEST_SPI4_TX
DMA_REQUEST_TIM15_CH1
DMA_REQUEST_TIM15_COM
DMA_REQUEST_TIM15_TRIG
DMA_REQUEST_TIM15_UP
DMA_REQUEST_TIM16_CH1
DMA_REQUEST_TIM16_UP
DMA_REQUEST_TIM17_CH1
DMA_REQUEST_TIM17_UP
DMA_REQUEST_TIM1_CH1
DMA_REQUEST_TIM1_CH2
DMA_REQUEST_TIM1_CH3
DMA_REQUEST_TIM1_CH4
DMA_REQUEST_TIM1_COM
DMA_REQUEST_TIM1_TRIG
DMA_REQUEST_TIM1_UP
DMA_REQUEST_TIM20_CH1
DMA_REQUEST_TIM20_CH2
DMA_REQUEST_TIM20_CH3
DMA_REQUEST_TIM20_CH4
DMA_REQUEST_TIM20_COM
DMA_REQUEST_TIM20_TRIG
DMA_REQUEST_TIM20_UP
DMA_REQUEST_TIM2_CH1
DMA_REQUEST_TIM2_CH2
DMA_REQUEST_TIM2_CH3
DMA_REQUEST_TIM2_CH4
DMA_REQUEST_TIM2_UP
DMA_REQUEST_TIM3_CH1
DMA_REQUEST_TIM3_CH2
DMA_REQUEST_TIM3_CH3
DMA_REQUEST_TIM3_CH4
DMA_REQUEST_TIM3_TRIG
DMA_REQUEST_TIM3_UP
DMA_REQUEST_TIM4_CH1
DMA_REQUEST_TIM4_CH2
DMA_REQUEST_TIM4_CH3
DMA_REQUEST_TIM4_CH4
DMA_REQUEST_TIM4_UP
DMA_REQUEST_TIM5_CH1
DMA_REQUEST_TIM5_CH2
DMA_REQUEST_TIM5_CH3
DMA_REQUEST_TIM5_CH4
DMA_REQUEST_TIM5_TRIG
DMA_REQUEST_TIM5_UP
DMA_REQUEST_TIM6_UP
DMA_REQUEST_TIM7_UP
DMA_REQUEST_TIM8_CH1
DMA_REQUEST_TIM8_CH2
DMA_REQUEST_TIM8_CH3
DMA_REQUEST_TIM8_CH4
DMA_REQUEST_TIM8_COM
DMA_REQUEST_TIM8_TRIG
DMA_REQUEST_TIM8_UP
DMA_REQUEST_UART4_RX
DMA_REQUEST_UART4_TX
DMA_REQUEST_UART5_RX
DMA_REQUEST_UART5_TX
DMA_REQUEST_UCPD1_RX
DMA_REQUEST_UCPD1_TX
DMA_REQUEST_USART1_RX
DMA_REQUEST_USART1_TX
DMA_REQUEST_USART2_RX
DMA_REQUEST_USART2_TX
DMA_REQUEST_USART3_RX
DMA_REQUEST_USART3_TX
DMA Data transfer direction
DMA_MEMORY_TO_PERIPH
DMA_PERIPH_TO_MEMORY
DMA Peripheral incremented mode
DMA_PINC_ENABLE
DMA Memory incremented mode
DMA_MINC_ENABLE
DMA Peripheral data size
DMA_PDATAALIGN_HALFWORD
DMA_PDATAALIGN_WORD
DMA Memory data size
DMA_MDATAALIGN_HALFWORD
DMA_MDATAALIGN_WORD
DMA mode
DMA_NORMAL
DMA Priority level
DMA_PRIORITY_LOW
DMA_PRIORITY_MEDIUM
DMA_PRIORITY_VERY_HIGH
DMA interrupt enable definitions
DMA_IT_TC
DMA_IT_TE
DMA flag definitions
DMA_FLAG_GL2
DMA_FLAG_GL3
DMA_FLAG_GL4
DMA_FLAG_GL5
DMA_FLAG_GL6
DMA_FLAG_GL7
DMA_FLAG_GL8
DMA_FLAG_HT1
DMA_FLAG_HT2
DMA_FLAG_HT3
DMA_FLAG_HT4
DMA_FLAG_HT5
DMA_FLAG_HT6
DMA_FLAG_HT7
DMA_FLAG_HT8
DMA_FLAG_TC1
DMA_FLAG_TC2
DMA_FLAG_TC3
DMA_FLAG_TC4
DMA_FLAG_TC5
DMA_FLAG_TC6
DMA_FLAG_TC7
DMA_FLAG_TC8
DMA_FLAG_TE1
DMA_FLAG_TE2
DMA_FLAG_TE3
DMA_FLAG_TE4
DMA_FLAG_TE5
DMA_FLAG_TE6
DMA_FLAG_TE7
DMA_FLAG_TE8
DMA Exported Macros
__HAL_DMA_DISABLE
__HAL_DMA_DISABLE_IT
__HAL_DMA_ENABLE
__HAL_DMA_ENABLE_IT
__HAL_DMA_GET_COUNTER
__HAL_DMA_GET_FLAG
__HAL_DMA_GET_GI_FLAG_INDEX
__HAL_DMA_GET_HT_FLAG_INDEX
__HAL_DMA_GET_IT_SOURCE
__HAL_DMA_GET_TC_FLAG_INDEX
__HAL_DMA_GET_TE_FLAG_INDEX
__HAL_DMA_RESET_HANDLE_STATE
DMA Private Macros
IS_DMA_BUFFER_SIZE
IS_DMA_DIRECTION
IS_DMA_MEMORY_DATA_SIZE
IS_DMA_MEMORY_INC_STATE
IS_DMA_MODE
IS_DMA_PERIPHERAL_DATA_SIZE
IS_DMA_PERIPHERAL_INC_STATE
IS_DMA_PRIORITY
DMAEx
HAL_DMAEx_ConfigMuxSync
HAL_DMAEx_DisableMuxRequestGenerator
HAL_DMAEx_EnableMuxRequestGenerator
HAL_DMAEx_MUX_IRQHandler
DMAEx Exported Types
HAL_DMA_MuxRequestGeneratorConfigTypeDef
DMAEx Exported Constants
HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT
HAL_DMAMUX1_SYNC_EXTI0
HAL_DMAMUX1_SYNC_EXTI1
HAL_DMAMUX1_SYNC_EXTI10
HAL_DMAMUX1_SYNC_EXTI11
HAL_DMAMUX1_SYNC_EXTI12
HAL_DMAMUX1_SYNC_EXTI13
HAL_DMAMUX1_SYNC_EXTI14
HAL_DMAMUX1_SYNC_EXTI15
HAL_DMAMUX1_SYNC_EXTI2
HAL_DMAMUX1_SYNC_EXTI3
HAL_DMAMUX1_SYNC_EXTI4
HAL_DMAMUX1_SYNC_EXTI5
HAL_DMAMUX1_SYNC_EXTI6
HAL_DMAMUX1_SYNC_EXTI7
HAL_DMAMUX1_SYNC_EXTI8
HAL_DMAMUX1_SYNC_EXTI9
HAL_DMAMUX1_SYNC_LPTIM1_OUT
DMAMUX SyncPolarity selection
HAL_DMAMUX_SYNC_NO_EVENT
HAL_DMAMUX_SYNC_RISING
HAL_DMAMUX_SYNC_RISING_FALLING
DMAMUX SignalGeneratorID selection
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
HAL_DMAMUX1_REQ_GEN_EXTI0
HAL_DMAMUX1_REQ_GEN_EXTI1
HAL_DMAMUX1_REQ_GEN_EXTI10
HAL_DMAMUX1_REQ_GEN_EXTI11
HAL_DMAMUX1_REQ_GEN_EXTI12
HAL_DMAMUX1_REQ_GEN_EXTI13
HAL_DMAMUX1_REQ_GEN_EXTI14
HAL_DMAMUX1_REQ_GEN_EXTI15
HAL_DMAMUX1_REQ_GEN_EXTI2
HAL_DMAMUX1_REQ_GEN_EXTI3
HAL_DMAMUX1_REQ_GEN_EXTI4
HAL_DMAMUX1_REQ_GEN_EXTI5
HAL_DMAMUX1_REQ_GEN_EXTI6
HAL_DMAMUX1_REQ_GEN_EXTI7
HAL_DMAMUX1_REQ_GEN_EXTI8
HAL_DMAMUX1_REQ_GEN_EXTI9
HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
DMAMUX RequestGeneneratorPolarity selection
HAL_DMAMUX_REQ_GEN_NO_EVENT
HAL_DMAMUX_REQ_GEN_RISING
HAL_DMAMUX_REQ_GEN_RISING_FALLING
DMAEx Private Macros
IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER
IS_DMAMUX_REQUEST_GEN_SIGNAL_ID
IS_DMAMUX_SYNC_EVENT
IS_DMAMUX_SYNC_POLARITY
IS_DMAMUX_SYNC_REQUEST_NUMBER
IS_DMAMUX_SYNC_SIGNAL_ID
IS_DMAMUX_SYNC_STATE
EXTI
EXTI_CONFIG_OFFSET
EXTI_DIRECT
EXTI_GPIO
EXTI_LINE_NB
EXTI_MODE_MASK
EXTI_MODE_OFFSET
EXTI_PIN_MASK
EXTI_PROPERTY_MASK
EXTI_PROPERTY_SHIFT
EXTI_REG1
EXTI_REG2
EXTI_REG_MASK
EXTI_REG_SHIFT
EXTI_RESERVED
EXTI_TRIGGER_MASK
EXTI Exported Types
Data Structures
EXTI_ConfigTypeDef
EXTI Exported Constants
EXTI_LINE_1
EXTI_LINE_10
EXTI_LINE_11
EXTI_LINE_12
EXTI_LINE_13
EXTI_LINE_14
EXTI_LINE_15
EXTI_LINE_16
EXTI_LINE_17
EXTI_LINE_18
EXTI_LINE_19
EXTI_LINE_2
EXTI_LINE_20
EXTI_LINE_21
EXTI_LINE_22
EXTI_LINE_23
EXTI_LINE_24
EXTI_LINE_25
EXTI_LINE_26
EXTI_LINE_27
EXTI_LINE_28
EXTI_LINE_29
EXTI_LINE_3
EXTI_LINE_30
EXTI_LINE_31
EXTI_LINE_32
EXTI_LINE_33
EXTI_LINE_34
EXTI_LINE_35
EXTI_LINE_36
EXTI_LINE_37
EXTI_LINE_38
EXTI_LINE_39
EXTI_LINE_4
EXTI_LINE_40
EXTI_LINE_41
EXTI_LINE_42
EXTI_LINE_43
EXTI_LINE_5
EXTI_LINE_6
EXTI_LINE_7
EXTI_LINE_8
EXTI_LINE_9
EXTI Mode
EXTI_MODE_INTERRUPT
EXTI_MODE_NONE
EXTI Trigger
EXTI_TRIGGER_NONE
EXTI_TRIGGER_RISING
EXTI_TRIGGER_RISING_FALLING
EXTI GPIOSel
EXTI_GPIOB
EXTI_GPIOC
EXTI_GPIOD
EXTI_GPIOE
EXTI_GPIOF
EXTI_GPIOG
EXTI Exported Macros
EXTI Private Macros
IS_EXTI_CONFIG_LINE
IS_EXTI_GPIO_PIN
IS_EXTI_GPIO_PORT
IS_EXTI_LINE
IS_EXTI_MODE
IS_EXTI_PENDING_EDGE
IS_EXTI_TRIGGER
EXTI Exported Functions
HAL_EXTI_GetConfigLine
HAL_EXTI_GetHandle
HAL_EXTI_RegisterCallback
HAL_EXTI_SetConfigLine
IO operation functions
HAL_EXTI_GenerateSWI
HAL_EXTI_GetPending
HAL_EXTI_IRQHandler
FDCAN
HAL_FDCAN_EnterPowerDownMode
HAL_FDCAN_ExitPowerDownMode
HAL_FDCAN_Init
HAL_FDCAN_MspDeInit
HAL_FDCAN_MspInit
HAL_FDCAN_RegisterCallback
HAL_FDCAN_RegisterCallback
HAL_FDCAN_RegisterErrorStatusCallback
HAL_FDCAN_RegisterRxFifo0Callback
HAL_FDCAN_RegisterRxFifo1Callback
HAL_FDCAN_RegisterTxBufferAbortCallback
HAL_FDCAN_RegisterTxBufferCompleteCallback
HAL_FDCAN_RegisterTxEventFifoCallback
HAL_FDCAN_UnRegisterCallback
HAL_FDCAN_UnRegisterErrorStatusCallback
HAL_FDCAN_UnRegisterRxFifo0Callback
HAL_FDCAN_UnRegisterRxFifo1Callback
HAL_FDCAN_UnRegisterTxBufferAbortCallback
HAL_FDCAN_UnRegisterTxBufferCompleteCallback
HAL_FDCAN_UnRegisterTxEventFifoCallback
Configuration functions
HAL_FDCAN_ConfigFilter
HAL_FDCAN_ConfigGlobalFilter
HAL_FDCAN_ConfigRamWatchdog
HAL_FDCAN_ConfigRxFifoOverwrite
HAL_FDCAN_ConfigTimeoutCounter
HAL_FDCAN_ConfigTimestampCounter
HAL_FDCAN_ConfigTxDelayCompensation
HAL_FDCAN_DisableEdgeFiltering
HAL_FDCAN_DisableISOMode
HAL_FDCAN_DisableTimeoutCounter
HAL_FDCAN_DisableTimestampCounter
HAL_FDCAN_DisableTxDelayCompensation
HAL_FDCAN_EnableEdgeFiltering
HAL_FDCAN_EnableISOMode
HAL_FDCAN_EnableTimeoutCounter
HAL_FDCAN_EnableTimestampCounter
HAL_FDCAN_EnableTxDelayCompensation
HAL_FDCAN_GetTimeoutCounter
HAL_FDCAN_GetTimestampCounter
HAL_FDCAN_ResetTimeoutCounter
HAL_FDCAN_ResetTimestampCounter
Control functions
HAL_FDCAN_AddMessageToTxFifoQ
HAL_FDCAN_ExitRestrictedOperationMode
HAL_FDCAN_GetErrorCounters
HAL_FDCAN_GetHighPriorityMessageStatus
HAL_FDCAN_GetLatestTxFifoQRequestBuffer
HAL_FDCAN_GetProtocolStatus
HAL_FDCAN_GetRxFifoFillLevel
HAL_FDCAN_GetRxMessage
HAL_FDCAN_GetTxEvent
HAL_FDCAN_GetTxFifoFreeLevel
HAL_FDCAN_IsRestrictedOperationMode
HAL_FDCAN_IsTxBufferMessagePending
HAL_FDCAN_Start
HAL_FDCAN_Stop
Interrupts management
HAL_FDCAN_ConfigInterruptLines
HAL_FDCAN_DeactivateNotification
HAL_FDCAN_IRQHandler
Callback functions
HAL_FDCAN_ErrorStatusCallback
HAL_FDCAN_HighPriorityMessageCallback
HAL_FDCAN_RxFifo0Callback
HAL_FDCAN_RxFifo1Callback
HAL_FDCAN_TimeoutOccurredCallback
HAL_FDCAN_TimestampWraparoundCallback
HAL_FDCAN_TxBufferAbortCallback
HAL_FDCAN_TxBufferCompleteCallback
HAL_FDCAN_TxEventFifoCallback
HAL_FDCAN_TxFifoEmptyCallback
Peripheral State functions
HAL_FDCAN_GetState
FDCAN Private Functions
FDCAN_CopyMessageToRAM
FDCAN Exported Types
pFDCAN_CallbackTypeDef
pFDCAN_ErrorStatusCallbackTypeDef
pFDCAN_RxFifo0CallbackTypeDef
pFDCAN_RxFifo1CallbackTypeDef
pFDCAN_TxBufferAbortCallbackTypeDef
pFDCAN_TxBufferCompleteCallbackTypeDef
pFDCAN_TxEventFifoCallbackTypeDef
Enumerations
HAL_FDCAN_StateTypeDef
Data Structures
FDCAN_FilterTypeDef
FDCAN_TxHeaderTypeDef
FDCAN_RxHeaderTypeDef
FDCAN_TxEventFifoTypeDef
FDCAN_HpMsgStatusTypeDef
FDCAN_ProtocolStatusTypeDef
FDCAN_ErrorCountersTypeDef
FDCAN_MsgRamAddressTypeDef
__FDCAN_HandleTypeDef
FDCAN Exported Constants
HAL_FDCAN_ERROR_FIFO_FULL
HAL_FDCAN_ERROR_INVALID_CALLBACK
HAL_FDCAN_ERROR_LOG_OVERFLOW
HAL_FDCAN_ERROR_NONE
HAL_FDCAN_ERROR_NOT_INITIALIZED
HAL_FDCAN_ERROR_NOT_READY
HAL_FDCAN_ERROR_NOT_STARTED
HAL_FDCAN_ERROR_NOT_SUPPORTED
HAL_FDCAN_ERROR_PARAM
HAL_FDCAN_ERROR_PENDING
HAL_FDCAN_ERROR_PROTOCOL_ARBT
HAL_FDCAN_ERROR_PROTOCOL_DATA
HAL_FDCAN_ERROR_RAM_ACCESS
HAL_FDCAN_ERROR_RAM_WDG
HAL_FDCAN_ERROR_RESERVED_AREA
HAL_FDCAN_ERROR_TIMEOUT
FDCAN Frame Format
FDCAN_FRAME_FD_BRS
FDCAN_FRAME_FD_NO_BRS
FDCAN Operating Mode
FDCAN_MODE_EXTERNAL_LOOPBACK
FDCAN_MODE_INTERNAL_LOOPBACK
FDCAN_MODE_NORMAL
FDCAN_MODE_RESTRICTED_OPERATION
FDCAN Clock Divider
FDCAN_CLOCK_DIV10
FDCAN_CLOCK_DIV12
FDCAN_CLOCK_DIV14
FDCAN_CLOCK_DIV16
FDCAN_CLOCK_DIV18
FDCAN_CLOCK_DIV2
FDCAN_CLOCK_DIV20
FDCAN_CLOCK_DIV22
FDCAN_CLOCK_DIV24
FDCAN_CLOCK_DIV26
FDCAN_CLOCK_DIV28
FDCAN_CLOCK_DIV30
FDCAN_CLOCK_DIV4
FDCAN_CLOCK_DIV6
FDCAN_CLOCK_DIV8
FDCAN Tx FIFO/Queue Mode
FDCAN_TX_QUEUE_OPERATION
FDCAN ID Type
FDCAN_STANDARD_ID
FDCAN Frame Type
FDCAN_REMOTE_FRAME
FDCAN Data Length Code
FDCAN_DLC_BYTES_1
FDCAN_DLC_BYTES_12
FDCAN_DLC_BYTES_16
FDCAN_DLC_BYTES_2
FDCAN_DLC_BYTES_20
FDCAN_DLC_BYTES_24
FDCAN_DLC_BYTES_3
FDCAN_DLC_BYTES_32
FDCAN_DLC_BYTES_4
FDCAN_DLC_BYTES_48
FDCAN_DLC_BYTES_5
FDCAN_DLC_BYTES_6
FDCAN_DLC_BYTES_64
FDCAN_DLC_BYTES_7
FDCAN_DLC_BYTES_8
FDCAN Error State Indicator
FDCAN_ESI_PASSIVE
FDCAN Bit Rate Switching
FDCAN_BRS_ON
FDCAN format
FDCAN_FD_CAN
FDCAN Event FIFO control
FDCAN_STORE_TX_EVENTS
FDCAN Filter Type
FDCAN_FILTER_MASK
FDCAN_FILTER_RANGE
FDCAN_FILTER_RANGE_NO_EIDM
FDCAN Filter Configuration
FDCAN_FILTER_HP
FDCAN_FILTER_REJECT
FDCAN_FILTER_TO_RXFIFO0
FDCAN_FILTER_TO_RXFIFO0_HP
FDCAN_FILTER_TO_RXFIFO1
FDCAN_FILTER_TO_RXFIFO1_HP
FDCAN Tx Location
FDCAN_TX_BUFFER1
FDCAN_TX_BUFFER2
FDCAN Rx Location
FDCAN_RX_FIFO1
FDCAN Event Type
FDCAN_TX_IN_SPITE_OF_ABORT
FDCAN High Priority Message Storage
FDCAN_HP_STORAGE_NO_FIFO
FDCAN_HP_STORAGE_RXFIFO0
FDCAN_HP_STORAGE_RXFIFO1
FDCAN protocol error code
FDCAN_PROTOCOL_ERROR_BIT0
FDCAN_PROTOCOL_ERROR_BIT1
FDCAN_PROTOCOL_ERROR_CRC
FDCAN_PROTOCOL_ERROR_FORM
FDCAN_PROTOCOL_ERROR_NO_CHANGE
FDCAN_PROTOCOL_ERROR_NONE
FDCAN_PROTOCOL_ERROR_STUFF
FDCAN communication state
FDCAN_COM_STATE_RX
FDCAN_COM_STATE_SYNC
FDCAN_COM_STATE_TX
FDCAN FIFO operation mode
FDCAN_RX_FIFO_OVERWRITE
FDCAN non-matching frames
FDCAN_ACCEPT_IN_RX_FIFO1
FDCAN_REJECT
FDCAN reject remote frames
FDCAN_REJECT_REMOTE
FDCAN interrupt line
FDCAN_INTERRUPT_LINE1
FDCAN timestamp
FDCAN_TIMESTAMP_INTERNAL
FDCAN timestamp prescaler
FDCAN_TIMESTAMP_PRESC_10
FDCAN_TIMESTAMP_PRESC_11
FDCAN_TIMESTAMP_PRESC_12
FDCAN_TIMESTAMP_PRESC_13
FDCAN_TIMESTAMP_PRESC_14
FDCAN_TIMESTAMP_PRESC_15
FDCAN_TIMESTAMP_PRESC_16
FDCAN_TIMESTAMP_PRESC_2
FDCAN_TIMESTAMP_PRESC_3
FDCAN_TIMESTAMP_PRESC_4
FDCAN_TIMESTAMP_PRESC_5
FDCAN_TIMESTAMP_PRESC_6
FDCAN_TIMESTAMP_PRESC_7
FDCAN_TIMESTAMP_PRESC_8
FDCAN_TIMESTAMP_PRESC_9
FDCAN timeout operation
FDCAN_TIMEOUT_RX_FIFO0
FDCAN_TIMEOUT_RX_FIFO1
FDCAN_TIMEOUT_TX_EVENT_FIFO
Interrupt masks
FDCAN_IR_MASK
FDCAN Flags
FDCAN_FLAG_BUS_OFF
FDCAN_FLAG_DATA_PROTOCOL_ERROR
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW
FDCAN_FLAG_ERROR_PASSIVE
FDCAN_FLAG_ERROR_WARNING
FDCAN_FLAG_RAM_ACCESS_FAILURE
FDCAN_FLAG_RAM_WATCHDOG
FDCAN_FLAG_RESERVED_ADDRESS_ACCESS
FDCAN_FLAG_RX_FIFO0_FULL
FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST
FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE
FDCAN_FLAG_RX_FIFO1_FULL
FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST
FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE
FDCAN_FLAG_RX_HIGH_PRIORITY_MSG
FDCAN_FLAG_TIMEOUT_OCCURRED
FDCAN_FLAG_TIMESTAMP_WRAPAROUND
FDCAN_FLAG_TX_ABORT_COMPLETE
FDCAN_FLAG_TX_COMPLETE
FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST
FDCAN_FLAG_TX_EVT_FIFO_FULL
FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA
FDCAN_FLAG_TX_FIFO_EMPTY
FDCAN Interrupts
FDCAN_IT_TX_COMPLETE
FDCAN_IT_TX_FIFO_EMPTY
FDCAN Rx Interrupts
FDCAN Counter Interrupts
FDCAN_IT_TIMESTAMP_WRAPAROUND
FDCAN Tx Event FIFO Interrupts
FDCAN_IT_TX_EVT_FIFO_FULL
FDCAN_IT_TX_EVT_FIFO_NEW_DATA
FDCAN Rx FIFO 0 Interrupts
FDCAN_IT_RX_FIFO0_MESSAGE_LOST
FDCAN_IT_RX_FIFO0_NEW_MESSAGE
FDCAN Rx FIFO 1 Interrupts
FDCAN_IT_RX_FIFO1_MESSAGE_LOST
FDCAN_IT_RX_FIFO1_NEW_MESSAGE
FDCAN Error Interrupts
FDCAN_IT_DATA_PROTOCOL_ERROR
FDCAN_IT_ERROR_LOGGING_OVERFLOW
FDCAN_IT_RAM_ACCESS_FAILURE
FDCAN_IT_RAM_WATCHDOG
FDCAN_IT_RESERVED_ADDRESS_ACCESS
FDCAN Error Status Interrupts
FDCAN_IT_ERROR_PASSIVE
FDCAN_IT_ERROR_WARNING
FDCAN Interrupts List
FDCAN_IT_LIST_MISC
FDCAN_IT_LIST_PROTOCOL_ERROR
FDCAN_IT_LIST_RX_FIFO0
FDCAN_IT_LIST_RX_FIFO1
FDCAN_IT_LIST_SMSG
FDCAN_IT_LIST_TX_FIFO_ERROR
FDCAN Interrupts Group
FDCAN_IT_GROUP_MISC
FDCAN_IT_GROUP_PROTOCOL_ERROR
FDCAN_IT_GROUP_RX_FIFO0
FDCAN_IT_GROUP_RX_FIFO1
FDCAN_IT_GROUP_SMSG
FDCAN_IT_GROUP_TX_FIFO_ERROR
FDCAN Exported Macros
__HAL_FDCAN_CLEAR_IT
__HAL_FDCAN_DISABLE_IT
__HAL_FDCAN_ENABLE_IT
__HAL_FDCAN_GET_FLAG
__HAL_FDCAN_GET_IT
__HAL_FDCAN_GET_IT_SOURCE
__HAL_FDCAN_RESET_HANDLE_STATE
FDCAN Private Variables
FDCAN Private Constants
FDCAN_ELEMENT_MASK_BRS
FDCAN_ELEMENT_MASK_DLC
FDCAN_ELEMENT_MASK_EFC
FDCAN_ELEMENT_MASK_ESI
FDCAN_ELEMENT_MASK_ET
FDCAN_ELEMENT_MASK_EXTID
FDCAN_ELEMENT_MASK_FDF
FDCAN_ELEMENT_MASK_FIDX
FDCAN_ELEMENT_MASK_MM
FDCAN_ELEMENT_MASK_RTR
FDCAN_ELEMENT_MASK_STDID
FDCAN_ELEMENT_MASK_TS
FDCAN_ELEMENT_MASK_XTD
FDCAN_ERROR_MASK
FDCAN_ERROR_STATUS_MASK
FDCAN_RX_FIFO0_MASK
FDCAN_RX_FIFO1_MASK
FDCAN_TIMEOUT_VALUE
FDCAN_TX_EVENT_FIFO_MASK
SRAMCAN_FLE_NBR
SRAMCAN_FLE_SIZE
SRAMCAN_FLESA
SRAMCAN_FLS_NBR
SRAMCAN_FLS_SIZE
SRAMCAN_FLSSA
SRAMCAN_RF0_NBR
SRAMCAN_RF0_SIZE
SRAMCAN_RF0SA
SRAMCAN_RF1_NBR
SRAMCAN_RF1_SIZE
SRAMCAN_RF1SA
SRAMCAN_SIZE
SRAMCAN_TEF_NBR
SRAMCAN_TEF_SIZE
SRAMCAN_TEFSA
SRAMCAN_TFQ_NBR
SRAMCAN_TFQ_SIZE
SRAMCAN_TFQSA
FDCAN Private Macros
FDCAN_CHECK_IT_SOURCE
IS_FDCAN_BRS
IS_FDCAN_CKDIV
IS_FDCAN_DATA_PRESCALER
IS_FDCAN_DATA_SJW
IS_FDCAN_DATA_TSEG1
IS_FDCAN_DATA_TSEG2
IS_FDCAN_DLC
IS_FDCAN_EFC
IS_FDCAN_ESI
IS_FDCAN_EXT_FILTER_TYPE
IS_FDCAN_FDF
IS_FDCAN_FILTER_CFG
IS_FDCAN_FRAME_FORMAT
IS_FDCAN_FRAME_TYPE
IS_FDCAN_ID_TYPE
IS_FDCAN_IT
IS_FDCAN_IT_GROUP
IS_FDCAN_IT_LINE
IS_FDCAN_MAX_VALUE
IS_FDCAN_MIN_VALUE
IS_FDCAN_MODE
IS_FDCAN_NOMINAL_PRESCALER
IS_FDCAN_NOMINAL_SJW
IS_FDCAN_NOMINAL_TSEG1
IS_FDCAN_NOMINAL_TSEG2
IS_FDCAN_NON_MATCHING
IS_FDCAN_REJECT_REMOTE
IS_FDCAN_RX_FIFO
IS_FDCAN_RX_FIFO_MODE
IS_FDCAN_STD_FILTER_TYPE
IS_FDCAN_TIMEOUT
IS_FDCAN_TIMESTAMP
IS_FDCAN_TIMESTAMP_PRESCALER
IS_FDCAN_TX_FIFO_QUEUE_MODE
IS_FDCAN_TX_LOCATION
IS_FDCAN_TX_LOCATION_LIST
FDCAN_Private_Functions_Prototypes
FLASH
FLASH_NB_DOUBLE_WORDS_IN_ROW
FLASH_PAGE_NB
FLASH_PAGE_SIZE
FLASH_PAGE_SIZE_128_BITS
FLASH_SIZE
FLASH_SIZE_DATA_REGISTER
FLASH_TIMEOUT_VALUE
FLASH Private Variables
FLASH Private Functions
FLASH_Program_Fast
FLASH_WaitForLastOperation
FLASH Exported Functions
HAL_FLASH_IRQHandler
HAL_FLASH_OperationErrorCallback
HAL_FLASH_Program
HAL_FLASH_Program_IT
Peripheral Control functions
HAL_FLASH_OB_Launch
HAL_FLASH_OB_Lock
HAL_FLASH_OB_Unlock
HAL_FLASH_Unlock
Peripheral State and Errors functions
FLASH Exported Types
FLASH_ProcedureTypeDef
Data Structures
FLASH_OBProgramInitTypeDef
FLASH_ProcessTypeDef
FLASH Exported Constants
HAL_FLASH_ERROR_ECCC2
HAL_FLASH_ERROR_ECCD
HAL_FLASH_ERROR_ECCD2
HAL_FLASH_ERROR_FAST
HAL_FLASH_ERROR_MIS
HAL_FLASH_ERROR_NONE
HAL_FLASH_ERROR_OP
HAL_FLASH_ERROR_OPTV
HAL_FLASH_ERROR_PGA
HAL_FLASH_ERROR_PGS
HAL_FLASH_ERROR_PROG
HAL_FLASH_ERROR_RD
HAL_FLASH_ERROR_SIZ
HAL_FLASH_ERROR_WRP
FLASH Erase Type
FLASH_TYPEERASE_PAGES
FLASH Banks
FLASH_BANK_2
FLASH_BANK_BOTH
FLASH Program Type
FLASH_TYPEPROGRAM_FAST
FLASH_TYPEPROGRAM_FAST_AND_LAST
FLASH Option Bytes Type
OPTIONBYTE_PCROP
OPTIONBYTE_RDP
OPTIONBYTE_SEC
OPTIONBYTE_USER
OPTIONBYTE_WRP
FLASH WRP Area
OB_WRPAREA_BANK1_AREAB
OB_WRPAREA_BANK2_AREAA
OB_WRPAREA_BANK2_AREAB
FLASH Boot Lock
OB_BOOT_LOCK_ENABLE
FLASH Option Bytes Read Protection
OB_RDP_LEVEL_1
OB_RDP_LEVEL_2
FLASH Option Bytes User Type
OB_USER_BOR_LEV
OB_USER_CCMSRAM_RST
OB_USER_DBANK
OB_USER_IRHEN
OB_USER_IWDG_STDBY
OB_USER_IWDG_STOP
OB_USER_IWDG_SW
OB_USER_nBOOT0
OB_USER_nBOOT1
OB_USER_NRST_MODE
OB_USER_nRST_SHDW
OB_USER_nRST_STDBY
OB_USER_nRST_STOP
OB_USER_nSWBOOT0
OB_USER_SRAM_PE
OB_USER_WWDG_SW
FLASH Option Bytes User BOR Level
OB_BOR_LEVEL_1
OB_BOR_LEVEL_2
OB_BOR_LEVEL_3
OB_BOR_LEVEL_4
FLASH Option Bytes User Reset On Stop
OB_STOP_RST
FLASH Option Bytes User Reset On Standby
OB_STANDBY_RST
FLASH Option Bytes User Reset On Shutdown
OB_SHUTDOWN_RST
FLASH Option Bytes User IWDG Type
OB_IWDG_SW
FLASH Option Bytes User IWDG Mode On Stop
OB_IWDG_STOP_RUN
FLASH Option Bytes User IWDG Mode On Standby
OB_IWDG_STDBY_RUN
FLASH Option Bytes User WWDG Type
OB_WWDG_SW
FLASH Option Bytes User BFB2 Mode
OB_BFB2_ENABLE
FLASH Option Bytes User DBANK Type
OB_DBANK_64_BITS
FLASH Option Bytes User BOOT1 Type
OB_BOOT1_SYSTEM
FLASH Option Bytes User SRAM Parity Check Type
OB_SRAM_PARITY_ENABLE
FLASH Option Bytes User CCMSRAM Erase On Reset Type
OB_CCMSRAM_RST_NOT_ERASE
FLASH Option Bytes User Software BOOT0
OB_BOOT0_FROM_PIN
FLASH Option Bytes User nBOOT0 option bit
OB_nBOOT0_SET
FLASH Option Bytes User NRST mode bit
OB_NRST_MODE_INPUT_ONLY
OB_NRST_MODE_INPUT_OUTPUT
FLASH Option Bytes User internal reset holder bit
OB_IRH_ENABLE
FLASH Option Bytes PCROP On RDP Level Type
OB_PCROP_RDP_NOT_ERASE
FLASH Latency
FLASH_LATENCY_1
FLASH_LATENCY_10
FLASH_LATENCY_11
FLASH_LATENCY_12
FLASH_LATENCY_13
FLASH_LATENCY_14
FLASH_LATENCY_15
FLASH_LATENCY_2
FLASH_LATENCY_3
FLASH_LATENCY_4
FLASH_LATENCY_5
FLASH_LATENCY_6
FLASH_LATENCY_7
FLASH_LATENCY_8
FLASH_LATENCY_9
FLASH Keys
FLASH_KEY2
FLASH_OPTKEY1
FLASH_OPTKEY2
FLASH_PDKEY1
FLASH_PDKEY2
FLASH Flags Definition
FLASH_FLAG_BSY
FLASH_FLAG_ECCC
FLASH_FLAG_ECCC2
FLASH_FLAG_ECCD
FLASH_FLAG_ECCD2
FLASH_FLAG_ECCR_ERRORS
FLASH_FLAG_EOP
FLASH_FLAG_FASTERR
FLASH_FLAG_MISERR
FLASH_FLAG_OPERR
FLASH_FLAG_OPTVERR
FLASH_FLAG_PGAERR
FLASH_FLAG_PGSERR
FLASH_FLAG_PROGERR
FLASH_FLAG_RDERR
FLASH_FLAG_SIZERR
FLASH_FLAG_SR_ERRORS
FLASH_FLAG_WRPERR
FLASH Interrupts Definition
FLASH_IT_EOP
FLASH_IT_OPERR
FLASH_IT_RDERR
FLASH Exported Macros
__HAL_FLASH_DATA_CACHE_ENABLE
__HAL_FLASH_DATA_CACHE_RESET
__HAL_FLASH_GET_LATENCY
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE
__HAL_FLASH_INSTRUCTION_CACHE_RESET
__HAL_FLASH_POWER_DOWN_DISABLE
__HAL_FLASH_POWER_DOWN_ENABLE
__HAL_FLASH_PREFETCH_BUFFER_DISABLE
__HAL_FLASH_PREFETCH_BUFFER_ENABLE
__HAL_FLASH_SET_LATENCY
__HAL_FLASH_SLEEP_POWERDOWN_DISABLE
__HAL_FLASH_SLEEP_POWERDOWN_ENABLE
FLASH Interrupts Macros
__HAL_FLASH_DISABLE_IT
__HAL_FLASH_ENABLE_IT
__HAL_FLASH_GET_FLAG
FLASH Exported Variables
FLASH Private Macros
IS_FLASH_BANK_EXCLUSIVE
IS_FLASH_LATENCY
IS_FLASH_MAIN_MEM_ADDRESS
IS_FLASH_OTP_ADDRESS
IS_FLASH_PAGE
IS_FLASH_PROGRAM_ADDRESS
IS_FLASH_TYPEERASE
IS_FLASH_TYPEPROGRAM
IS_OB_BOOT_LOCK
IS_OB_PCROP_RDP
IS_OB_RDP_LEVEL
IS_OB_SECMEM_SIZE
IS_OB_USER_BFB2
IS_OB_USER_BOOT0
IS_OB_USER_BOOT1
IS_OB_USER_BOR_LEVEL
IS_OB_USER_CCMSRAM_RST
IS_OB_USER_DBANK
IS_OB_USER_IRHEN
IS_OB_USER_IWDG
IS_OB_USER_IWDG_STDBY
IS_OB_USER_IWDG_STOP
IS_OB_USER_NRST_MODE
IS_OB_USER_SHUTDOWN
IS_OB_USER_SRAM_PARITY
IS_OB_USER_STANDBY
IS_OB_USER_STOP
IS_OB_USER_SWBOOT0
IS_OB_USER_TYPE
IS_OB_USER_WWDG
IS_OB_WRPAREA
IS_OPTIONBYTE
FLASHEx
FLASH_MassErase
FLASH_OB_BootLockConfig
FLASH_OB_GetBootLock
FLASH_OB_GetPCROP
FLASH_OB_GetRDP
FLASH_OB_GetSecMem
FLASH_OB_GetUser
FLASH_OB_GetWRP
FLASH_OB_PCROPConfig
FLASH_OB_RDPConfig
FLASH_OB_SecMemConfig
FLASH_OB_UserConfig
FLASH_OB_WRPConfig
FLASH_PageErase
FLASHEx Exported Functions
HAL_FLASHEx_EnableDebugger
HAL_FLASHEx_EnableSecMemProtection
HAL_FLASHEx_Erase
HAL_FLASHEx_Erase_IT
HAL_FLASHEx_OBGetConfig
HAL_FLASHEx_OBProgram
FLASH_RAMFUNC
HAL_FLASHEx_EnableRunPowerDown
HAL_FLASHEx_OB_DBankConfig
FMAC
FMAC_DMA_WEN
FMAC_PARAM_P_MAX_FIR
FMAC_PARAM_P_MAX_IIR
FMAC_PARAM_P_MIN
FMAC_PARAM_Q_MAX
FMAC_PARAM_Q_MIN
FMAC_PARAM_R_MAX
FMAC_START
HAL_FMAC_RESET_TIMEOUT_VALUE
HAL_FMAC_TIMEOUT_VALUE
MAX_FILTER_DATA_SIZE_TO_HANDLE
MAX_PRELOAD_INDEX
POLLING_DISABLED
POLLING_ENABLED
POLLING_NOT_STOPPED
POLLING_STOPPED
PRELOAD_ACCESS_DMA
PRELOAD_ACCESS_POLLING
FMAC Private Macros
FMAC_GET_THRESHOLD_FROM_WM
FMAC_GET_X1_FULL_WM
FMAC_GET_X1_SIZE
FMAC_GET_X2_SIZE
FMAC_GET_Y_EMPTY_WM
FMAC_GET_Y_SIZE
IS_FMAC_BUFFER_ACCESS
IS_FMAC_CLIP_STATE
IS_FMAC_FILTER_FUNCTION
IS_FMAC_FUNCTION
IS_FMAC_LOAD_FUNCTION
IS_FMAC_N_LOAD_FUNCTION
IS_FMAC_N_M_LOAD_FUNCTION
IS_FMAC_PARAM_P
IS_FMAC_PARAM_Q
IS_FMAC_PARAM_R
IS_FMAC_THRESHOLD
IS_FMAC_THRESHOLD_APPLICABLE
FMAC Exported Functions
HAL_FMAC_Init
HAL_FMAC_MspDeInit
HAL_FMAC_MspInit
HAL_FMAC_RegisterCallback
HAL_FMAC_UnRegisterCallback
Peripheral Control functions
HAL_FMAC_ConfigFilterOutputBuffer
HAL_FMAC_FilterConfig
HAL_FMAC_FilterConfig_DMA
HAL_FMAC_FilterPreload
HAL_FMAC_FilterPreload_DMA
HAL_FMAC_FilterStart
HAL_FMAC_FilterStop
HAL_FMAC_PollFilterData
Callback functions
HAL_FMAC_FilterConfigCallback
HAL_FMAC_FilterPreloadCallback
HAL_FMAC_GetDataCallback
HAL_FMAC_HalfGetDataCallback
HAL_FMAC_HalfOutputDataReadyCallback
HAL_FMAC_OutputDataReadyCallback
IRQ handler management
Peripheral State and Error functions
HAL_FMAC_GetState
FMAC Private Functions
FMAC_ConfigFilterOutputBufferUpdateState
FMAC_DMAError
FMAC_DMAFilterConfig
FMAC_DMAFilterPreload
FMAC_DMAGetData
FMAC_DMAHalfGetData
FMAC_DMAHalfOutputDataReady
FMAC_DMAOutputDataReady
FMAC_FilterConfig
FMAC_FilterPreload
FMAC_ReadDataIncrementPtr
FMAC_Reset
FMAC_ResetDataPointers
FMAC_ResetInputStateAndDataPointers
FMAC_ResetOutputStateAndDataPointers
FMAC_WaitOnStartUntilTimeout
FMAC_WriteDataIncrementPtr
FMAC_WritePreloadDataIncrementPtr
FMAC Exported Types
pFMAC_CallbackTypeDef
Enumerations
HAL_FMAC_StateTypeDef
Data Structures
FMAC_FilterConfigTypeDef
FMAC Exported Constants
HAL_FMAC_ERROR_INVALID_CALLBACK
HAL_FMAC_ERROR_NONE
HAL_FMAC_ERROR_OVFL
HAL_FMAC_ERROR_PARAM
HAL_FMAC_ERROR_RESET
HAL_FMAC_ERROR_SAT
HAL_FMAC_ERROR_TIMEOUT
HAL_FMAC_ERROR_UNFL
FMAC Functions
FMAC_FUNC_IIR_DIRECT_FORM_1
FMAC_FUNC_LOAD_X1
FMAC_FUNC_LOAD_X2
FMAC_FUNC_LOAD_Y
FMAC Data Buffer Threshold
FMAC_THRESHOLD_2
FMAC_THRESHOLD_4
FMAC_THRESHOLD_8
FMAC_THRESHOLD_NO_VALUE
FMAC Buffer Access
FMAC_BUFFER_ACCESS_IT
FMAC_BUFFER_ACCESS_NONE
FMAC_BUFFER_ACCESS_POLLING
FMAC Clip State
FMAC_CLIP_ENABLED
FMAC status flags
FMAC_FLAG_SAT
FMAC_FLAG_UNFL
FMAC_FLAG_X1FULL
FMAC_FLAG_YEMPTY
FMAC Interrupts Enable bit
FMAC_IT_RIEN
FMAC_IT_SATIEN
FMAC_IT_UNFLIEN
FMAC_IT_WIEN
FMAC Exported variables
FMAC Exported Macros
__HAL_FMAC_CLEAR_IT
__HAL_FMAC_DISABLE_IT
__HAL_FMAC_ENABLE_IT
__HAL_FMAC_GET_FLAG
__HAL_FMAC_GET_IT
__HAL_FMAC_GET_IT_SOURCE
__HAL_FMAC_RESET_HANDLE_STATE
GPIO
Data Structures
GPIO Exported Constants
GPIO_PIN_1
GPIO_PIN_10
GPIO_PIN_11
GPIO_PIN_12
GPIO_PIN_13
GPIO_PIN_14
GPIO_PIN_15
GPIO_PIN_2
GPIO_PIN_3
GPIO_PIN_4
GPIO_PIN_5
GPIO_PIN_6
GPIO_PIN_7
GPIO_PIN_8
GPIO_PIN_9
GPIO_PIN_All
GPIO_PIN_MASK
GPIO mode
GPIO_MODE_AF_PP
GPIO_MODE_ANALOG
GPIO_MODE_EVT_FALLING
GPIO_MODE_EVT_RISING
GPIO_MODE_EVT_RISING_FALLING
GPIO_MODE_INPUT
GPIO_MODE_IT_FALLING
GPIO_MODE_IT_RISING
GPIO_MODE_IT_RISING_FALLING
GPIO_MODE_OUTPUT_OD
GPIO_MODE_OUTPUT_PP
GPIO speed
GPIO_SPEED_FREQ_LOW
GPIO_SPEED_FREQ_MEDIUM
GPIO_SPEED_FREQ_VERY_HIGH
GPIO pull
GPIO_PULLDOWN
GPIO_PULLUP
GPIO Exported Macros
__HAL_GPIO_EXTI_CLEAR_IT
__HAL_GPIO_EXTI_GENERATE_SWIT
__HAL_GPIO_EXTI_GET_FLAG
__HAL_GPIO_EXTI_GET_IT
GPIO Private Constants
EXTI_IT
EXTI_MODE
EXTI_MODE_Pos
GPIO_MODE
GPIO_MODE_Pos
GPIO_NUMBER
MODE_AF
MODE_ANALOG
MODE_INPUT
MODE_OUTPUT
OUTPUT_OD
OUTPUT_PP
OUTPUT_TYPE
OUTPUT_TYPE_Pos
TRIGGER_FALLING
TRIGGER_MODE
TRIGGER_MODE_Pos
TRIGGER_RISING
GPIO Private Macros
IS_GPIO_PIN
IS_GPIO_PIN_ACTION
IS_GPIO_PULL
IS_GPIO_SPEED
GPIO Exported Functions
HAL_GPIO_Init
IO operation functions
HAL_GPIO_EXTI_IRQHandler
HAL_GPIO_LockPin
HAL_GPIO_ReadPin
HAL_GPIO_TogglePin
HAL_GPIO_WritePin
GPIOEx
GPIO_AF0_RTC_50Hz
GPIO_AF0_SWJ
GPIO_AF0_TRACE
GPIO_AF10_QUADSPI
GPIO_AF10_TIM17
GPIO_AF10_TIM17_COMP1
GPIO_AF10_TIM2
GPIO_AF10_TIM3
GPIO_AF10_TIM4
GPIO_AF10_TIM8
GPIO_AF10_TIM8_COMP2
GPIO_AF11_FDCAN1
GPIO_AF11_FDCAN3
GPIO_AF11_LPTIM1
GPIO_AF11_TIM1
GPIO_AF11_TIM8
GPIO_AF11_TIM8_COMP1
GPIO_AF12_FMC
GPIO_AF12_HRTIM1
GPIO_AF12_LPUART1
GPIO_AF12_SAI1
GPIO_AF12_TIM1
GPIO_AF12_TIM1_COMP1
GPIO_AF12_TIM1_COMP2
GPIO_AF13_HRTIM1
GPIO_AF13_SAI1
GPIO_AF14_SAI1
GPIO_AF14_TIM15
GPIO_AF14_TIM2
GPIO_AF14_UART4
GPIO_AF14_UART5
GPIO_AF14_UCPD1
GPIO_AF15_EVENTOUT
GPIO_AF1_IR
GPIO_AF1_LPTIM1
GPIO_AF1_TIM15
GPIO_AF1_TIM16
GPIO_AF1_TIM17
GPIO_AF1_TIM17_COMP1
GPIO_AF1_TIM2
GPIO_AF1_TIM5
GPIO_AF2_COMP1
GPIO_AF2_I2C3
GPIO_AF2_TIM1
GPIO_AF2_TIM15
GPIO_AF2_TIM15_COMP1
GPIO_AF2_TIM16
GPIO_AF2_TIM16_COMP1
GPIO_AF2_TIM1_COMP1
GPIO_AF2_TIM2
GPIO_AF2_TIM20
GPIO_AF2_TIM20_COMP1
GPIO_AF2_TIM20_COMP2
GPIO_AF2_TIM3
GPIO_AF2_TIM4
GPIO_AF2_TIM5
GPIO_AF2_TIM8
GPIO_AF3_COMP3
GPIO_AF3_HRTIM1
GPIO_AF3_I2C3
GPIO_AF3_I2C4
GPIO_AF3_QUADSPI
GPIO_AF3_SAI1
GPIO_AF3_TIM15
GPIO_AF3_TIM20
GPIO_AF3_TIM8
GPIO_AF3_UCPD1
GPIO_AF4_I2C1
GPIO_AF4_I2C2
GPIO_AF4_I2C3
GPIO_AF4_I2C4
GPIO_AF4_TIM1
GPIO_AF4_TIM16
GPIO_AF4_TIM17
GPIO_AF4_TIM8
GPIO_AF4_TIM8_COMP1
GPIO_AF5_I2S2ext
GPIO_AF5_IR
GPIO_AF5_SPI1
GPIO_AF5_SPI2
GPIO_AF5_SPI4
GPIO_AF5_TIM8
GPIO_AF5_TIM8_COMP1
GPIO_AF5_UART4
GPIO_AF5_UART5
GPIO_AF6_I2S3ext
GPIO_AF6_IR
GPIO_AF6_SPI2
GPIO_AF6_SPI3
GPIO_AF6_TIM1
GPIO_AF6_TIM1_COMP1
GPIO_AF6_TIM1_COMP2
GPIO_AF6_TIM20
GPIO_AF6_TIM5
GPIO_AF6_TIM8
GPIO_AF6_TIM8_COMP2
GPIO_AF7_COMP5
GPIO_AF7_COMP6
GPIO_AF7_COMP7
GPIO_AF7_USART1
GPIO_AF7_USART2
GPIO_AF7_USART3
GPIO_AF8_COMP1
GPIO_AF8_COMP2
GPIO_AF8_COMP3
GPIO_AF8_COMP4
GPIO_AF8_COMP5
GPIO_AF8_COMP6
GPIO_AF8_COMP7
GPIO_AF8_I2C3
GPIO_AF8_I2C4
GPIO_AF8_LPUART1
GPIO_AF8_UART4
GPIO_AF8_UART5
GPIO_AF9_FDCAN1
GPIO_AF9_FDCAN2
GPIO_AF9_TIM1
GPIO_AF9_TIM15
GPIO_AF9_TIM15_COMP1
GPIO_AF9_TIM1_COMP1
GPIO_AF9_TIM8
GPIO_AF9_TIM8_COMP1
IS_GPIO_AF
GPIOEx Exported Macros
HRTIM
HRTIM_FLTINR2_FLTxLCK
HRTIM_FLTR_FLTxEN
HRTIM_TIMCR_TIMUPDATETRIGGER
HRTIM Private Variables
HRTIM Private Functions
HRTIM_BurstDMACplt
HRTIM_CaptureUnitConfig
HRTIM_DMAError
HRTIM_DMAMasterCplt
HRTIM_DMATimerxCplt
HRTIM_EventConfig
HRTIM_ForceRegistersUpdate
HRTIM_GetDMAFromOCMode
HRTIM_GetDMAHandleFromTimerIdx
HRTIM_GetITFromOCMode
HRTIM_HRTIM_ISR
HRTIM_Master_ISR
HRTIM_MasterBase_Config
HRTIM_MasterWaveform_Config
HRTIM_OutputConfig
HRTIM_TIM_ResetConfig
HRTIM_Timer_ISR
HRTIM_TimingUnitBase_Config
HRTIM_TimingUnitRollOver_Config
HRTIM_TimingUnitWaveform_Config
HRTIM_TimingUnitWaveform_Control
HRTIM Exported Functions
HAL_HRTIM_DLLCalibrationStart
HAL_HRTIM_DLLCalibrationStart_IT
HAL_HRTIM_Init
HAL_HRTIM_MspDeInit
HAL_HRTIM_MspInit
HAL_HRTIM_PollForDLLCalibration
HAL_HRTIM_TimeBaseConfig
Simple time base mode functions
HAL_HRTIM_SimpleBaseStart_DMA
HAL_HRTIM_SimpleBaseStart_IT
HAL_HRTIM_SimpleBaseStop
HAL_HRTIM_SimpleBaseStop_DMA
HAL_HRTIM_SimpleBaseStop_IT
Simple output compare mode functions
HAL_HRTIM_SimpleOCStart
HAL_HRTIM_SimpleOCStart_DMA
HAL_HRTIM_SimpleOCStart_IT
HAL_HRTIM_SimpleOCStop
HAL_HRTIM_SimpleOCStop_DMA
HAL_HRTIM_SimpleOCStop_IT
Simple PWM output mode functions
HAL_HRTIM_SimplePWMStart
HAL_HRTIM_SimplePWMStart_DMA
HAL_HRTIM_SimplePWMStart_IT
HAL_HRTIM_SimplePWMStop
HAL_HRTIM_SimplePWMStop_DMA
HAL_HRTIM_SimplePWMStop_IT
Simple input capture functions
HAL_HRTIM_SimpleCaptureStart
HAL_HRTIM_SimpleCaptureStart_DMA
HAL_HRTIM_SimpleCaptureStart_IT
HAL_HRTIM_SimpleCaptureStop
HAL_HRTIM_SimpleCaptureStop_DMA
HAL_HRTIM_SimpleCaptureStop_IT
Simple one pulse functions
HAL_HRTIM_SimpleOnePulseStart
HAL_HRTIM_SimpleOnePulseStart_IT
HAL_HRTIM_SimpleOnePulseStop
HAL_HRTIM_SimpleOnePulseStop_IT
Configuration functions
HAL_HRTIM_ADCTriggerConfig
HAL_HRTIM_BurstModeConfig
HAL_HRTIM_EventConfig
HAL_HRTIM_EventPrescalerConfig
HAL_HRTIM_FaultBlankingConfigAndEnable
HAL_HRTIM_FaultConfig
HAL_HRTIM_FaultCounterConfig
HAL_HRTIM_FaultCounterReset
HAL_HRTIM_FaultModeCtl
HAL_HRTIM_FaultPrescalerConfig
HAL_HRTIM_OutputSwapDisable
HAL_HRTIM_OutputSwapEnable
HAL_HRTIM_RollOverModeConfig
HAL_HRTIM_SwapTimerOutput
Timer waveform configuration and functions
HAL_HRTIM_BurstDMATransfer
HAL_HRTIM_BurstModeCtl
HAL_HRTIM_BurstModeSoftwareTrigger
HAL_HRTIM_ChopperModeConfig
HAL_HRTIM_DeadTimeConfig
HAL_HRTIM_ExtEventCounterConfig
HAL_HRTIM_ExtEventCounterDisable
HAL_HRTIM_ExtEventCounterEnable
HAL_HRTIM_ExtEventCounterReset
HAL_HRTIM_OutputSwapDisable
HAL_HRTIM_OutputSwapEnable
HAL_HRTIM_SoftwareCapture
HAL_HRTIM_SoftwareReset
HAL_HRTIM_SoftwareUpdate
HAL_HRTIM_SwapTimerOutput
HAL_HRTIM_TimerDualChannelDacConfig
HAL_HRTIM_TimerEventFilteringConfig
HAL_HRTIM_UpdateDisable
HAL_HRTIM_UpdateEnable
HAL_HRTIM_WaveformCaptureConfig
HAL_HRTIM_WaveformCompareConfig
HAL_HRTIM_WaveformCountStart
HAL_HRTIM_WaveformCountStart_DMA
HAL_HRTIM_WaveformCountStart_IT
HAL_HRTIM_WaveformCountStop
HAL_HRTIM_WaveformCountStop_DMA
HAL_HRTIM_WaveformCountStop_IT
HAL_HRTIM_WaveformOutputConfig
HAL_HRTIM_WaveformOutputStart
HAL_HRTIM_WaveformOutputStop
HAL_HRTIM_WaveformSetOutputLevel
HAL_HRTIM_WaveformTimerConfig
HAL_HRTIM_WaveformTimerControl
Peripheral state functions
HAL_HRTIM_GetCaptured
HAL_HRTIM_GetCapturedDir
HAL_HRTIM_GetCapturedValue
HAL_HRTIM_GetCurrentPushPullStatus
HAL_HRTIM_GetDelayedProtectionStatus
HAL_HRTIM_GetIdlePushPullStatus
HAL_HRTIM_GetState
HAL_HRTIM_WaveformGetOutputLevel
HAL_HRTIM_WaveformGetOutputState
Interrupts handling
HAL_HRTIM_BurstModePeriodCallback
HAL_HRTIM_Capture1EventCallback
HAL_HRTIM_Capture2EventCallback
HAL_HRTIM_Compare1EventCallback
HAL_HRTIM_Compare2EventCallback
HAL_HRTIM_Compare3EventCallback
HAL_HRTIM_Compare4EventCallback
HAL_HRTIM_CounterResetCallback
HAL_HRTIM_DelayedProtectionCallback
HAL_HRTIM_DLLCalibrationReadyCallback
HAL_HRTIM_ErrorCallback
HAL_HRTIM_Fault1Callback
HAL_HRTIM_Fault2Callback
HAL_HRTIM_Fault3Callback
HAL_HRTIM_Fault4Callback
HAL_HRTIM_Fault5Callback
HAL_HRTIM_Fault6Callback
HAL_HRTIM_IRQHandler
HAL_HRTIM_Output1ResetCallback
HAL_HRTIM_Output1SetCallback
HAL_HRTIM_Output2ResetCallback
HAL_HRTIM_Output2SetCallback
HAL_HRTIM_RegisterCallback
HAL_HRTIM_RegistersUpdateCallback
HAL_HRTIM_RepetitionEventCallback
HAL_HRTIM_SynchronizationEventCallback
HAL_HRTIM_SystemFaultCallback
HAL_HRTIM_TIMxRegisterCallback
HAL_HRTIM_TIMxUnRegisterCallback
HAL_HRTIM_UnRegisterCallback
HRTIM Exported Types
pHRTIM_CallbackTypeDef
pHRTIM_TIMxCallbackTypeDef
Enumerations
HAL_HRTIM_StateTypeDef
Data Structures
HRTIM_TimerParamTypeDef
__HRTIM_HandleTypeDef
HRTIM_TimeBaseCfgTypeDef
HRTIM_SimpleOCChannelCfgTypeDef
HRTIM_SimplePWMChannelCfgTypeDef
HRTIM_SimpleCaptureChannelCfgTypeDef
HRTIM_SimpleOnePulseChannelCfgTypeDef
HRTIM_TimerCfgTypeDef
HRTIM_TimerCtlTypeDef
HRTIM_CompareCfgTypeDef
HRTIM_CaptureValueTypeDef
HRTIM_CaptureCfgTypeDef
HRTIM_OutputCfgTypeDef
HRTIM_TimerEventFilteringCfgTypeDef
HRTIM_DeadTimeCfgTypeDef
HRTIM_ChopperModeCfgTypeDef
HRTIM_EventCfgTypeDef
HRTIM_FaultCfgTypeDef
HRTIM_FaultBlankingCfgTypeDef
HRTIM_BurstModeCfgTypeDef
HRTIM_ADCTriggerCfgTypeDef
HRTIM_ExternalEventCfgTypeDef
HRTIM Exported Constants
HRTIM Timer Index
HRTIM_TIMERINDEX_MASTER
HRTIM_TIMERINDEX_TIMER_A
HRTIM_TIMERINDEX_TIMER_B
HRTIM_TIMERINDEX_TIMER_C
HRTIM_TIMERINDEX_TIMER_D
HRTIM_TIMERINDEX_TIMER_E
HRTIM_TIMERINDEX_TIMER_F
HRTIM Timer identifier
HRTIM_TIMERID_TIMER_A
HRTIM_TIMERID_TIMER_B
HRTIM_TIMERID_TIMER_C
HRTIM_TIMERID_TIMER_D
HRTIM_TIMERID_TIMER_E
HRTIM_TIMERID_TIMER_F
HRTIM Compare Unit
HRTIM_COMPAREUNIT_2
HRTIM_COMPAREUNIT_3
HRTIM_COMPAREUNIT_4
HRTIM Capture Unit
HRTIM_CAPTUREUNIT_2
HRTIM Timer Output
HRTIM_OUTPUT_TA2
HRTIM_OUTPUT_TB1
HRTIM_OUTPUT_TB2
HRTIM_OUTPUT_TC1
HRTIM_OUTPUT_TC2
HRTIM_OUTPUT_TD1
HRTIM_OUTPUT_TD2
HRTIM_OUTPUT_TE1
HRTIM_OUTPUT_TE2
HRTIM_OUTPUT_TF1
HRTIM_OUTPUT_TF2
HRTIM ADC Trigger
HRTIM_ADCTRIGGER_2
HRTIM_ADCTRIGGER_3
HRTIM_ADCTRIGGER_4
HRTIM ADC Extended Trigger
HRTIM_ADCTRIGGER_5
HRTIM_ADCTRIGGER_6
HRTIM_ADCTRIGGER_7
HRTIM_ADCTRIGGER_8
HRTIM_ADCTRIGGER_9
IS_HRTIM_ADCEXTTRIGGER
IS_HRTIM_ADCTRIGGER
HRTIM External Event Channels
HRTIM_EVENT_10
HRTIM_EVENT_2
HRTIM_EVENT_3
HRTIM_EVENT_4
HRTIM_EVENT_5
HRTIM_EVENT_6
HRTIM_EVENT_7
HRTIM_EVENT_8
HRTIM_EVENT_9
HRTIM_EVENT_NONE
HRTIM Fault Channel
HRTIM_FAULT_2
HRTIM_FAULT_3
HRTIM_FAULT_4
HRTIM_FAULT_5
HRTIM_FAULT_6
HRTIM Prescaler Ratio
HRTIM_PRESCALERRATIO_DIV2
HRTIM_PRESCALERRATIO_DIV4
HRTIM_PRESCALERRATIO_MUL16
HRTIM_PRESCALERRATIO_MUL2
HRTIM_PRESCALERRATIO_MUL32
HRTIM_PRESCALERRATIO_MUL4
HRTIM_PRESCALERRATIO_MUL8
HRTIM Counter Operating Mode
HRTIM_MODE_SINGLESHOT
HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
HRTIM Half Mode Enable
HRTIM_HALFMODE_ENABLED
HRTIM Interleaved Mode
HRTIM_INTERLEAVED_MODE_DUAL
HRTIM_INTERLEAVED_MODE_QUAD
HRTIM_INTERLEAVED_MODE_TRIPLE
HRTIM Start On Sync Input Event
HRTIM_SYNCSTART_ENABLED
HRTIM Reset On Sync Input Event
HRTIM_SYNCRESET_ENABLED
HRTIM DAC Synchronization
HRTIM_DACSYNC_DACTRIGOUT_2
HRTIM_DACSYNC_DACTRIGOUT_3
HRTIM_DACSYNC_NONE
HRTIM Register Preload Enable
HRTIM_PRELOAD_ENABLED
HRTIM Update Gating
HRTIM_UPDATEGATING_DMABURST_UPDATE
HRTIM_UPDATEGATING_INDEPENDENT
HRTIM_UPDATEGATING_UPDEN1
HRTIM_UPDATEGATING_UPDEN1_UPDATE
HRTIM_UPDATEGATING_UPDEN2
HRTIM_UPDATEGATING_UPDEN2_UPDATE
HRTIM_UPDATEGATING_UPDEN3
HRTIM_UPDATEGATING_UPDEN3_UPDATE
HRTIM Timer Burst Mode
HRTIM_TIMERBURSTMODE_RESETCOUNTER
HRTIM Timer UpDown Mode
HRTIM_TIMERUPDOWNMODE_UPDOWN
HRTIM Timer Triggered-Half Mode
HRTIM_TIMERTRIGHALF_ENABLED
LL_HRTIM_TRIGHALF_DISABLED
LL_HRTIM_TRIGHALF_ENABLED
HRTIM Timer Greater than Compare 3 PWM Mode
HRTIM_TIMERGTCMP3_GREATER
HRTIM Timer Greater than Compare 1 PWM Mode
HRTIM_TIMERGTCMP1_GREATER
HRTIM Dual Channel Dac Reset Trigger
HRTIM_TIMER_DCDR_OUT1SET
HRTIM Dual Channel Dac Step Trigger
HRTIM_TIMER_DCDS_OUT1RST
HRTIM Dual Channel DAC Trigger Enable
HRTIM_TIMER_DCDE_ENABLED
HRTIM Timer Repetition Update
HRTIM_UPDATEONREPETITION_ENABLED
HRTIM Timer Push Pull Mode
HRTIM_TIMPUSHPULLMODE_ENABLED
HRTIM Timer Fault Enabling
HRTIM_TIMFAULTENABLE_FAULT2
HRTIM_TIMFAULTENABLE_FAULT3
HRTIM_TIMFAULTENABLE_FAULT4
HRTIM_TIMFAULTENABLE_FAULT5
HRTIM_TIMFAULTENABLE_FAULT6
HRTIM_TIMFAULTENABLE_NONE
HRTIM Timer Fault Lock
HRTIM_TIMFAULTLOCK_READWRITE
HRTIM Timer Dead-time Insertion
HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM Timer Delayed Protection Mode
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED
HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED
HRTIM Timer Update Trigger
HRTIM_TIMUPDATETRIGGER_NONE
HRTIM_TIMUPDATETRIGGER_TIMER_A
HRTIM_TIMUPDATETRIGGER_TIMER_B
HRTIM_TIMUPDATETRIGGER_TIMER_C
HRTIM_TIMUPDATETRIGGER_TIMER_D
HRTIM_TIMUPDATETRIGGER_TIMER_E
HRTIM_TIMUPDATETRIGGER_TIMER_F
HRTIM Timer Reset Trigger
HRTIM_TIMRESETTRIGGER_CMP4
HRTIM_TIMRESETTRIGGER_EEV_1
HRTIM_TIMRESETTRIGGER_EEV_10
HRTIM_TIMRESETTRIGGER_EEV_2
HRTIM_TIMRESETTRIGGER_EEV_3
HRTIM_TIMRESETTRIGGER_EEV_4
HRTIM_TIMRESETTRIGGER_EEV_5
HRTIM_TIMRESETTRIGGER_EEV_6
HRTIM_TIMRESETTRIGGER_EEV_7
HRTIM_TIMRESETTRIGGER_EEV_8
HRTIM_TIMRESETTRIGGER_EEV_9
HRTIM_TIMRESETTRIGGER_MASTER_CMP1
HRTIM_TIMRESETTRIGGER_MASTER_CMP2
HRTIM_TIMRESETTRIGGER_MASTER_CMP3
HRTIM_TIMRESETTRIGGER_MASTER_CMP4
HRTIM_TIMRESETTRIGGER_MASTER_PER
HRTIM_TIMRESETTRIGGER_NONE
HRTIM_TIMRESETTRIGGER_OTHER1_CMP1
HRTIM_TIMRESETTRIGGER_OTHER1_CMP2
HRTIM_TIMRESETTRIGGER_OTHER1_CMP4
HRTIM_TIMRESETTRIGGER_OTHER2_CMP1
HRTIM_TIMRESETTRIGGER_OTHER2_CMP2
HRTIM_TIMRESETTRIGGER_OTHER2_CMP4
HRTIM_TIMRESETTRIGGER_OTHER3_CMP1
HRTIM_TIMRESETTRIGGER_OTHER3_CMP2
HRTIM_TIMRESETTRIGGER_OTHER3_CMP4
HRTIM_TIMRESETTRIGGER_OTHER4_CMP1
HRTIM_TIMRESETTRIGGER_OTHER4_CMP2
HRTIM_TIMRESETTRIGGER_OTHER4_CMP4
HRTIM_TIMRESETTRIGGER_OTHER5_CMP1
HRTIM_TIMRESETTRIGGER_OTHER5_CMP2
HRTIM_TIMRESETTRIGGER_UPDATE
HRTIM Timer Reset Update
HRTIM_TIMUPDATEONRESET_ENABLED
HRTIM Timer RollOver Mode
HRTIM_TIM_ADROM_CREST
HRTIM_TIM_ADROM_VALLEY
HRTIM_TIM_BMROM_BOTH
HRTIM_TIM_BMROM_CREST
HRTIM_TIM_BMROM_VALLEY
HRTIM_TIM_FEROM_BOTH
HRTIM_TIM_FEROM_CREST
HRTIM_TIM_FEROM_VALLEY
HRTIM_TIM_OUTROM_BOTH
HRTIM_TIM_OUTROM_CREST
HRTIM_TIM_OUTROM_VALLEY
HRTIM_TIM_ROM_BOTH
HRTIM_TIM_ROM_CREST
HRTIM_TIM_ROM_VALLEY
IS_HRTIM_ROLLOVERMODE
HRTIM Compare Unit Auto Delayed Mode
HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1
HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3
HRTIM_AUTODELAYEDMODE_REGULAR
HRTIM Simple OC Mode
HRTIM_BASICOCMODE_INACTIVE
HRTIM_BASICOCMODE_TOGGLE
IS_HRTIM_BASICOCMODE
HRTIM Output Polarity
HRTIM_OUTPUTPOLARITY_LOW
HRTIM Output Set Source
HRTIM_OUTPUTSET_EEV_10
HRTIM_OUTPUTSET_EEV_2
HRTIM_OUTPUTSET_EEV_3
HRTIM_OUTPUTSET_EEV_4
HRTIM_OUTPUTSET_EEV_5
HRTIM_OUTPUTSET_EEV_6
HRTIM_OUTPUTSET_EEV_7
HRTIM_OUTPUTSET_EEV_8
HRTIM_OUTPUTSET_EEV_9
HRTIM_OUTPUTSET_MASTERCMP1
HRTIM_OUTPUTSET_MASTERCMP2
HRTIM_OUTPUTSET_MASTERCMP3
HRTIM_OUTPUTSET_MASTERCMP4
HRTIM_OUTPUTSET_MASTERPER
HRTIM_OUTPUTSET_NONE
HRTIM_OUTPUTSET_RESYNC
HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
HRTIM_OUTPUTSET_TIMCMP1
HRTIM_OUTPUTSET_TIMCMP2
HRTIM_OUTPUTSET_TIMCMP3
HRTIM_OUTPUTSET_TIMCMP4
HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
HRTIM_OUTPUTSET_TIMPER
HRTIM_OUTPUTSET_UPDATE
HRTIM Output Reset Source
HRTIM_OUTPUTRESET_EEV_10
HRTIM_OUTPUTRESET_EEV_2
HRTIM_OUTPUTRESET_EEV_3
HRTIM_OUTPUTRESET_EEV_4
HRTIM_OUTPUTRESET_EEV_5
HRTIM_OUTPUTRESET_EEV_6
HRTIM_OUTPUTRESET_EEV_7
HRTIM_OUTPUTRESET_EEV_8
HRTIM_OUTPUTRESET_EEV_9
HRTIM_OUTPUTRESET_MASTERCMP1
HRTIM_OUTPUTRESET_MASTERCMP2
HRTIM_OUTPUTRESET_MASTERCMP3
HRTIM_OUTPUTRESET_MASTERCMP4
HRTIM_OUTPUTRESET_MASTERPER
HRTIM_OUTPUTRESET_NONE
HRTIM_OUTPUTRESET_RESYNC
HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
HRTIM_OUTPUTRESET_TIMCMP1
HRTIM_OUTPUTRESET_TIMCMP2
HRTIM_OUTPUTRESET_TIMCMP3
HRTIM_OUTPUTRESET_TIMCMP4
HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
HRTIM_OUTPUTRESET_TIMPER
HRTIM_OUTPUTRESET_UPDATE
LL_HRTIM_OUTPUTRESET_EEV_1
LL_HRTIM_OUTPUTRESET_EEV_10
LL_HRTIM_OUTPUTRESET_EEV_2
LL_HRTIM_OUTPUTRESET_EEV_3
LL_HRTIM_OUTPUTRESET_EEV_4
LL_HRTIM_OUTPUTRESET_EEV_5
LL_HRTIM_OUTPUTRESET_EEV_6
LL_HRTIM_OUTPUTRESET_EEV_7
LL_HRTIM_OUTPUTRESET_EEV_8
LL_HRTIM_OUTPUTRESET_EEV_9
LL_HRTIM_OUTPUTRESET_MASTERCMP1
LL_HRTIM_OUTPUTRESET_MASTERCMP2
LL_HRTIM_OUTPUTRESET_MASTERCMP3
LL_HRTIM_OUTPUTRESET_MASTERCMP4
LL_HRTIM_OUTPUTRESET_MASTERPER
LL_HRTIM_OUTPUTRESET_NONE
LL_HRTIM_OUTPUTRESET_RESYNC
LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP1
LL_HRTIM_OUTPUTRESET_TIMCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP3
LL_HRTIM_OUTPUTRESET_TIMCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMPER
LL_HRTIM_OUTPUTRESET_UPDATE
HRTIM Output Idle Mode
HRTIM_OUTPUTIDLEMODE_NONE
HRTIM Output IDLE Level
HRTIM_OUTPUTIDLELEVEL_INACTIVE
HRTIM Output FAULT Level
HRTIM_OUTPUTFAULTLEVEL_HIGHZ
HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM_OUTPUTFAULTLEVEL_NONE
HRTIM Output Chopper Mode Enable
HRTIM_OUTPUTCHOPPERMODE_ENABLED
HRTIM Output Burst Mode Entry Delayed
HRTIM_OUTPUTBURSTMODEENTRY_REGULAR
HRTIM Output Balanced Idle Automatic Resume
HRTIM_OUTPUTBIAR_ENABLED
HRTIM Capture Unit Trigger
HRTIM_CAPTURETRIGGER_EEV_10
HRTIM_CAPTURETRIGGER_EEV_2
HRTIM_CAPTURETRIGGER_EEV_3
HRTIM_CAPTURETRIGGER_EEV_4
HRTIM_CAPTURETRIGGER_EEV_5
HRTIM_CAPTURETRIGGER_EEV_6
HRTIM_CAPTURETRIGGER_EEV_7
HRTIM_CAPTURETRIGGER_EEV_8
HRTIM_CAPTURETRIGGER_EEV_9
HRTIM_CAPTURETRIGGER_NONE
HRTIM_CAPTURETRIGGER_TA1_RESET
HRTIM_CAPTURETRIGGER_TA1_SET
HRTIM_CAPTURETRIGGER_TB1_RESET
HRTIM_CAPTURETRIGGER_TB1_SET
HRTIM_CAPTURETRIGGER_TC1_RESET
HRTIM_CAPTURETRIGGER_TC1_SET
HRTIM_CAPTURETRIGGER_TD1_RESET
HRTIM_CAPTURETRIGGER_TD1_SET
HRTIM_CAPTURETRIGGER_TE1_RESET
HRTIM_CAPTURETRIGGER_TE1_SET
HRTIM_CAPTURETRIGGER_TIMERA_CMP1
HRTIM_CAPTURETRIGGER_TIMERA_CMP2
HRTIM_CAPTURETRIGGER_TIMERB_CMP1
HRTIM_CAPTURETRIGGER_TIMERB_CMP2
HRTIM_CAPTURETRIGGER_TIMERC_CMP1
HRTIM_CAPTURETRIGGER_TIMERC_CMP2
HRTIM_CAPTURETRIGGER_TIMERD_CMP1
HRTIM_CAPTURETRIGGER_TIMERD_CMP2
HRTIM_CAPTURETRIGGER_TIMERE_CMP1
HRTIM_CAPTURETRIGGER_TIMERE_CMP2
HRTIM_CAPTURETRIGGER_UPDATE
HRTIM Capture Unit TimerF Trigger
HRTIM_CAPTURETRIGGER_TF1_SET
HRTIM_CAPTURETRIGGER_TIMERF_CMP1
HRTIM_CAPTURETRIGGER_TIMERF_CMP2
HRTIM Timer External Event Filter
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2
HRTIM_TIMEEVFLT_BLANKINGCMP1
HRTIM_TIMEEVFLT_BLANKINGCMP2
HRTIM_TIMEEVFLT_BLANKINGCMP3
HRTIM_TIMEEVFLT_BLANKINGCMP4
HRTIM_TIMEEVFLT_NONE
HRTIM_TIMEEVFLT_WINDOWINGCMP2
HRTIM_TIMEEVFLT_WINDOWINGCMP3
HRTIM_TIMEEVFLT_WINDOWINGTIM
HRTIM Timer External Event Latch
HRTIM_TIMEVENTLATCH_ENABLED
HRTIM Timer External Event Counter A or B
HRTIM_EVENTCOUNTER_B
HRTIM Timer External Counter Reset Mode
HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
HRTIM Timer Re-Synchronized update
HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL
HRTIM Dead-time Prescaler Ratio
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL16
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8
HRTIM Dead-time Rising Sign
HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE
HRTIM Dead-time Rising Lock
HRTIM_TIMDEADTIME_RISINGLOCK_WRITE
HRTIM Dead-time Rising Sign Lock
HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE
HRTIM Dead-time Falling Sign
HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE
HRTIM Dead-time Falling Lock
HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE
HRTIM Dead-time Falling Sign Lock
HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE
HRTIM Chopper Frequency
HRTIM_CHOPPER_PRESCALERRATIO_DIV128
HRTIM_CHOPPER_PRESCALERRATIO_DIV144
HRTIM_CHOPPER_PRESCALERRATIO_DIV16
HRTIM_CHOPPER_PRESCALERRATIO_DIV160
HRTIM_CHOPPER_PRESCALERRATIO_DIV176
HRTIM_CHOPPER_PRESCALERRATIO_DIV192
HRTIM_CHOPPER_PRESCALERRATIO_DIV208
HRTIM_CHOPPER_PRESCALERRATIO_DIV224
HRTIM_CHOPPER_PRESCALERRATIO_DIV240
HRTIM_CHOPPER_PRESCALERRATIO_DIV256
HRTIM_CHOPPER_PRESCALERRATIO_DIV32
HRTIM_CHOPPER_PRESCALERRATIO_DIV48
HRTIM_CHOPPER_PRESCALERRATIO_DIV64
HRTIM_CHOPPER_PRESCALERRATIO_DIV80
HRTIM_CHOPPER_PRESCALERRATIO_DIV96
HRTIM Chopper Duty Cycle
HRTIM_CHOPPER_DUTYCYCLE_125
HRTIM_CHOPPER_DUTYCYCLE_250
HRTIM_CHOPPER_DUTYCYCLE_375
HRTIM_CHOPPER_DUTYCYCLE_500
HRTIM_CHOPPER_DUTYCYCLE_625
HRTIM_CHOPPER_DUTYCYCLE_750
HRTIM_CHOPPER_DUTYCYCLE_875
HRTIM Chopper Start Pulse Width
HRTIM_CHOPPER_PULSEWIDTH_128
HRTIM_CHOPPER_PULSEWIDTH_144
HRTIM_CHOPPER_PULSEWIDTH_16
HRTIM_CHOPPER_PULSEWIDTH_160
HRTIM_CHOPPER_PULSEWIDTH_176
HRTIM_CHOPPER_PULSEWIDTH_192
HRTIM_CHOPPER_PULSEWIDTH_208
HRTIM_CHOPPER_PULSEWIDTH_224
HRTIM_CHOPPER_PULSEWIDTH_240
HRTIM_CHOPPER_PULSEWIDTH_256
HRTIM_CHOPPER_PULSEWIDTH_32
HRTIM_CHOPPER_PULSEWIDTH_48
HRTIM_CHOPPER_PULSEWIDTH_64
HRTIM_CHOPPER_PULSEWIDTH_80
HRTIM_CHOPPER_PULSEWIDTH_96
HRTIM Synchronization Options
HRTIM_SYNCOPTION_NONE
HRTIM_SYNCOPTION_SLAVE
HRTIM Synchronization Input Source
HRTIM_SYNCINPUTSOURCE_INTERNALEVENT
HRTIM_SYNCINPUTSOURCE_NONE
HRTIM Synchronization Output Source
HRTIM_SYNCOUTPUTSOURCE_MASTER_START
HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1
HRTIM_SYNCOUTPUTSOURCE_TIMA_START
HRTIM Synchronization Output Polarity
HRTIM_SYNCOUTPUTPOLARITY_NONE
HRTIM_SYNCOUTPUTPOLARITY_POSITIVE
HRTIM External Event Sources
HRTIM_EEV10SRC_COMP7_OUT
HRTIM_EEV10SRC_GPIO
HRTIM_EEV10SRC_TIM6_TRGO
HRTIM_EEV1SRC_ADC1_AWD1
HRTIM_EEV1SRC_COMP2_OUT
HRTIM_EEV1SRC_GPIO
HRTIM_EEV1SRC_TIM1_TRGO
HRTIM_EEV2SRC_ADC1_AWD2
HRTIM_EEV2SRC_COMP4_OUT
HRTIM_EEV2SRC_GPIO
HRTIM_EEV2SRC_TIM2_TRGO
HRTIM_EEV3SRC_ADC1_AWD3
HRTIM_EEV3SRC_COMP6_OUT
HRTIM_EEV3SRC_GPIO
HRTIM_EEV3SRC_TIM3_TRGO
HRTIM_EEV4SRC_ADC2_AWD1
HRTIM_EEV4SRC_COMP1_OUT
HRTIM_EEV4SRC_COMP5_OUT
HRTIM_EEV4SRC_GPIO
HRTIM_EEV5SRC_ADC2_AWD2
HRTIM_EEV5SRC_COMP3_OUT
HRTIM_EEV5SRC_COMP7_OUT
HRTIM_EEV5SRC_GPIO
HRTIM_EEV6SRC_ADC2_AWD3
HRTIM_EEV6SRC_COMP1_OUT
HRTIM_EEV6SRC_COMP2_OUT
HRTIM_EEV6SRC_GPIO
HRTIM_EEV7SRC_ADC3_AWD1
HRTIM_EEV7SRC_COMP4_OUT
HRTIM_EEV7SRC_GPIO
HRTIM_EEV7SRC_TIM7_TRGO
HRTIM_EEV8SRC_ADC4_AWD1
HRTIM_EEV8SRC_COMP3_OUT
HRTIM_EEV8SRC_COMP6_OUT
HRTIM_EEV8SRC_GPIO
HRTIM_EEV9SRC_COMP4_OUT
HRTIM_EEV9SRC_COMP5_OUT
HRTIM_EEV9SRC_GPIO
HRTIM_EEV9SRC_TIM15_TRGO
HRTIM External Event Polarity
HRTIM_EVENTPOLARITY_LOW
HRTIM External Event Sensitivity
HRTIM_EVENTSENSITIVITY_FALLINGEDGE
HRTIM_EVENTSENSITIVITY_LEVEL
HRTIM_EVENTSENSITIVITY_RISINGEDGE
HRTIM External Event Fast Mode
HRTIM_EVENTFASTMODE_ENABLE
HRTIM External Event Filter
HRTIM_EVENTFILTER_10
HRTIM_EVENTFILTER_11
HRTIM_EVENTFILTER_12
HRTIM_EVENTFILTER_13
HRTIM_EVENTFILTER_14
HRTIM_EVENTFILTER_15
HRTIM_EVENTFILTER_2
HRTIM_EVENTFILTER_3
HRTIM_EVENTFILTER_4
HRTIM_EVENTFILTER_5
HRTIM_EVENTFILTER_6
HRTIM_EVENTFILTER_7
HRTIM_EVENTFILTER_8
HRTIM_EVENTFILTER_9
HRTIM_EVENTFILTER_NONE
HRTIM External Event Prescaler
HRTIM_EVENTPRESCALER_DIV2
HRTIM_EVENTPRESCALER_DIV4
HRTIM_EVENTPRESCALER_DIV8
HRTIM Fault Sources
HRTIM_FAULTSOURCE_EEVINPUT
HRTIM_FAULTSOURCE_INTERNAL
HRTIM Fault Polarity
HRTIM_FAULTPOLARITY_LOW
HRTIM Fault Blanking Source
HRTIM_FAULTBLANKINGMODE_RSTALIGNED
HRTIM Fault Reset Mode
HRTIM_FAULTCOUNTERRST_UNCONDITIONAL
HRTIM Fault Blanking Control
HRTIM_FAULTBLANKINGCTL_ENABLED
HRTIM Fault Filter
HRTIM_FAULTFILTER_10
HRTIM_FAULTFILTER_11
HRTIM_FAULTFILTER_12
HRTIM_FAULTFILTER_13
HRTIM_FAULTFILTER_14
HRTIM_FAULTFILTER_15
HRTIM_FAULTFILTER_2
HRTIM_FAULTFILTER_3
HRTIM_FAULTFILTER_4
HRTIM_FAULTFILTER_5
HRTIM_FAULTFILTER_6
HRTIM_FAULTFILTER_7
HRTIM_FAULTFILTER_8
HRTIM_FAULTFILTER_9
HRTIM_FAULTFILTER_NONE
HRTIM Fault counter threshold value
HRTIM_FAULTCOUNTER_10
HRTIM_FAULTCOUNTER_11
HRTIM_FAULTCOUNTER_12
HRTIM_FAULTCOUNTER_13
HRTIM_FAULTCOUNTER_14
HRTIM_FAULTCOUNTER_15
HRTIM_FAULTCOUNTER_2
HRTIM_FAULTCOUNTER_3
HRTIM_FAULTCOUNTER_4
HRTIM_FAULTCOUNTER_5
HRTIM_FAULTCOUNTER_6
HRTIM_FAULTCOUNTER_7
HRTIM_FAULTCOUNTER_8
HRTIM_FAULTCOUNTER_9
HRTIM_FAULTCOUNTER_NONE
HRTIM Fault Lock
HRTIM_FAULTLOCK_READWRITE
HRTIM External Fault Prescaler
HRTIM_FAULTPRESCALER_DIV2
HRTIM_FAULTPRESCALER_DIV4
HRTIM_FAULTPRESCALER_DIV8
HRTIM Burst Mode Operating Mode
HRTIM_BURSTMODE_SINGLESHOT
HRTIM Burst Mode Clock Source
HRTIM_BURSTMODECLOCKSOURCE_MASTER
HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC
HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC
HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO
HRTIM_BURSTMODECLOCKSOURCE_TIMER_A
HRTIM_BURSTMODECLOCKSOURCE_TIMER_B
HRTIM_BURSTMODECLOCKSOURCE_TIMER_C
HRTIM_BURSTMODECLOCKSOURCE_TIMER_D
HRTIM_BURSTMODECLOCKSOURCE_TIMER_E
HRTIM_BURSTMODECLOCKSOURCE_TIMER_F
HRTIM Burst Mode Prescaler
HRTIM_BURSTMODEPRESCALER_DIV1024
HRTIM_BURSTMODEPRESCALER_DIV128
HRTIM_BURSTMODEPRESCALER_DIV16
HRTIM_BURSTMODEPRESCALER_DIV16384
HRTIM_BURSTMODEPRESCALER_DIV2
HRTIM_BURSTMODEPRESCALER_DIV2048
HRTIM_BURSTMODEPRESCALER_DIV256
HRTIM_BURSTMODEPRESCALER_DIV32
HRTIM_BURSTMODEPRESCALER_DIV32768
HRTIM_BURSTMODEPRESCALER_DIV4
HRTIM_BURSTMODEPRESCALER_DIV4096
HRTIM_BURSTMODEPRESCALER_DIV512
HRTIM_BURSTMODEPRESCALER_DIV64
HRTIM_BURSTMODEPRESCALER_DIV8
HRTIM_BURSTMODEPRESCALER_DIV8192
HRTIM Burst Mode Register Preload Enable
HRIM_BURSTMODEPRELOAD_ENABLED
HRTIM Burst Mode Trigger
HRTIM_BURSTMODETRIGGER_EVENT_8
HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP
HRTIM_BURSTMODETRIGGER_MASTER_CMP1
HRTIM_BURSTMODETRIGGER_MASTER_CMP2
HRTIM_BURSTMODETRIGGER_MASTER_CMP3
HRTIM_BURSTMODETRIGGER_MASTER_CMP4
HRTIM_BURSTMODETRIGGER_MASTER_REPETITION
HRTIM_BURSTMODETRIGGER_MASTER_RESET
HRTIM_BURSTMODETRIGGER_NONE
HRTIM_BURSTMODETRIGGER_TIMERA_CMP1
HRTIM_BURSTMODETRIGGER_TIMERA_CMP2
HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7
HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERA_RESET
HRTIM_BURSTMODETRIGGER_TIMERB_CMP1
HRTIM_BURSTMODETRIGGER_TIMERB_CMP2
HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERB_RESET
HRTIM_BURSTMODETRIGGER_TIMERC_CMP1
HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERC_RESET
HRTIM_BURSTMODETRIGGER_TIMERD_CMP2
HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8
HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERD_RESET
HRTIM_BURSTMODETRIGGER_TIMERE_CMP1
HRTIM_BURSTMODETRIGGER_TIMERE_CMP2
HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERF_CMP1
HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERF_RESET
HRTIM ADC Trigger Update Source
HRTIM_ADCTRIGGERUPDATE_TIMER_A
HRTIM_ADCTRIGGERUPDATE_TIMER_B
HRTIM_ADCTRIGGERUPDATE_TIMER_C
HRTIM_ADCTRIGGERUPDATE_TIMER_D
HRTIM_ADCTRIGGERUPDATE_TIMER_E
HRTIM_ADCTRIGGERUPDATE_TIMER_F
HRTIM ADC Trigger Event
HRTIM_ADCTRIGGEREVENT13_EVENT_2
HRTIM_ADCTRIGGEREVENT13_EVENT_3
HRTIM_ADCTRIGGEREVENT13_EVENT_4
HRTIM_ADCTRIGGEREVENT13_EVENT_5
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT13_NONE
HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET
HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET
HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET
HRTIM_ADCTRIGGEREVENT24_EVENT_10
HRTIM_ADCTRIGGEREVENT24_EVENT_6
HRTIM_ADCTRIGGEREVENT24_EVENT_7
HRTIM_ADCTRIGGEREVENT24_EVENT_8
HRTIM_ADCTRIGGEREVENT24_EVENT_9
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT24_NONE
HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT579_EVENT_1
HRTIM_ADCTRIGGEREVENT579_EVENT_2
HRTIM_ADCTRIGGEREVENT579_EVENT_3
HRTIM_ADCTRIGGEREVENT579_EVENT_4
HRTIM_ADCTRIGGEREVENT579_EVENT_5
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET
HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET
HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET
HRTIM_ADCTRIGGEREVENT6810_EVENT_10
HRTIM_ADCTRIGGEREVENT6810_EVENT_6
HRTIM_ADCTRIGGEREVENT6810_EVENT_7
HRTIM_ADCTRIGGEREVENT6810_EVENT_8
HRTIM_ADCTRIGGEREVENT6810_EVENT_9
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD
HRTIM DLL Calibration Rate
HRTIM_CALIBRATIONRATE_1
HRTIM_CALIBRATIONRATE_2
HRTIM_CALIBRATIONRATE_3
HRTIM_SINGLE_CALIBRATION
HRTIM Burst DMA Registers Update
HRTIM_BURSTDMA_CMP1
HRTIM_BURSTDMA_CMP2
HRTIM_BURSTDMA_CMP3
HRTIM_BURSTDMA_CMP4
HRTIM_BURSTDMA_CNT
HRTIM_BURSTDMA_CR
HRTIM_BURSTDMA_CR2
HRTIM_BURSTDMA_DIER
HRTIM_BURSTDMA_DTR
HRTIM_BURSTDMA_EEFR1
HRTIM_BURSTDMA_EEFR2
HRTIM_BURSTDMA_EEFR3
HRTIM_BURSTDMA_FLTR
HRTIM_BURSTDMA_ICR
HRTIM_BURSTDMA_NONE
HRTIM_BURSTDMA_OUTR
HRTIM_BURSTDMA_PER
HRTIM_BURSTDMA_REP
HRTIM_BURSTDMA_RST1R
HRTIM_BURSTDMA_RST2R
HRTIM_BURSTDMA_RSTR
HRTIM_BURSTDMA_SET1R
HRTIM_BURSTDMA_SET2R
HRTIM Burst Mode Control
HRTIM_BURSTMODECTL_ENABLED
HRTIM Fault Mode Control
HRTIM_FAULTMODECTL_ENABLED
HRTIM Software Timer Update
HRTIM_TIMERUPDATE_B
HRTIM_TIMERUPDATE_C
HRTIM_TIMERUPDATE_D
HRTIM_TIMERUPDATE_E
HRTIM_TIMERUPDATE_F
HRTIM_TIMERUPDATE_MASTER
HRTIM Software Timer swap Output
HRTIM_TIMERSWAP_B
HRTIM_TIMERSWAP_C
HRTIM_TIMERSWAP_D
HRTIM_TIMERSWAP_E
HRTIM_TIMERSWAP_F
HRTIM Software Timer Reset
HRTIM_TIMERRESET_TIMER_A
HRTIM_TIMERRESET_TIMER_B
HRTIM_TIMERRESET_TIMER_C
HRTIM_TIMERRESET_TIMER_D
HRTIM_TIMERRESET_TIMER_E
HRTIM_TIMERRESET_TIMER_F
HRTIM Output Level
HRTIM_OUTPUTLEVEL_INACTIVE
IS_HRTIM_OUTPUTLEVEL
HRTIM Output State
HRTIM_OUTPUTSTATE_IDLE
HRTIM_OUTPUTSTATE_RUN
HRTIM Burst Mode Status
HRTIM_BURSTMODESTATUS_ONGOING
HRTIM Current Push Pull Status
HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2
HRTIM Idle Push Pull Status
HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2
HRTIM Common Interrupt Enable
HRTIM_IT_DLLRDY
HRTIM_IT_FLT1
HRTIM_IT_FLT2
HRTIM_IT_FLT3
HRTIM_IT_FLT4
HRTIM_IT_FLT5
HRTIM_IT_FLT6
HRTIM_IT_NONE
HRTIM_IT_SYSFLT
HRTIM Master Interrupt Enable
HRTIM_MASTER_IT_MCMP2
HRTIM_MASTER_IT_MCMP3
HRTIM_MASTER_IT_MCMP4
HRTIM_MASTER_IT_MREP
HRTIM_MASTER_IT_MUPD
HRTIM_MASTER_IT_NONE
HRTIM_MASTER_IT_SYNC
HRTIM Timing Unit Interrupt Enable
HRTIM_TIM_IT_CMP2
HRTIM_TIM_IT_CMP3
HRTIM_TIM_IT_CMP4
HRTIM_TIM_IT_CPT1
HRTIM_TIM_IT_CPT2
HRTIM_TIM_IT_DLYPRT
HRTIM_TIM_IT_NONE
HRTIM_TIM_IT_REP
HRTIM_TIM_IT_RST
HRTIM_TIM_IT_RST1
HRTIM_TIM_IT_RST2
HRTIM_TIM_IT_SET1
HRTIM_TIM_IT_SET2
HRTIM_TIM_IT_UPD
HRTIM Common Interrupt Flag
HRTIM_FLAG_DLLRDY
HRTIM_FLAG_FLT1
HRTIM_FLAG_FLT2
HRTIM_FLAG_FLT3
HRTIM_FLAG_FLT4
HRTIM_FLAG_FLT5
HRTIM_FLAG_FLT6
HRTIM_FLAG_SYSFLT
HRTIM Master Interrupt Flag
HRTIM_MASTER_FLAG_MCMP2
HRTIM_MASTER_FLAG_MCMP3
HRTIM_MASTER_FLAG_MCMP4
HRTIM_MASTER_FLAG_MREP
HRTIM_MASTER_FLAG_MUPD
HRTIM_MASTER_FLAG_SYNC
HRTIM Timing Unit Interrupt Flag
HRTIM_TIM_FLAG_CMP2
HRTIM_TIM_FLAG_CMP3
HRTIM_TIM_FLAG_CMP4
HRTIM_TIM_FLAG_CPT1
HRTIM_TIM_FLAG_CPT2
HRTIM_TIM_FLAG_DLYPRT
HRTIM_TIM_FLAG_REP
HRTIM_TIM_FLAG_RST
HRTIM_TIM_FLAG_RST1
HRTIM_TIM_FLAG_RST2
HRTIM_TIM_FLAG_SET1
HRTIM_TIM_FLAG_SET2
HRTIM_TIM_FLAG_UPD
HRTIM Master DMA Request Enable
HRTIM_MASTER_DMA_MCMP2
HRTIM_MASTER_DMA_MCMP3
HRTIM_MASTER_DMA_MCMP4
HRTIM_MASTER_DMA_MREP
HRTIM_MASTER_DMA_MUPD
HRTIM_MASTER_DMA_NONE
HRTIM_MASTER_DMA_SYNC
HRTIM Timing Unit DMA Request Enable
HRTIM_TIM_DMA_CMP2
HRTIM_TIM_DMA_CMP3
HRTIM_TIM_DMA_CMP4
HRTIM_TIM_DMA_CPT1
HRTIM_TIM_DMA_CPT2
HRTIM_TIM_DMA_DLYPRT
HRTIM_TIM_DMA_NONE
HRTIM_TIM_DMA_REP
HRTIM_TIM_DMA_RST
HRTIM_TIM_DMA_RST1
HRTIM_TIM_DMA_RST2
HRTIM_TIM_DMA_SET1
HRTIM_TIM_DMA_SET2
HRTIM_TIM_DMA_UPD
HRTIM Exported Macros
__HAL_HRTIM_CLEAR_IT
__HAL_HRTIM_COUNTER_MODE_UP
__HAL_HRTIM_COUNTER_MODE_UPDOWN
__HAL_HRTIM_DISABLE
__HAL_HRTIM_DISABLE_IT
__HAL_HRTIM_ENABLE
__HAL_HRTIM_ENABLE_IT
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET
__HAL_HRTIM_FAULT_BLANKING_DISABLE
__HAL_HRTIM_FAULT_BLANKING_ENABLE
__HAL_HRTIM_GET_FLAG
__HAL_HRTIM_GET_ITSTATUS
__HAL_HRTIM_GETCLOCKPRESCALER
__HAL_HRTIM_GETCOMPARE
__HAL_HRTIM_GETCOUNTER
__HAL_HRTIM_GETPERIOD
__HAL_HRTIM_MASTER_CLEAR_FLAG
__HAL_HRTIM_MASTER_CLEAR_IT
__HAL_HRTIM_MASTER_DISABLE_DMA
__HAL_HRTIM_MASTER_DISABLE_IT
__HAL_HRTIM_MASTER_ENABLE_DMA
__HAL_HRTIM_MASTER_ENABLE_IT
__HAL_HRTIM_MASTER_GET_FLAG
__HAL_HRTIM_MASTER_GET_ITSTATUS
__HAL_HRTIM_RESET_HANDLE_STATE
__HAL_HRTIM_SETCLOCKPRESCALER
__HAL_HRTIM_SETCOMPARE
__HAL_HRTIM_SETCOUNTER
__HAL_HRTIM_SETPERIOD
__HAL_HRTIM_TIMER_CLEAR_FLAG
__HAL_HRTIM_TIMER_CLEAR_IT
__HAL_HRTIM_TIMER_DISABLE_DMA
__HAL_HRTIM_TIMER_DISABLE_IT
__HAL_HRTIM_TIMER_ENABLE_DMA
__HAL_HRTIM_TIMER_ENABLE_IT
__HAL_HRTIM_TIMER_GET_FLAG
__HAL_HRTIM_TIMER_GET_ITSTATUS
__HAL_HRTIM_TIMER_OUTPUT_NOSWAP
__HAL_HRTIM_TIMER_OUTPUT_SWAP
HRTIM_TAOEN_MASK
HRTIM_TBOEN_MASK
HRTIM_TCOEN_MASK
HRTIM_TDOEN_MASK
HRTIM_TEOEN_MASK
HRTIM_TFOEN_MASK
HRTIM_Private_Constants
HRTIM_CAPTUREFTRIGGER_TF1_RESET
HRTIM_CAPTUREFTRIGGER_TF1_SET
HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1
HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2
HRTIM_Private_Macros
IS_HRTIM_AUTODELAYEDMODE
IS_HRTIM_BURSTMODE
IS_HRTIM_BURSTMODECLOCKSOURCE
IS_HRTIM_BURSTMODECTL
IS_HRTIM_BURSTMODEPRELOAD
IS_HRTIM_BURSTMODETRIGGER
IS_HRTIM_CALIBRATIONRATE
IS_HRTIM_CAPTUREUNIT
IS_HRTIM_CHOPPER_DUTYCYCLE
IS_HRTIM_CHOPPER_PRESCALERRATIO
IS_HRTIM_CHOPPER_PULSEWIDTH
IS_HRTIM_COMPAREUNIT
IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE
IS_HRTIM_DACSYNC
IS_HRTIM_DUALDAC_ENABLE
IS_HRTIM_DUALDAC_RESET
IS_HRTIM_DUALDAC_STEP
IS_HRTIM_EVENT
IS_HRTIM_EVENTFASTMODE
IS_HRTIM_EVENTFILTER
IS_HRTIM_EVENTPOLARITY
IS_HRTIM_EVENTPRESCALER
IS_HRTIM_EVENTSENSITIVITY
IS_HRTIM_EVENTSRC
IS_HRTIM_FAULT
IS_HRTIM_FAULTBLANKING
IS_HRTIM_FAULTBLANKINGCTL
IS_HRTIM_FAULTBLANKNGMODE
IS_HRTIM_FAULTCOUNTER
IS_HRTIM_FAULTCOUNTERRST
IS_HRTIM_FAULTFILTER
IS_HRTIM_FAULTLOCK
IS_HRTIM_FAULTMODECTL
IS_HRTIM_FAULTPOLARITY
IS_HRTIM_FAULTPRESCALER
IS_HRTIM_FAULTSOURCE
IS_HRTIM_HALFMODE
IS_HRTIM_HRTIM_BURSTMODEPRESCALER
IS_HRTIM_INTERLEAVEDMODE
IS_HRTIM_IT
IS_HRTIM_MASTER_DMA
IS_HRTIM_MASTER_IT
IS_HRTIM_MODE
IS_HRTIM_MODE_ONEPULSE
IS_HRTIM_OUTPUT
IS_HRTIM_OUTPUTBALANCEDIDLE
IS_HRTIM_OUTPUTBURSTMODEENTRY
IS_HRTIM_OUTPUTCHOPPERMODE
IS_HRTIM_OUTPUTFAULTLEVEL
IS_HRTIM_OUTPUTIDLELEVEL
IS_HRTIM_OUTPUTIDLEMODE
IS_HRTIM_OUTPUTPOLARITY
IS_HRTIM_OUTPUTPULSE
IS_HRTIM_OUTPUTRESET
IS_HRTIM_OUTPUTSET
IS_HRTIM_PRELOAD
IS_HRTIM_PRESCALERRATIO
IS_HRTIM_SYNCINPUTSOURCE
IS_HRTIM_SYNCOUTPUTPOLARITY
IS_HRTIM_SYNCOUTPUTSOURCE
IS_HRTIM_SYNCRESET
IS_HRTIM_SYNCSTART
IS_HRTIM_TIM_DMA
IS_HRTIM_TIM_IT
IS_HRTIM_TIMDEADTIME_FALLINGLOCK
IS_HRTIM_TIMDEADTIME_FALLINGSIGN
IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK
IS_HRTIM_TIMDEADTIME_PRESCALERRATIO
IS_HRTIM_TIMDEADTIME_RISINGLOCK
IS_HRTIM_TIMDEADTIME_RISINGSIGN
IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK
IS_HRTIM_TIMDEADTIMEINSERTION
IS_HRTIM_TIMDELAYEDPROTECTION
IS_HRTIM_TIMEEVENT
IS_HRTIM_TIMEEVENT_COUNTER
IS_HRTIM_TIMEEVENT_RESETMODE
IS_HRTIM_TIMEEVENT_SOURCE
IS_HRTIM_TIMER_BURSTDMA
IS_HRTIM_TIMER_CAPTUREFTRIGGER
IS_HRTIM_TIMER_CAPTURETRIGGER
IS_HRTIM_TIMER_OUTPUT
IS_HRTIM_TIMERBURSTMODE
IS_HRTIM_TIMERGTCMP1
IS_HRTIM_TIMERGTCMP3
IS_HRTIM_TIMERID
IS_HRTIM_TIMERINDEX
IS_HRTIM_TIMERRESET
IS_HRTIM_TIMERSWAP
IS_HRTIM_TIMERTRGHLFMODE
IS_HRTIM_TIMERUPDATE
IS_HRTIM_TIMERUPDOWNMODE
IS_HRTIM_TIMEVENTFILTER
IS_HRTIM_TIMEVENTLATCH
IS_HRTIM_TIMFAULTENABLE
IS_HRTIM_TIMFAULTLOCK
IS_HRTIM_TIMING_UNIT
IS_HRTIM_TIMPUSHPULLMODE
IS_HRTIM_TIMRESETTRIGGER
IS_HRTIM_TIMSYNCUPDATE
IS_HRTIM_TIMUPDATEONRESET
IS_HRTIM_TIMUPDATETRIGGER
IS_HRTIM_UPDATEGATING_MASTER
IS_HRTIM_UPDATEGATING_TIM
IS_HRTIM_UPDATEONREPETITION
I2C
I2C_STATE_MASTER_BUSY_RX
I2C_STATE_MASTER_BUSY_TX
I2C_STATE_MEM_BUSY_RX
I2C_STATE_MEM_BUSY_TX
I2C_STATE_MSK
I2C_STATE_NONE
I2C_STATE_SLAVE_BUSY_RX
I2C_STATE_SLAVE_BUSY_TX
I2C_TIMEOUT_ADDR
I2C_TIMEOUT_BUSY
I2C_TIMEOUT_DIR
I2C_TIMEOUT_FLAG
I2C_TIMEOUT_RXNE
I2C_TIMEOUT_STOPF
I2C_TIMEOUT_TC
I2C_TIMEOUT_TCR
I2C_TIMEOUT_TXIS
I2C_XFER_CPLT_IT
I2C_XFER_ERROR_IT
I2C_XFER_LISTEN_IT
I2C_XFER_RELOAD_IT
I2C_XFER_RX_IT
I2C_XFER_TX_IT
MAX_NBYTE_SIZE
SLAVE_ADDR_MSK
SLAVE_ADDR_SHIFT
TIMING_CLEAR_MASK
I2C Private Functions
I2C_Disable_IRQ
I2C_DMAAbort
I2C_DMAError
I2C_DMAMasterReceiveCplt
I2C_DMAMasterTransmitCplt
I2C_DMASlaveReceiveCplt
I2C_DMASlaveTransmitCplt
I2C_Enable_IRQ
I2C_Flush_TXDR
I2C_IsErrorOccurred
I2C_ITAddrCplt
I2C_ITError
I2C_ITListenCplt
I2C_ITMasterCplt
I2C_ITMasterSeqCplt
I2C_ITSlaveCplt
I2C_ITSlaveSeqCplt
I2C_Master_ISR_DMA
I2C_Master_ISR_IT
I2C_Mem_ISR_DMA
I2C_Mem_ISR_IT
I2C_RequestMemoryRead
I2C_RequestMemoryWrite
I2C_Slave_ISR_DMA
I2C_Slave_ISR_IT
I2C_TransferConfig
I2C_TreatErrorCallback
I2C_WaitOnFlagUntilTimeout
I2C_WaitOnRXNEFlagUntilTimeout
I2C_WaitOnSTOPFlagUntilTimeout
I2C_WaitOnTXISFlagUntilTimeout
I2C Exported Functions
HAL_I2C_Init
HAL_I2C_MspDeInit
HAL_I2C_MspInit
HAL_I2C_RegisterAddrCallback
HAL_I2C_RegisterCallback
HAL_I2C_UnRegisterAddrCallback
HAL_I2C_UnRegisterCallback
Input and Output operation functions
HAL_I2C_EnableListen_IT
HAL_I2C_IsDeviceReady
HAL_I2C_Master_Abort_IT
HAL_I2C_Master_Receive
HAL_I2C_Master_Receive_DMA
HAL_I2C_Master_Receive_IT
HAL_I2C_Master_Seq_Receive_DMA
HAL_I2C_Master_Seq_Receive_IT
HAL_I2C_Master_Seq_Transmit_DMA
HAL_I2C_Master_Seq_Transmit_IT
HAL_I2C_Master_Transmit
HAL_I2C_Master_Transmit_DMA
HAL_I2C_Master_Transmit_IT
HAL_I2C_Mem_Read
HAL_I2C_Mem_Read_DMA
HAL_I2C_Mem_Read_IT
HAL_I2C_Mem_Write
HAL_I2C_Mem_Write_DMA
HAL_I2C_Mem_Write_IT
HAL_I2C_Slave_Receive
HAL_I2C_Slave_Receive_DMA
HAL_I2C_Slave_Receive_IT
HAL_I2C_Slave_Seq_Receive_DMA
HAL_I2C_Slave_Seq_Receive_IT
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_I2C_Slave_Seq_Transmit_IT
HAL_I2C_Slave_Transmit
HAL_I2C_Slave_Transmit_DMA
HAL_I2C_Slave_Transmit_IT
IRQ Handler and Callbacks
HAL_I2C_AddrCallback
HAL_I2C_ER_IRQHandler
HAL_I2C_ErrorCallback
HAL_I2C_EV_IRQHandler
HAL_I2C_ListenCpltCallback
HAL_I2C_MasterRxCpltCallback
HAL_I2C_MasterTxCpltCallback
HAL_I2C_MemRxCpltCallback
HAL_I2C_MemTxCpltCallback
HAL_I2C_SlaveRxCpltCallback
HAL_I2C_SlaveTxCpltCallback
Peripheral State, Mode and Error functions
HAL_I2C_GetMode
HAL_I2C_GetState
I2C Exported Types
HAL state structure definition
HAL mode structure definition
I2C Error Code definition
HAL_I2C_ERROR_ARLO
HAL_I2C_ERROR_BERR
HAL_I2C_ERROR_DMA
HAL_I2C_ERROR_DMA_PARAM
HAL_I2C_ERROR_INVALID_CALLBACK
HAL_I2C_ERROR_INVALID_PARAM
HAL_I2C_ERROR_NONE
HAL_I2C_ERROR_OVR
HAL_I2C_ERROR_SIZE
HAL_I2C_ERROR_TIMEOUT
I2C handle Structure definition
pI2C_AddrCallbackTypeDef
pI2C_CallbackTypeDef
Enumerations
Data Structures
I2C Exported Constants
I2C_FIRST_AND_NEXT_FRAME
I2C_FIRST_FRAME
I2C_LAST_FRAME
I2C_LAST_FRAME_NO_STOP
I2C_NEXT_FRAME
I2C_OTHER_AND_LAST_FRAME
I2C_OTHER_FRAME
I2C Addressing Mode
I2C_ADDRESSINGMODE_7BIT
I2C Dual Addressing Mode
I2C_DUALADDRESS_ENABLE
I2C Own Address2 Masks
I2C_OA2_MASK02
I2C_OA2_MASK03
I2C_OA2_MASK04
I2C_OA2_MASK05
I2C_OA2_MASK06
I2C_OA2_MASK07
I2C_OA2_NOMASK
I2C General Call Addressing Mode
I2C_GENERALCALL_ENABLE
I2C No-Stretch Mode
I2C_NOSTRETCH_ENABLE
I2C Memory Address Size
I2C_MEMADD_SIZE_8BIT
I2C Transfer Direction Master Point of View
I2C_DIRECTION_TRANSMIT
I2C Reload End Mode
I2C_RELOAD_MODE
I2C_SOFTEND_MODE
I2C Start or Stop Mode
I2C_GENERATE_START_WRITE
I2C_GENERATE_STOP
I2C_NO_STARTSTOP
I2C Interrupt configuration definition
I2C_IT_ERRI
I2C_IT_NACKI
I2C_IT_RXI
I2C_IT_STOPI
I2C_IT_TCI
I2C_IT_TXI
I2C Flag definition
I2C_FLAG_AF
I2C_FLAG_ALERT
I2C_FLAG_ARLO
I2C_FLAG_BERR
I2C_FLAG_BUSY
I2C_FLAG_DIR
I2C_FLAG_OVR
I2C_FLAG_PECERR
I2C_FLAG_RXNE
I2C_FLAG_STOPF
I2C_FLAG_TC
I2C_FLAG_TCR
I2C_FLAG_TIMEOUT
I2C_FLAG_TXE
I2C_FLAG_TXIS
I2C Exported Macros
__HAL_I2C_DISABLE
__HAL_I2C_DISABLE_IT
__HAL_I2C_ENABLE
__HAL_I2C_ENABLE_IT
__HAL_I2C_GENERATE_NACK
__HAL_I2C_GET_FLAG
__HAL_I2C_GET_IT_SOURCE
__HAL_I2C_RESET_HANDLE_STATE
I2C_FLAG_MASK
I2C Private Constants
I2C Private Macros
I2C_CHECK_IT_SOURCE
I2C_GENERATE_START
I2C_GET_ADDR_MATCH
I2C_GET_DIR
I2C_GET_DMA_REMAIN_DATA
I2C_GET_OWN_ADDRESS1
I2C_GET_OWN_ADDRESS2
I2C_GET_STOP_MODE
I2C_MEM_ADD_LSB
I2C_MEM_ADD_MSB
I2C_RESET_CR2
IS_I2C_ADDRESSING_MODE
IS_I2C_DUAL_ADDRESS
IS_I2C_GENERAL_CALL
IS_I2C_MEMADD_SIZE
IS_I2C_NO_STRETCH
IS_I2C_OWN_ADDRESS1
IS_I2C_OWN_ADDRESS2
IS_I2C_OWN_ADDRESS2_MASK
IS_I2C_TRANSFER_OPTIONS_REQUEST
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST
IS_TRANSFER_MODE
IS_TRANSFER_REQUEST
I2CEx
HAL_I2CEx_ConfigDigitalFilter
WakeUp Mode Functions
HAL_I2CEx_EnableWakeUp
Fast Mode Plus Functions
HAL_I2CEx_EnableFastModePlus
I2C Extended Exported Constants
I2C_ANALOGFILTER_ENABLE
I2C Extended Fast Mode Plus
I2C_FASTMODEPLUS_I2C2
I2C_FASTMODEPLUS_I2C3
I2C_FASTMODEPLUS_I2C4
I2C_FASTMODEPLUS_PB6
I2C_FASTMODEPLUS_PB7
I2C_FASTMODEPLUS_PB8
I2C_FASTMODEPLUS_PB9
I2C_FMP_NOT_SUPPORTED
I2C Extended Exported Macros
I2C Extended Private Constants
I2C Extended Private Macros
IS_I2C_DIGITAL_FILTER
IS_I2C_FASTMODEPLUS
I2C Extended Private Functions
I2S
I2S_DMARxCplt
I2S_DMARxHalfCplt
I2S_DMATxCplt
I2S_DMATxHalfCplt
I2S_Receive_IT
I2S_Transmit_IT
I2S_WaitFlagStateUntilTimeout
I2S Exported Functions
HAL_I2S_Init
HAL_I2S_MspDeInit
HAL_I2S_MspInit
HAL_I2S_RegisterCallback
HAL_I2S_UnRegisterCallback
IO operation functions
HAL_I2S_DMAResume
HAL_I2S_DMAStop
HAL_I2S_ErrorCallback
HAL_I2S_IRQHandler
HAL_I2S_Receive
HAL_I2S_Receive_DMA
HAL_I2S_Receive_IT
HAL_I2S_RxCpltCallback
HAL_I2S_RxHalfCpltCallback
HAL_I2S_Transmit
HAL_I2S_Transmit_DMA
HAL_I2S_Transmit_IT
HAL_I2S_TxCpltCallback
HAL_I2S_TxHalfCpltCallback
Peripheral State and Errors functions
HAL_I2S_GetState
I2S Exported Types
pI2S_CallbackTypeDef
Enumerations
HAL_I2S_StateTypeDef
Data Structures
__I2S_HandleTypeDef
I2S Exported Constants
HAL_I2S_ERROR_DMA
HAL_I2S_ERROR_INVALID_CALLBACK
HAL_I2S_ERROR_NONE
HAL_I2S_ERROR_OVR
HAL_I2S_ERROR_PRESCALER
HAL_I2S_ERROR_TIMEOUT
HAL_I2S_ERROR_UDR
I2S Mode
I2S_MODE_MASTER_TX
I2S_MODE_SLAVE_RX
I2S_MODE_SLAVE_TX
I2S Standard
I2S_STANDARD_MSB
I2S_STANDARD_PCM_LONG
I2S_STANDARD_PCM_SHORT
I2S_STANDARD_PHILIPS
I2S Data Format
I2S_DATAFORMAT_16B_EXTENDED
I2S_DATAFORMAT_24B
I2S_DATAFORMAT_32B
I2S MCLK Output
I2S_MCLKOUTPUT_ENABLE
I2S Audio Frequency
I2S_AUDIOFREQ_16K
I2S_AUDIOFREQ_192K
I2S_AUDIOFREQ_22K
I2S_AUDIOFREQ_32K
I2S_AUDIOFREQ_44K
I2S_AUDIOFREQ_48K
I2S_AUDIOFREQ_8K
I2S_AUDIOFREQ_96K
I2S_AUDIOFREQ_DEFAULT
I2S Clock Polarity
I2S_CPOL_LOW
I2S Interrupts Definition
I2S_IT_RXNE
I2S_IT_TXE
I2S Flags Definition
I2S_FLAG_CHSIDE
I2S_FLAG_FRE
I2S_FLAG_MASK
I2S_FLAG_OVR
I2S_FLAG_RXNE
I2S_FLAG_TXE
I2S_FLAG_UDR
I2S Exported Macros
__HAL_I2S_CLEAR_UDRFLAG
__HAL_I2S_DISABLE
__HAL_I2S_DISABLE_IT
__HAL_I2S_ENABLE
__HAL_I2S_ENABLE_IT
__HAL_I2S_FLUSH_RX_DR
__HAL_I2S_GET_FLAG
__HAL_I2S_GET_IT_SOURCE
__HAL_I2S_RESET_HANDLE_STATE
I2S Private Macros
I2S_CHECK_IT_SOURCE
IS_I2S_AUDIO_FREQ
IS_I2S_CPOL
IS_I2S_DATA_FORMAT
IS_I2S_MCLK_OUTPUT
IS_I2S_MODE
IS_I2S_STANDARD
Defines
IRDA
IRDA_TEACK_REACK_TIMEOUT
USART_BRR_MAX
USART_BRR_MIN
IRDA Private Macros
IS_IRDA_BAUDRATE
IS_IRDA_CLOCKPRESCALER
IS_IRDA_DMA_RX
IS_IRDA_DMA_TX
IS_IRDA_MODE
IS_IRDA_ONE_BIT_SAMPLE
IS_IRDA_PARITY
IS_IRDA_POWERMODE
IS_IRDA_PRESCALER
IS_IRDA_REQUEST_PARAMETER
IS_IRDA_STATE
IS_IRDA_TX_RX_MODE
IRDA Exported Functions
HAL_IRDA_Init
HAL_IRDA_MspDeInit
HAL_IRDA_MspInit
HAL_IRDA_RegisterCallback
HAL_IRDA_UnRegisterCallback
IO operation functions
HAL_IRDA_Abort_IT
HAL_IRDA_AbortCpltCallback
HAL_IRDA_AbortReceive
HAL_IRDA_AbortReceive_IT
HAL_IRDA_AbortReceiveCpltCallback
HAL_IRDA_AbortTransmit
HAL_IRDA_AbortTransmit_IT
HAL_IRDA_AbortTransmitCpltCallback
HAL_IRDA_DMAPause
HAL_IRDA_DMAResume
HAL_IRDA_DMAStop
HAL_IRDA_ErrorCallback
HAL_IRDA_IRQHandler
HAL_IRDA_Receive
HAL_IRDA_Receive_DMA
HAL_IRDA_Receive_IT
HAL_IRDA_RxCpltCallback
HAL_IRDA_RxHalfCpltCallback
HAL_IRDA_Transmit
HAL_IRDA_Transmit_DMA
HAL_IRDA_Transmit_IT
HAL_IRDA_TxCpltCallback
HAL_IRDA_TxHalfCpltCallback
Peripheral State and Error functions
HAL_IRDA_GetState
IRDA Private Functions
IRDA_DMAAbortOnError
IRDA_DMAError
IRDA_DMAReceiveCplt
IRDA_DMAReceiveHalfCplt
IRDA_DMARxAbortCallback
IRDA_DMARxOnlyAbortCallback
IRDA_DMATransmitCplt
IRDA_DMATransmitHalfCplt
IRDA_DMATxAbortCallback
IRDA_DMATxOnlyAbortCallback
IRDA_EndRxTransfer
IRDA_EndTransmit_IT
IRDA_EndTxTransfer
IRDA_InitCallbacksToDefault
IRDA_Receive_IT
IRDA_SetConfig
IRDA_Transmit_IT
IRDA_WaitOnFlagUntilTimeout
IRDA Exported Types
IRDA_HandleTypeDef
pIRDA_CallbackTypeDef
Enumerations
IRDA_ClockSourceTypeDef
Data Structures
__IRDA_HandleTypeDef
IRDA Exported Constants
HAL_IRDA_STATE_BUSY_RX
HAL_IRDA_STATE_BUSY_TX
HAL_IRDA_STATE_BUSY_TX_RX
HAL_IRDA_STATE_ERROR
HAL_IRDA_STATE_READY
HAL_IRDA_STATE_RESET
HAL_IRDA_STATE_TIMEOUT
IRDA Error Code Definition
HAL_IRDA_ERROR_DMA
HAL_IRDA_ERROR_FE
HAL_IRDA_ERROR_INVALID_CALLBACK
HAL_IRDA_ERROR_NE
HAL_IRDA_ERROR_NONE
HAL_IRDA_ERROR_ORE
HAL_IRDA_ERROR_PE
IRDA Parity
IRDA_PARITY_NONE
IRDA_PARITY_ODD
IRDA Transfer Mode
IRDA_MODE_TX
IRDA_MODE_TX_RX
IRDA Low Power
IRDA_POWERMODE_NORMAL
IRDA Clock Prescaler
IRDA_PRESCALER_DIV10
IRDA_PRESCALER_DIV12
IRDA_PRESCALER_DIV128
IRDA_PRESCALER_DIV16
IRDA_PRESCALER_DIV2
IRDA_PRESCALER_DIV256
IRDA_PRESCALER_DIV32
IRDA_PRESCALER_DIV4
IRDA_PRESCALER_DIV6
IRDA_PRESCALER_DIV64
IRDA_PRESCALER_DIV8
IRDA State
IRDA_STATE_ENABLE
IRDA Mode
IRDA_MODE_ENABLE
IRDA One Bit Sampling
IRDA_ONE_BIT_SAMPLE_ENABLE
IRDA DMA Tx
IRDA_DMA_TX_ENABLE
IRDA DMA Rx
IRDA_DMA_RX_ENABLE
IRDA Request Parameters
IRDA_RXDATA_FLUSH_REQUEST
IRDA_TXDATA_FLUSH_REQUEST
IRDA Flags
IRDA_FLAG_ABRF
IRDA_FLAG_BUSY
IRDA_FLAG_FE
IRDA_FLAG_NE
IRDA_FLAG_ORE
IRDA_FLAG_PE
IRDA_FLAG_REACK
IRDA_FLAG_RXNE
IRDA_FLAG_TC
IRDA_FLAG_TEACK
IRDA_FLAG_TXE
IRDA Interrupts Definition
IRDA_IT_FE
IRDA_IT_IDLE
IRDA_IT_NE
IRDA_IT_ORE
IRDA_IT_PE
IRDA_IT_RXNE
IRDA_IT_TC
IRDA_IT_TXE
IRDA Interruption Clear Flags
IRDA_CLEAR_IDLEF
IRDA_CLEAR_NEF
IRDA_CLEAR_OREF
IRDA_CLEAR_PEF
IRDA_CLEAR_TCF
IRDA interruptions flags mask
IRDA_CR_POS
IRDA_ISR_MASK
IRDA_ISR_POS
IRDA_IT_MASK
IRDA Exported Macros
__HAL_IRDA_CLEAR_FLAG
__HAL_IRDA_CLEAR_IDLEFLAG
__HAL_IRDA_CLEAR_IT
__HAL_IRDA_CLEAR_NEFLAG
__HAL_IRDA_CLEAR_OREFLAG
__HAL_IRDA_CLEAR_PEFLAG
__HAL_IRDA_DISABLE
__HAL_IRDA_DISABLE_IT
__HAL_IRDA_ENABLE
__HAL_IRDA_ENABLE_IT
__HAL_IRDA_FLUSH_DRREGISTER
__HAL_IRDA_GET_FLAG
__HAL_IRDA_GET_IT
__HAL_IRDA_GET_IT_SOURCE
__HAL_IRDA_ONE_BIT_SAMPLE_DISABLE
__HAL_IRDA_ONE_BIT_SAMPLE_ENABLE
__HAL_IRDA_RESET_HANDLE_STATE
__HAL_IRDA_SEND_REQ
IRDAEx
IRDA_WORDLENGTH_8B
IRDA_WORDLENGTH_9B
IRDAEx Private Macros
IRDA_MASK_COMPUTATION
IS_IRDA_WORD_LENGTH
IWDG
IWDG_KERNEL_UPDATE_FLAGS
IWDG Exported Types
IWDG_HandleTypeDef
IWDG Exported Constants
IWDG_PRESCALER_16
IWDG_PRESCALER_256
IWDG_PRESCALER_32
IWDG_PRESCALER_4
IWDG_PRESCALER_64
IWDG_PRESCALER_8
IWDG Window option
IWDG Exported Macros
__HAL_IWDG_START
IWDG Exported Functions
IO operation functions
IWDG Private Constants
IWDG_KEY_RELOAD
IWDG_KEY_WRITE_ACCESS_DISABLE
IWDG_KEY_WRITE_ACCESS_ENABLE
IWDG Private Macros
IS_IWDG_RELOAD
IS_IWDG_WINDOW
IWDG_DISABLE_WRITE_ACCESS
IWDG_ENABLE_WRITE_ACCESS
LPTIM
HAL_LPTIM_Init
HAL_LPTIM_MspDeInit
HAL_LPTIM_MspInit
LPTIM Start-Stop operation functions
HAL_LPTIM_Counter_Start_IT
HAL_LPTIM_Counter_Stop
HAL_LPTIM_Counter_Stop_IT
HAL_LPTIM_Encoder_Start
HAL_LPTIM_Encoder_Start_IT
HAL_LPTIM_Encoder_Stop
HAL_LPTIM_Encoder_Stop_IT
HAL_LPTIM_OnePulse_Start
HAL_LPTIM_OnePulse_Start_IT
HAL_LPTIM_OnePulse_Stop
HAL_LPTIM_OnePulse_Stop_IT
HAL_LPTIM_PWM_Start
HAL_LPTIM_PWM_Start_IT
HAL_LPTIM_PWM_Stop
HAL_LPTIM_PWM_Stop_IT
HAL_LPTIM_SetOnce_Start
HAL_LPTIM_SetOnce_Start_IT
HAL_LPTIM_SetOnce_Stop
HAL_LPTIM_SetOnce_Stop_IT
HAL_LPTIM_TimeOut_Start
HAL_LPTIM_TimeOut_Start_IT
HAL_LPTIM_TimeOut_Stop
HAL_LPTIM_TimeOut_Stop_IT
LPTIM Read operation functions
HAL_LPTIM_ReadCompare
HAL_LPTIM_ReadCounter
LPTIM IRQ handler and callbacks
HAL_LPTIM_AutoReloadWriteCallback
HAL_LPTIM_CompareMatchCallback
HAL_LPTIM_CompareWriteCallback
HAL_LPTIM_DirectionDownCallback
HAL_LPTIM_DirectionUpCallback
HAL_LPTIM_IRQHandler
HAL_LPTIM_RegisterCallback
HAL_LPTIM_TriggerCallback
HAL_LPTIM_UnRegisterCallback
Peripheral State functions
LPTIM Private Functions
LPTIM_ResetCallback
LPTIM_WaitForFlag
LPTIM Exported Types
Typedefs
pLPTIM_CallbackTypeDef
Enumerations
HAL_LPTIM_StateTypeDef
Data Structures
LPTIM_ULPClockConfigTypeDef
LPTIM_TriggerConfigTypeDef
LPTIM_InitTypeDef
__LPTIM_HandleTypeDef
LPTIM Exported Constants
LPTIM_CLOCKSOURCE_ULPTIM
LPTIM Clock Prescaler
LPTIM_PRESCALER_DIV128
LPTIM_PRESCALER_DIV16
LPTIM_PRESCALER_DIV2
LPTIM_PRESCALER_DIV32
LPTIM_PRESCALER_DIV4
LPTIM_PRESCALER_DIV64
LPTIM_PRESCALER_DIV8
LPTIM Output Polarity
LPTIM_OUTPUTPOLARITY_LOW
LPTIM Clock Sample Time
LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
LPTIM Clock Polarity
LPTIM_CLOCKPOLARITY_RISING
LPTIM_CLOCKPOLARITY_RISING_FALLING
LPTIM Trigger Source
LPTIM_TRIGSOURCE_1
LPTIM_TRIGSOURCE_10
LPTIM_TRIGSOURCE_11
LPTIM_TRIGSOURCE_12
LPTIM_TRIGSOURCE_2
LPTIM_TRIGSOURCE_3
LPTIM_TRIGSOURCE_4
LPTIM_TRIGSOURCE_5
LPTIM_TRIGSOURCE_6
LPTIM_TRIGSOURCE_7
LPTIM_TRIGSOURCE_8
LPTIM_TRIGSOURCE_9
LPTIM_TRIGSOURCE_SOFTWARE
LPTIM External Trigger Polarity
LPTIM_ACTIVEEDGE_RISING
LPTIM_ACTIVEEDGE_RISING_FALLING
LPTIM Trigger Sample Time
LPTIM_TRIGSAMPLETIME_4TRANSITIONS
LPTIM_TRIGSAMPLETIME_8TRANSITIONS
LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
LPTIM Updating Mode
LPTIM_UPDATE_IMMEDIATE
LPTIM Counter Source
LPTIM_COUNTERSOURCE_INTERNAL
LPTIM Input1 Source
LPTIM_INPUT1SOURCE_COMP3
LPTIM_INPUT1SOURCE_COMP5
LPTIM_INPUT1SOURCE_COMP7
LPTIM_INPUT1SOURCE_GPIO
LPTIM Input2 Source
LPTIM_INPUT2SOURCE_COMP4
LPTIM_INPUT2SOURCE_COMP6
LPTIM_INPUT2SOURCE_GPIO
LPTIM Flags Definition
LPTIM_FLAG_ARROK
LPTIM_FLAG_CMPM
LPTIM_FLAG_CMPOK
LPTIM_FLAG_DOWN
LPTIM_FLAG_EXTTRIG
LPTIM_FLAG_UP
LPTIM Interrupts Definition
LPTIM_IT_ARROK
LPTIM_IT_CMPM
LPTIM_IT_CMPOK
LPTIM_IT_DOWN
LPTIM_IT_EXTTRIG
LPTIM_IT_UP
LPTIM Exported Macros
__HAL_LPTIM_CLEAR_FLAG
__HAL_LPTIM_COMPARE_SET
__HAL_LPTIM_DISABLE
__HAL_LPTIM_DISABLE_IT
__HAL_LPTIM_ENABLE
__HAL_LPTIM_ENABLE_IT
__HAL_LPTIM_GET_FLAG
__HAL_LPTIM_GET_IT_SOURCE
__HAL_LPTIM_RESET_COUNTER
__HAL_LPTIM_RESET_COUNTER_AFTERREAD
__HAL_LPTIM_RESET_HANDLE_STATE
__HAL_LPTIM_START_CONTINUOUS
__HAL_LPTIM_START_SINGLE
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT
LPTIM Private Types
LPTIM Private Variables
LPTIM Private Constants
LPTIM Private Macros
IS_LPTIM_CLOCK_PRESCALER
IS_LPTIM_CLOCK_PRESCALERDIV1
IS_LPTIM_CLOCK_SAMPLE_TIME
IS_LPTIM_CLOCK_SOURCE
IS_LPTIM_COMPARE
IS_LPTIM_COUNTER_SOURCE
IS_LPTIM_EXT_TRG_POLARITY
IS_LPTIM_INPUT1_SOURCE
IS_LPTIM_INPUT2_SOURCE
IS_LPTIM_OUTPUT_POLARITY
IS_LPTIM_PERIOD
IS_LPTIM_PULSE
IS_LPTIM_TRG_SOURCE
IS_LPTIM_TRIG_SAMPLE_TIME
IS_LPTIM_UPDATE_MODE
NAND
HAL_NAND_Init
HAL_NAND_IRQHandler
HAL_NAND_ITCallback
HAL_NAND_MspDeInit
HAL_NAND_MspInit
Input and Output functions
HAL_NAND_ConfigDevice
HAL_NAND_Erase_Block
HAL_NAND_Read_ID
HAL_NAND_Read_Page_16b
HAL_NAND_Read_Page_8b
HAL_NAND_Read_SpareArea_16b
HAL_NAND_Read_SpareArea_8b
HAL_NAND_RegisterCallback
HAL_NAND_Reset
HAL_NAND_UnRegisterCallback
HAL_NAND_Write_Page_16b
HAL_NAND_Write_Page_8b
HAL_NAND_Write_SpareArea_16b
HAL_NAND_Write_SpareArea_8b
Peripheral Control functions
HAL_NAND_ECC_Enable
HAL_NAND_GetECC
Peripheral State functions
HAL_NAND_Read_Status
NOR
NOR_AMD_FUJITSU_COMMAND_SET
NOR_AMD_FUJITSU_EXT_COMMAND_SET
NOR_CMD_ADDRESS_FIFTH
NOR_CMD_ADDRESS_FIRST
NOR_CMD_ADDRESS_FIRST_BYTE
NOR_CMD_ADDRESS_FIRST_CFI
NOR_CMD_ADDRESS_FIRST_CFI_BYTE
NOR_CMD_ADDRESS_FOURTH
NOR_CMD_ADDRESS_SECOND
NOR_CMD_ADDRESS_SECOND_BYTE
NOR_CMD_ADDRESS_SIXTH
NOR_CMD_ADDRESS_THIRD
NOR_CMD_ADDRESS_THIRD_BYTE
NOR_CMD_BLOCK_ERASE
NOR_CMD_BLOCK_UNLOCK
NOR_CMD_BUFFERED_PROGRAM
NOR_CMD_CLEAR_STATUS_REG
NOR_CMD_CONFIRM
NOR_CMD_DATA_AUTO_SELECT
NOR_CMD_DATA_BLOCK_ERASE
NOR_CMD_DATA_BUFFER_AND_PROG
NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
NOR_CMD_DATA_CFI
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
NOR_CMD_DATA_CHIP_ERASE
NOR_CMD_DATA_FIRST
NOR_CMD_DATA_PROGRAM
NOR_CMD_DATA_READ_RESET
NOR_CMD_DATA_SECOND
NOR_CMD_READ_ARRAY
NOR_CMD_READ_STATUS_REG
NOR_CMD_WORD_PROGRAM
NOR_INTEL_DATA_COMMAND_SET
NOR_INTEL_PERFORMANCE_COMMAND_SET
NOR_INTEL_SHARP_EXT_COMMAND_SET
NOR_INTEL_STANDARD_COMMAND_SET
NOR_MASK_STATUS_DQ4
NOR_MASK_STATUS_DQ5
NOR_MASK_STATUS_DQ6
NOR_MASK_STATUS_DQ7
NOR_MITSUBISHI_EXT_COMMAND_SET
NOR_MITSUBISHI_STANDARD_COMMAND_SET
NOR_PAGE_WRITE_COMMAND_SET
NOR_WINDBOND_STANDARD_COMMAND_SET
NOR Private Variables
NOR Exported Functions
HAL_NOR_Init
HAL_NOR_MspDeInit
HAL_NOR_MspInit
HAL_NOR_MspWait
Input and Output functions
HAL_NOR_Erase_Chip
HAL_NOR_Program
HAL_NOR_ProgramBuffer
HAL_NOR_Read
HAL_NOR_Read_CFI
HAL_NOR_Read_ID
HAL_NOR_ReadBuffer
HAL_NOR_RegisterCallback
HAL_NOR_ReturnToReadMode
HAL_NOR_UnRegisterCallback
NOR Control functions
HAL_NOR_WriteOperation_Enable
NOR State functions
HAL_NOR_GetStatus
OPAMP
OPAMP_CSR_RESET_VALUE
OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK
OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK
OPAMP Exported Functions
HAL_OPAMP_Init
HAL_OPAMP_MspDeInit
HAL_OPAMP_MspInit
Input and Output operation functions
HAL_OPAMP_Start
HAL_OPAMP_Stop
Peripheral Control functions
HAL_OPAMP_LockTimerMux
HAL_OPAMP_RegisterCallback
HAL_OPAMP_UnRegisterCallback
Peripheral State functions
HAL_OPAMP_GetTrimOffset
Functions
Peripheral State functions
HAL_OPAMP_GetTrimOffset
OPAMP Exported Types
OPAMP_TrimmingValueTypeDef
Enumerations
Data Structures
__OPAMP_HandleTypeDef
OPAMP Exported Constants
OPAMP_PGA_MODE
OPAMP_STANDALONE_MODE
OPAMP Non Inverting Input
OPAMP_NONINVERTINGINPUT_IO0
OPAMP_NONINVERTINGINPUT_IO1
OPAMP_NONINVERTINGINPUT_IO2
OPAMP_NONINVERTINGINPUT_IO3
OPAMP Inverting Input
OPAMP_INVERTINGINPUT_IO1
OPAMP Timer Controlled Mux mode
OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6
OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6
OPAMP Non Inverting Input Secondary
OPAMP_SEC_NONINVERTINGINPUT_IO0
OPAMP_SEC_NONINVERTINGINPUT_IO1
OPAMP_SEC_NONINVERTINGINPUT_IO2
OPAMP_SEC_NONINVERTINGINPUT_IO3
OPAMP Inverting Input Secondary
OPAMP_SEC_INVERTINGINPUT_IO0
OPAMP_SEC_INVERTINGINPUT_IO1
OPAMP_SEC_INVERTINGINPUT_PGA
OPAMP Pga Connect
OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS
OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS
OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
OPAMP Pga Gain
OPAMP_PGA_GAIN_2_OR_MINUS_1
OPAMP_PGA_GAIN_32_OR_MINUS_31
OPAMP_PGA_GAIN_4_OR_MINUS_3
OPAMP_PGA_GAIN_64_OR_MINUS_63
OPAMP_PGA_GAIN_8_OR_MINUS_7
OPAMP PowerMode
OPAMP_POWERMODE_NORMALSPEED
OPAMP User Trimming
OPAMP_TRIMMING_USER
OPAMP Factory Trimming
OPAMP_FACTORYTRIMMING_N
OPAMP_FACTORYTRIMMING_P
OPAMP VREF
OPAMP_VREF_3VDDA
OPAMP_VREF_50VDDA
OPAMP_VREF_90VDDA
OPAMP Private Constants
OPAMP_INPUT_INVERTING
OPAMP_INPUT_NONINVERTING
OPAMP Private Macros
IS_OPAMP_FUNCTIONAL_NORMALMODE
IS_OPAMP_INVERTING_INPUT
IS_OPAMP_NONINVERTING_INPUT
IS_OPAMP_PGA_GAIN
IS_OPAMP_PGACONNECT
IS_OPAMP_POWERMODE
IS_OPAMP_SEC_INVERTING_INPUT
IS_OPAMP_SEC_NONINVERTING_INPUT
IS_OPAMP_TIMERCONTROLLED_MUXMODE
IS_OPAMP_TRIMMING
IS_OPAMP_TRIMMINGVALUE
IS_OPAMP_VREF
OPAMP Exported Macros
Typedefs
Enumerations
Functions
HAL_OPAMP_UnRegisterCallback
PCD
PCD_CALC_BLK32
PCD_CLEAR_BULK_EP_DBUF
PCD_CLEAR_EP_KIND
PCD_CLEAR_OUT_STATUS
PCD_CLEAR_RX_DTOG
PCD_CLEAR_RX_EP_CTR
PCD_CLEAR_TX_DTOG
PCD_CLEAR_TX_EP_CTR
PCD_EP_RX_CNT
PCD_EP_TX_CNT
PCD_FREE_USER_BUFFER
PCD_GET_ENDPOINT
PCD_GET_EP_ADDRESS
PCD_GET_EP_DBUF0_ADDR
PCD_GET_EP_DBUF0_CNT
PCD_GET_EP_DBUF1_ADDR
PCD_GET_EP_DBUF1_CNT
PCD_GET_EP_RX_ADDRESS
PCD_GET_EP_RX_CNT
PCD_GET_EP_RX_STALL_STATUS
PCD_GET_EP_RX_STATUS
PCD_GET_EP_TX_ADDRESS
PCD_GET_EP_TX_CNT
PCD_GET_EP_TX_STALL_STATUS
PCD_GET_EP_TX_STATUS
PCD_GET_EPTYPE
PCD_MAX
PCD_MIN
PCD_RX_DTOG
PCD_SET_BULK_EP_DBUF
PCD_SET_ENDPOINT
PCD_SET_EP_ADDRESS
PCD_SET_EP_CNT_RX_REG
PCD_SET_EP_DBUF0_ADDR
PCD_SET_EP_DBUF0_CNT
PCD_SET_EP_DBUF1_ADDR
PCD_SET_EP_DBUF1_CNT
PCD_SET_EP_DBUF_ADDR
PCD_SET_EP_DBUF_CNT
PCD_SET_EP_KIND
PCD_SET_EP_RX_ADDRESS
PCD_SET_EP_RX_CNT
PCD_SET_EP_RX_DBUF0_CNT
PCD_SET_EP_RX_STATUS
PCD_SET_EP_RX_VALID
PCD_SET_EP_TX_ADDRESS
PCD_SET_EP_TX_CNT
PCD_SET_EP_TX_STATUS
PCD_SET_EP_TX_VALID
PCD_SET_EP_TXRX_STATUS
PCD_SET_EPTYPE
PCD_SET_OUT_STATUS
PCD_TX_DTOG
USB_CNTRX_BLSIZE
USB_CNTRX_NBLK_MSK
PCD Private Functions
HAL_PCD_EP_DB_Transmit
PCD_EP_ISR_Handler
PCD Exported Functions
HAL USB OTG PCD Callback pointer definition
pPCD_CallbackTypeDef
pPCD_DataInStageCallbackTypeDef
pPCD_DataOutStageCallbackTypeDef
pPCD_IsoInIncpltCallbackTypeDef
pPCD_IsoOutIncpltCallbackTypeDef
pPCD_LpmCallbackTypeDef
Functions
HAL_PCD_Init
HAL_PCD_MspDeInit
HAL_PCD_MspInit
HAL_PCD_RegisterBcdCallback
HAL_PCD_RegisterCallback
HAL_PCD_RegisterDataInStageCallback
HAL_PCD_RegisterDataOutStageCallback
HAL_PCD_RegisterIsoInIncpltCallback
HAL_PCD_RegisterIsoOutIncpltCallback
HAL_PCD_RegisterLpmCallback
HAL_PCD_UnRegisterBcdCallback
HAL_PCD_UnRegisterCallback
HAL_PCD_UnRegisterDataInStageCallback
HAL_PCD_UnRegisterDataOutStageCallback
HAL_PCD_UnRegisterIsoInIncpltCallback
HAL_PCD_UnRegisterIsoOutIncpltCallback
HAL_PCD_UnRegisterLpmCallback
Input and Output operation functions
HAL_PCD_DataInStageCallback
HAL_PCD_DataOutStageCallback
HAL_PCD_DisconnectCallback
HAL_PCD_IRQHandler
HAL_PCD_ISOINIncompleteCallback
HAL_PCD_ISOOUTIncompleteCallback
HAL_PCD_ResetCallback
HAL_PCD_ResumeCallback
HAL_PCD_SetupStageCallback
HAL_PCD_SOFCallback
HAL_PCD_Start
HAL_PCD_Stop
HAL_PCD_SuspendCallback
Peripheral Control functions
HAL_PCD_DeActivateRemoteWakeup
HAL_PCD_DevConnect
HAL_PCD_DevDisconnect
HAL_PCD_EP_Abort
HAL_PCD_EP_Close
HAL_PCD_EP_ClrStall
HAL_PCD_EP_Flush
HAL_PCD_EP_GetRxCount
HAL_PCD_EP_Open
HAL_PCD_EP_Receive
HAL_PCD_EP_SetStall
HAL_PCD_EP_Transmit
HAL_PCD_SetAddress
Peripheral State functions
PCD Exported Types
PCD_HandleTypeDef
PCD_InitTypeDef
PCD_TypeDef
Enumerations
PCD_LPM_MsgTypeDef
PCD_LPM_StateTypeDef
PCD_StateTypeDef
Data Structures
PCD Exported Constants
PCD PHY Module
PCD_PHY_EMBEDDED
PCD_PHY_ULPI
PCD_PHY_UTMI
PCD Error Code definition
PCD Exported Macros
__HAL_PCD_DISABLE
__HAL_PCD_ENABLE
__HAL_PCD_GET_FLAG
__HAL_USB_WAKEUP_EXTI_DISABLE_IT
__HAL_USB_WAKEUP_EXTI_ENABLE_IT
PCD Private Constants
PCD EP0 MPS
PCD_EP0MPS_16
PCD_EP0MPS_32
PCD_EP0MPS_64
PCD ENDP
PCD_ENDP1
PCD_ENDP2
PCD_ENDP3
PCD_ENDP4
PCD_ENDP5
PCD_ENDP6
PCD_ENDP7
PCD Endpoint Kind
PCD_SNG_BUF
PCDEx
HAL_PCDEx_ActivateLPM
HAL_PCDEx_BCD_Callback
HAL_PCDEx_BCD_VBUSDetect
HAL_PCDEx_DeActivateBCD
HAL_PCDEx_DeActivateLPM
HAL_PCDEx_LPM_Callback
HAL_PCDEx_PMAConfig
PWR
PVD_MODE_EVT
PVD_MODE_IT
PVD_RISING_EDGE
PWR Exported Functions
HAL_PWR_DisableBkUpAccess
HAL_PWR_EnableBkUpAccess
Peripheral Control functions
HAL_PWR_DisablePVD
HAL_PWR_DisableSEVOnPend
HAL_PWR_DisableSleepOnExit
HAL_PWR_DisableWakeUpPin
HAL_PWR_EnablePVD
HAL_PWR_EnableSEVOnPend
HAL_PWR_EnableSleepOnExit
HAL_PWR_EnableWakeUpPin
HAL_PWR_EnterSLEEPMode
HAL_PWR_EnterSTANDBYMode
HAL_PWR_EnterSTOPMode
HAL_PWR_PVDCallback
PWR Exported Types
PWR Exported Constants
PWR_PVDLEVEL_1
PWR_PVDLEVEL_2
PWR_PVDLEVEL_3
PWR_PVDLEVEL_4
PWR_PVDLEVEL_5
PWR_PVDLEVEL_6
PWR_PVDLEVEL_7
PWR PVD interrupt and event mode
PWR_PVD_MODE_EVENT_RISING
PWR_PVD_MODE_EVENT_RISING_FALLING
PWR_PVD_MODE_IT_FALLING
PWR_PVD_MODE_IT_RISING
PWR_PVD_MODE_IT_RISING_FALLING
PWR_PVD_MODE_NORMAL
PWR regulator mode
PWR_MAINREGULATOR_ON
PWR SLEEP mode entry
PWR_SLEEPENTRY_WFI
PWR STOP mode entry
PWR_STOPENTRY_WFI
PWR PVD external interrupt line
PWR PVD event line
PWR Exported Macros
__HAL_PWR_GET_FLAG
__HAL_PWR_PVD_EXTI_CLEAR_FLAG
__HAL_PWR_PVD_EXTI_DISABLE_EVENT
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVD_EXTI_DISABLE_IT
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_EVENT
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_IT
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVD_EXTI_GENERATE_SWIT
__HAL_PWR_PVD_EXTI_GET_FLAG
PWR Private Macros
IS_PWR_PVD_MODE
IS_PWR_REGULATOR
IS_PWR_SLEEP_ENTRY
IS_PWR_STOP_ENTRY
PWREx
PVM_MODE_EVT
PVM_MODE_IT
PVM_RISING_EDGE
PWR Extended Flag Setting Time Out Value
PWR Extended Exported Functions
HAL_PWREx_ControlVoltageScaling
HAL_PWREx_DisableBatteryCharging
HAL_PWREx_DisableGPIOPullDown
HAL_PWREx_DisableGPIOPullUp
HAL_PWREx_DisableInternalWakeUpLine
HAL_PWREx_DisableLowPowerRunMode
HAL_PWREx_DisablePullUpPullDownConfig
HAL_PWREx_DisablePVM1
HAL_PWREx_DisablePVM2
HAL_PWREx_DisablePVM3
HAL_PWREx_DisablePVM4
HAL_PWREx_DisableSRAM2ContentRetention
HAL_PWREx_DisableUCPDDeadBattery
HAL_PWREx_DisableUCPDStandbyMode
HAL_PWREx_EnableBatteryCharging
HAL_PWREx_EnableGPIOPullDown
HAL_PWREx_EnableGPIOPullUp
HAL_PWREx_EnableInternalWakeUpLine
HAL_PWREx_EnableLowPowerRunMode
HAL_PWREx_EnablePullUpPullDownConfig
HAL_PWREx_EnablePVM1
HAL_PWREx_EnablePVM2
HAL_PWREx_EnablePVM3
HAL_PWREx_EnablePVM4
HAL_PWREx_EnableSRAM2ContentRetention
HAL_PWREx_EnableUCPDDeadBattery
HAL_PWREx_EnableUCPDStandbyMode
HAL_PWREx_EnterSHUTDOWNMode
HAL_PWREx_EnterSTOP0Mode
HAL_PWREx_EnterSTOP1Mode
HAL_PWREx_GetVoltageRange
HAL_PWREx_PVD_PVM_IRQHandler
HAL_PWREx_PVM1Callback
HAL_PWREx_PVM2Callback
HAL_PWREx_PVM3Callback
HAL_PWREx_PVM4Callback
PWR Extended Exported Types
PWR Extended Exported Constants
PWR wake-up pins
PWR_WAKEUP_PIN1_HIGH
PWR_WAKEUP_PIN1_LOW
PWR_WAKEUP_PIN2
PWR_WAKEUP_PIN2_HIGH
PWR_WAKEUP_PIN2_LOW
PWR_WAKEUP_PIN3
PWR_WAKEUP_PIN3_HIGH
PWR_WAKEUP_PIN3_LOW
PWR_WAKEUP_PIN4
PWR_WAKEUP_PIN4_HIGH
PWR_WAKEUP_PIN4_LOW
PWR_WAKEUP_PIN5
PWR_WAKEUP_PIN5_HIGH
PWR_WAKEUP_PIN5_LOW
Peripheral Voltage Monitoring type
PWR_PVM_2
PWR_PVM_3
PWR_PVM_4
PWR PVM interrupt and event mode
PWR_PVM_MODE_EVENT_RISING
PWR_PVM_MODE_EVENT_RISING_FALLING
PWR_PVM_MODE_IT_FALLING
PWR_PVM_MODE_IT_RISING
PWR_PVM_MODE_IT_RISING_FALLING
PWR_PVM_MODE_NORMAL
PWR Regulator voltage scale
PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
PWR_REGULATOR_VOLTAGE_SCALE2
PWR battery charging resistor selection
PWR_BATTERY_CHARGING_RESISTOR_5
PWR battery charging
PWR_BATTERY_CHARGING_ENABLE
GPIO bit number for I/O setting in standby/shutdown mode
PWR_GPIO_BIT_1
PWR_GPIO_BIT_10
PWR_GPIO_BIT_11
PWR_GPIO_BIT_12
PWR_GPIO_BIT_13
PWR_GPIO_BIT_14
PWR_GPIO_BIT_15
PWR_GPIO_BIT_2
PWR_GPIO_BIT_3
PWR_GPIO_BIT_4
PWR_GPIO_BIT_5
PWR_GPIO_BIT_6
PWR_GPIO_BIT_7
PWR_GPIO_BIT_8
PWR_GPIO_BIT_9
GPIO port
PWR_GPIO_B
PWR_GPIO_C
PWR_GPIO_D
PWR_GPIO_E
PWR_GPIO_F
PWR_GPIO_G
PWR PVM external interrupts lines
PWR_EXTI_LINE_PVM2
PWR_EXTI_LINE_PVM3
PWR_EXTI_LINE_PVM4
PWR PVM event lines
PWR_EVENT_LINE_PVM2
PWR_EVENT_LINE_PVM3
PWR_EVENT_LINE_PVM4
PWR Status Flags
PWR_FLAG_PVMO1
PWR_FLAG_PVMO2
PWR_FLAG_PVMO3
PWR_FLAG_PVMO4
PWR_FLAG_REGLPF
PWR_FLAG_REGLPS
PWR_FLAG_SB
PWR_FLAG_VOSF
PWR_FLAG_WU
PWR_FLAG_WUF1
PWR_FLAG_WUF2
PWR_FLAG_WUF3
PWR_FLAG_WUF4
PWR_FLAG_WUF5
PWR_FLAG_WUFI
PWR Extended Exported Macros
__HAL_PWR_PVM1_EXTI_DISABLE_EVENT
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_DISABLE_IT
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_EVENT
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_IT
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_GENERATE_SWIT
__HAL_PWR_PVM1_EXTI_GET_FLAG
__HAL_PWR_PVM2_EXTI_CLEAR_FLAG
__HAL_PWR_PVM2_EXTI_DISABLE_EVENT
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_DISABLE_IT
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_EVENT
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_IT
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_GENERATE_SWIT
__HAL_PWR_PVM2_EXTI_GET_FLAG
__HAL_PWR_PVM3_EXTI_CLEAR_FLAG
__HAL_PWR_PVM3_EXTI_DISABLE_EVENT
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_DISABLE_IT
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_EVENT
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_IT
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_GENERATE_SWIT
__HAL_PWR_PVM3_EXTI_GET_FLAG
__HAL_PWR_PVM4_EXTI_CLEAR_FLAG
__HAL_PWR_PVM4_EXTI_DISABLE_EVENT
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_DISABLE_IT
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_EVENT
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_IT
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_GENERATE_SWIT
__HAL_PWR_PVM4_EXTI_GET_FLAG
__HAL_PWR_VOLTAGESCALING_CONFIG
PWR Extended Private Macros
IS_PWR_BATTERY_RESISTOR_SELECT
IS_PWR_GPIO
IS_PWR_GPIO_BIT_NUMBER
IS_PWR_PVM_MODE
IS_PWR_PVM_TYPE
IS_PWR_VOLTAGE_SCALING_RANGE
IS_PWR_WAKEUP_PIN
Defines
PWR_PORTG_AVAILABLE_PINS
QSPI
QSPI_FUNCTIONAL_MODE_INDIRECT_READ
QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE
QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED
QSPI Private Macros
IS_QSPI_ADDRESS_SIZE
IS_QSPI_ALTERNATE_BYTES_MODE
IS_QSPI_ALTERNATE_BYTES_SIZE
IS_QSPI_AUTOMATIC_STOP
IS_QSPI_CLOCK_MODE
IS_QSPI_CLOCK_PRESCALER
IS_QSPI_CS_HIGH_TIME
IS_QSPI_DATA_MODE
IS_QSPI_DDR_HHC
IS_QSPI_DDR_MODE
IS_QSPI_DUAL_FLASH_MODE
IS_QSPI_DUMMY_CYCLES
IS_QSPI_FIFO_THRESHOLD
IS_QSPI_FLASH_ID
IS_QSPI_FLASH_SIZE
IS_QSPI_FUNCTIONAL_MODE
IS_QSPI_INSTRUCTION
IS_QSPI_INSTRUCTION_MODE
IS_QSPI_INTERVAL
IS_QSPI_MATCH_MODE
IS_QSPI_SIOO_MODE
IS_QSPI_SSHIFT
IS_QSPI_STATUS_BYTES_SIZE
IS_QSPI_TIMEOUT_ACTIVATION
IS_QSPI_TIMEOUT_PERIOD
QSPI Exported Functions
HAL_QSPI_Init
HAL_QSPI_MspDeInit
HAL_QSPI_MspInit
Input and Output operation functions
HAL_QSPI_AutoPolling
HAL_QSPI_AutoPolling_IT
HAL_QSPI_CmdCpltCallback
HAL_QSPI_Command
HAL_QSPI_Command_IT
HAL_QSPI_ErrorCallback
HAL_QSPI_FifoThresholdCallback
HAL_QSPI_IRQHandler
HAL_QSPI_MemoryMapped
HAL_QSPI_Receive
HAL_QSPI_Receive_DMA
HAL_QSPI_Receive_IT
HAL_QSPI_RegisterCallback
HAL_QSPI_RxCpltCallback
HAL_QSPI_RxHalfCpltCallback
HAL_QSPI_StatusMatchCallback
HAL_QSPI_TimeOutCallback
HAL_QSPI_Transmit
HAL_QSPI_Transmit_DMA
HAL_QSPI_Transmit_IT
HAL_QSPI_TxCpltCallback
HAL_QSPI_TxHalfCpltCallback
HAL_QSPI_UnRegisterCallback
Peripheral Control and State functions
HAL_QSPI_Abort_IT
HAL_QSPI_GetError
HAL_QSPI_GetFifoThreshold
HAL_QSPI_GetState
HAL_QSPI_SetFifoThreshold
HAL_QSPI_SetFlashID
HAL_QSPI_SetTimeout
QSPI Private Functions
QSPI_DMAAbortCplt
QSPI_DMAError
QSPI_DMARxCplt
QSPI_DMARxHalfCplt
QSPI_DMATxCplt
QSPI_DMATxHalfCplt
QSPI_WaitFlagStateUntilTimeout
QSPI Exported Types
QSPI_HandleTypeDef
Enumerations
HAL_QSPI_StateTypeDef
Data Structures
__QSPI_HandleTypeDef
QSPI_CommandTypeDef
QSPI_AutoPollingTypeDef
QSPI_MemoryMappedTypeDef
QSPI Exported Constants
HAL_QSPI_ERROR_INVALID_CALLBACK
HAL_QSPI_ERROR_INVALID_PARAM
HAL_QSPI_ERROR_NONE
HAL_QSPI_ERROR_TIMEOUT
HAL_QSPI_ERROR_TRANSFER
QSPI Sample Shifting
QSPI_SAMPLE_SHIFTING_NONE
QSPI ChipSelect High Time
QSPI_CS_HIGH_TIME_2_CYCLE
QSPI_CS_HIGH_TIME_3_CYCLE
QSPI_CS_HIGH_TIME_4_CYCLE
QSPI_CS_HIGH_TIME_5_CYCLE
QSPI_CS_HIGH_TIME_6_CYCLE
QSPI_CS_HIGH_TIME_7_CYCLE
QSPI_CS_HIGH_TIME_8_CYCLE
QSPI Clock Mode
QSPI_CLOCK_MODE_3
QSPI Flash Select
QSPI_FLASH_ID_2
QSPI Dual Flash Mode
QSPI_DUALFLASH_ENABLE
QSPI Address Size
QSPI_ADDRESS_24_BITS
QSPI_ADDRESS_32_BITS
QSPI_ADDRESS_8_BITS
QSPI Alternate Bytes Size
QSPI_ALTERNATE_BYTES_24_BITS
QSPI_ALTERNATE_BYTES_32_BITS
QSPI_ALTERNATE_BYTES_8_BITS
QSPI Instruction Mode
QSPI_INSTRUCTION_2_LINES
QSPI_INSTRUCTION_4_LINES
QSPI_INSTRUCTION_NONE
QSPI Address Mode
QSPI_ADDRESS_2_LINES
QSPI_ADDRESS_4_LINES
QSPI_ADDRESS_NONE
QSPI Alternate Bytes Mode
QSPI_ALTERNATE_BYTES_2_LINES
QSPI_ALTERNATE_BYTES_4_LINES
QSPI_ALTERNATE_BYTES_NONE
QSPI Data Mode
QSPI_DATA_2_LINES
QSPI_DATA_4_LINES
QSPI_DATA_NONE
QSPI DDR Mode
QSPI_DDR_MODE_ENABLE
QSPI DDR Data Output Delay
QSPI_DDR_HHC_HALF_CLK_DELAY
QSPI Send Instruction Mode
QSPI_SIOO_INST_ONLY_FIRST_CMD
QSPI Match Mode
QSPI_MATCH_MODE_OR
QSPI Automatic Stop
QSPI_AUTOMATIC_STOP_ENABLE
QSPI Timeout Activation
QSPI_TIMEOUT_COUNTER_ENABLE
QSPI Flags
QSPI_FLAG_FT
QSPI_FLAG_SM
QSPI_FLAG_TC
QSPI_FLAG_TE
QSPI_FLAG_TO
QSPI Interrupts
QSPI_IT_SM
QSPI_IT_TC
QSPI_IT_TE
QSPI_IT_TO
QSPI Timeout definition
QSPI Exported Macros
__HAL_QSPI_DISABLE
__HAL_QSPI_DISABLE_IT
__HAL_QSPI_ENABLE
__HAL_QSPI_ENABLE_IT
__HAL_QSPI_GET_FLAG
__HAL_QSPI_GET_IT_SOURCE
__HAL_QSPI_RESET_HANDLE_STATE
RCC
CLOCKSWITCH_TIMEOUT_VALUE
CR_REG_INDEX
CRRCR_REG_INDEX
CSR_REG_INDEX
HSE_TIMEOUT_VALUE
HSI48_TIMEOUT_VALUE
HSI_TIMEOUT_VALUE
LSI_TIMEOUT_VALUE
PLL_TIMEOUT_VALUE
RCC_CLOCKTYPE_ALL
RCC_FLAG_MASK
RCC Private Macros
IS_RCC_HCLK
IS_RCC_HSE
IS_RCC_HSI
IS_RCC_HSI48
IS_RCC_HSI_CALIBRATION_VALUE
IS_RCC_LSE
IS_RCC_LSE_DRIVE
IS_RCC_LSI
IS_RCC_MCO
IS_RCC_MCO1SOURCE
IS_RCC_MCODIV
IS_RCC_OSCILLATORTYPE
IS_RCC_PCLK
IS_RCC_PLL
IS_RCC_PLLM_VALUE
IS_RCC_PLLN_VALUE
IS_RCC_PLLP_VALUE
IS_RCC_PLLQ_VALUE
IS_RCC_PLLR_VALUE
IS_RCC_PLLSOURCE
IS_RCC_RTCCLKSOURCE
IS_RCC_SYSCLKSOURCE
RCC_GET_MCO_GPIO_AF
RCC_GET_MCO_GPIO_INDEX
RCC_GET_MCO_GPIO_PIN
RCC_GET_MCO_GPIO_PORT
RCC_PLL_OSCSOURCE_CONFIG
RCC Private Functions
RCC Exported Functions
HAL_RCC_DeInit
HAL_RCC_OscConfig
Peripheral Control functions
HAL_RCC_DisableLSECSS
HAL_RCC_EnableCSS
HAL_RCC_EnableLSECSS
HAL_RCC_GetClockConfig
HAL_RCC_GetHCLKFreq
HAL_RCC_GetOscConfig
HAL_RCC_GetPCLK1Freq
HAL_RCC_GetPCLK2Freq
HAL_RCC_GetSysClockFreq
HAL_RCC_MCOConfig
HAL_RCC_NMI_IRQHandler
RCC Exported Types
RCC_OscInitTypeDef
RCC_ClkInitTypeDef
RCC Exported Constants
RCC_LSE_TIMEOUT_VALUE
Oscillator Type
RCC_OSCILLATORTYPE_HSI
RCC_OSCILLATORTYPE_HSI48
RCC_OSCILLATORTYPE_LSE
RCC_OSCILLATORTYPE_LSI
RCC_OSCILLATORTYPE_NONE
HSE Config
RCC_HSE_OFF
RCC_HSE_ON
LSE Config
RCC_LSE_OFF
RCC_LSE_ON
HSI Config
RCC_HSI_ON
RCC_HSICALIBRATION_DEFAULT
LSI Config
RCC_LSI_ON
HSI48 Config
RCC_HSI48_ON
PLL Config
RCC_PLL_OFF
RCC_PLL_ON
PLLM Clock Divider
RCC_PLLM_DIV10
RCC_PLLM_DIV11
RCC_PLLM_DIV12
RCC_PLLM_DIV13
RCC_PLLM_DIV14
RCC_PLLM_DIV15
RCC_PLLM_DIV16
RCC_PLLM_DIV2
RCC_PLLM_DIV3
RCC_PLLM_DIV4
RCC_PLLM_DIV5
RCC_PLLM_DIV6
RCC_PLLM_DIV7
RCC_PLLM_DIV8
RCC_PLLM_DIV9
PLLP Clock Divider
RCC_PLLP_DIV11
RCC_PLLP_DIV12
RCC_PLLP_DIV13
RCC_PLLP_DIV14
RCC_PLLP_DIV15
RCC_PLLP_DIV16
RCC_PLLP_DIV17
RCC_PLLP_DIV18
RCC_PLLP_DIV19
RCC_PLLP_DIV2
RCC_PLLP_DIV20
RCC_PLLP_DIV21
RCC_PLLP_DIV22
RCC_PLLP_DIV23
RCC_PLLP_DIV24
RCC_PLLP_DIV25
RCC_PLLP_DIV26
RCC_PLLP_DIV27
RCC_PLLP_DIV28
RCC_PLLP_DIV29
RCC_PLLP_DIV3
RCC_PLLP_DIV30
RCC_PLLP_DIV31
RCC_PLLP_DIV4
RCC_PLLP_DIV5
RCC_PLLP_DIV6
RCC_PLLP_DIV7
RCC_PLLP_DIV8
RCC_PLLP_DIV9
PLLQ Clock Divider
RCC_PLLQ_DIV4
RCC_PLLQ_DIV6
RCC_PLLQ_DIV8
PLLR Clock Divider
RCC_PLLR_DIV4
RCC_PLLR_DIV6
RCC_PLLR_DIV8
PLL Clock Source
RCC_PLLSOURCE_HSI
RCC_PLLSOURCE_NONE
PLL Clock Output
RCC_PLL_ADCCLK
RCC_PLL_SYSCLK
System Clock Type
RCC_CLOCKTYPE_PCLK1
RCC_CLOCKTYPE_PCLK2
RCC_CLOCKTYPE_SYSCLK
System Clock Source
RCC_SYSCLKSOURCE_HSI
RCC_SYSCLKSOURCE_PLLCLK
System Clock Source Status
RCC_SYSCLKSOURCE_STATUS_HSI
RCC_SYSCLKSOURCE_STATUS_PLLCLK
AHB Clock Source
RCC_SYSCLK_DIV128
RCC_SYSCLK_DIV16
RCC_SYSCLK_DIV2
RCC_SYSCLK_DIV256
RCC_SYSCLK_DIV4
RCC_SYSCLK_DIV512
RCC_SYSCLK_DIV64
RCC_SYSCLK_DIV8
APB1 APB2 Clock Source
RCC_HCLK_DIV16
RCC_HCLK_DIV2
RCC_HCLK_DIV4
RCC_HCLK_DIV8
RTC Clock Source
RCC_RTCCLKSOURCE_LSE
RCC_RTCCLKSOURCE_LSI
RCC_RTCCLKSOURCE_NONE
MCO Index
RCC_MCO1
RCC_MCO1_INDEX
RCC_MCO_GPIOAF_MASK
RCC_MCO_GPIOAF_POS
RCC_MCO_GPIOPORT_MASK
RCC_MCO_GPIOPORT_POS
RCC_MCO_INDEX_MASK
RCC_MCO_INDEX_POS
RCC_MCO_PA8
RCC_MCO_PG10
MCO1 Clock Source
RCC_MCO1SOURCE_HSI
RCC_MCO1SOURCE_HSI48
RCC_MCO1SOURCE_LSE
RCC_MCO1SOURCE_LSI
RCC_MCO1SOURCE_NOCLOCK
RCC_MCO1SOURCE_PLLCLK
RCC_MCO1SOURCE_SYSCLK
MCO1 Clock Prescaler
RCC_MCODIV_16
RCC_MCODIV_2
RCC_MCODIV_4
RCC_MCODIV_8
Interrupts
RCC_IT_HSERDY
RCC_IT_HSI48RDY
RCC_IT_HSIRDY
RCC_IT_LSECSS
RCC_IT_LSERDY
RCC_IT_LSIRDY
RCC_IT_PLLRDY
Flags
RCC_FLAG_HSERDY
RCC_FLAG_HSI48RDY
RCC_FLAG_HSIRDY
RCC_FLAG_IWDGRST
RCC_FLAG_LPWRRST
RCC_FLAG_LSECSSD
RCC_FLAG_LSERDY
RCC_FLAG_LSIRDY
RCC_FLAG_OBLRST
RCC_FLAG_PINRST
RCC_FLAG_PLLRDY
RCC_FLAG_SFTRST
RCC_FLAG_WWDGRST
LSE Drive Config
RCC_LSEDRIVE_LOW
RCC_LSEDRIVE_MEDIUMHIGH
RCC_LSEDRIVE_MEDIUMLOW
RCC Exported Macros
__HAL_RCC_CORDIC_CLK_ENABLE
__HAL_RCC_CRC_CLK_DISABLE
__HAL_RCC_CRC_CLK_ENABLE
__HAL_RCC_DMA1_CLK_DISABLE
__HAL_RCC_DMA1_CLK_ENABLE
__HAL_RCC_DMA2_CLK_DISABLE
__HAL_RCC_DMA2_CLK_ENABLE
__HAL_RCC_DMAMUX1_CLK_DISABLE
__HAL_RCC_DMAMUX1_CLK_ENABLE
__HAL_RCC_FLASH_CLK_DISABLE
__HAL_RCC_FLASH_CLK_ENABLE
__HAL_RCC_FMAC_CLK_DISABLE
__HAL_RCC_FMAC_CLK_ENABLE
AHB2 Peripheral Clock Enable Disable
__HAL_RCC_ADC12_CLK_ENABLE
__HAL_RCC_ADC345_CLK_DISABLE
__HAL_RCC_ADC345_CLK_ENABLE
__HAL_RCC_DAC1_CLK_DISABLE
__HAL_RCC_DAC1_CLK_ENABLE
__HAL_RCC_DAC2_CLK_DISABLE
__HAL_RCC_DAC2_CLK_ENABLE
__HAL_RCC_DAC3_CLK_DISABLE
__HAL_RCC_DAC3_CLK_ENABLE
__HAL_RCC_DAC4_CLK_DISABLE
__HAL_RCC_DAC4_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_DISABLE
__HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOB_CLK_DISABLE
__HAL_RCC_GPIOB_CLK_ENABLE
__HAL_RCC_GPIOC_CLK_DISABLE
__HAL_RCC_GPIOC_CLK_ENABLE
__HAL_RCC_GPIOD_CLK_DISABLE
__HAL_RCC_GPIOD_CLK_ENABLE
__HAL_RCC_GPIOE_CLK_DISABLE
__HAL_RCC_GPIOE_CLK_ENABLE
__HAL_RCC_GPIOF_CLK_DISABLE
__HAL_RCC_GPIOF_CLK_ENABLE
__HAL_RCC_GPIOG_CLK_DISABLE
__HAL_RCC_GPIOG_CLK_ENABLE
__HAL_RCC_RNG_CLK_DISABLE
__HAL_RCC_RNG_CLK_ENABLE
AHB3 Peripheral Clock Enable Disable
__HAL_RCC_FMC_CLK_ENABLE
__HAL_RCC_QSPI_CLK_DISABLE
__HAL_RCC_QSPI_CLK_ENABLE
APB1 Peripheral Clock Enable Disable
__HAL_RCC_CRS_CLK_ENABLE
__HAL_RCC_FDCAN_CLK_DISABLE
__HAL_RCC_FDCAN_CLK_ENABLE
__HAL_RCC_I2C1_CLK_DISABLE
__HAL_RCC_I2C1_CLK_ENABLE
__HAL_RCC_I2C2_CLK_DISABLE
__HAL_RCC_I2C2_CLK_ENABLE
__HAL_RCC_I2C3_CLK_DISABLE
__HAL_RCC_I2C3_CLK_ENABLE
__HAL_RCC_I2C4_CLK_DISABLE
__HAL_RCC_I2C4_CLK_ENABLE
__HAL_RCC_LPTIM1_CLK_DISABLE
__HAL_RCC_LPTIM1_CLK_ENABLE
__HAL_RCC_LPUART1_CLK_DISABLE
__HAL_RCC_LPUART1_CLK_ENABLE
__HAL_RCC_PWR_CLK_DISABLE
__HAL_RCC_PWR_CLK_ENABLE
__HAL_RCC_RTCAPB_CLK_DISABLE
__HAL_RCC_RTCAPB_CLK_ENABLE
__HAL_RCC_SPI2_CLK_DISABLE
__HAL_RCC_SPI2_CLK_ENABLE
__HAL_RCC_SPI3_CLK_DISABLE
__HAL_RCC_SPI3_CLK_ENABLE
__HAL_RCC_TIM2_CLK_DISABLE
__HAL_RCC_TIM2_CLK_ENABLE
__HAL_RCC_TIM3_CLK_DISABLE
__HAL_RCC_TIM3_CLK_ENABLE
__HAL_RCC_TIM4_CLK_DISABLE
__HAL_RCC_TIM4_CLK_ENABLE
__HAL_RCC_TIM5_CLK_DISABLE
__HAL_RCC_TIM5_CLK_ENABLE
__HAL_RCC_TIM6_CLK_DISABLE
__HAL_RCC_TIM6_CLK_ENABLE
__HAL_RCC_TIM7_CLK_DISABLE
__HAL_RCC_TIM7_CLK_ENABLE
__HAL_RCC_UART4_CLK_DISABLE
__HAL_RCC_UART4_CLK_ENABLE
__HAL_RCC_UART5_CLK_DISABLE
__HAL_RCC_UART5_CLK_ENABLE
__HAL_RCC_UCPD1_CLK_DISABLE
__HAL_RCC_UCPD1_CLK_ENABLE
__HAL_RCC_USART2_CLK_DISABLE
__HAL_RCC_USART2_CLK_ENABLE
__HAL_RCC_USART3_CLK_DISABLE
__HAL_RCC_USART3_CLK_ENABLE
__HAL_RCC_USB_CLK_DISABLE
__HAL_RCC_USB_CLK_ENABLE
__HAL_RCC_WWDG_CLK_DISABLE
__HAL_RCC_WWDG_CLK_ENABLE
APB2 Peripheral Clock Enable Disable
__HAL_RCC_HRTIM1_CLK_ENABLE
__HAL_RCC_SAI1_CLK_DISABLE
__HAL_RCC_SAI1_CLK_ENABLE
__HAL_RCC_SPI1_CLK_DISABLE
__HAL_RCC_SPI1_CLK_ENABLE
__HAL_RCC_SPI4_CLK_DISABLE
__HAL_RCC_SPI4_CLK_ENABLE
__HAL_RCC_SYSCFG_CLK_DISABLE
__HAL_RCC_SYSCFG_CLK_ENABLE
__HAL_RCC_TIM15_CLK_DISABLE
__HAL_RCC_TIM15_CLK_ENABLE
__HAL_RCC_TIM16_CLK_DISABLE
__HAL_RCC_TIM16_CLK_ENABLE
__HAL_RCC_TIM17_CLK_DISABLE
__HAL_RCC_TIM17_CLK_ENABLE
__HAL_RCC_TIM1_CLK_DISABLE
__HAL_RCC_TIM1_CLK_ENABLE
__HAL_RCC_TIM20_CLK_DISABLE
__HAL_RCC_TIM20_CLK_ENABLE
__HAL_RCC_TIM8_CLK_DISABLE
__HAL_RCC_TIM8_CLK_ENABLE
__HAL_RCC_USART1_CLK_DISABLE
__HAL_RCC_USART1_CLK_ENABLE
AHB1 Peripheral Clock Enabled or Disabled Status
__HAL_RCC_CORDIC_IS_CLK_ENABLED
__HAL_RCC_CRC_IS_CLK_DISABLED
__HAL_RCC_CRC_IS_CLK_ENABLED
__HAL_RCC_DMA1_IS_CLK_DISABLED
__HAL_RCC_DMA1_IS_CLK_ENABLED
__HAL_RCC_DMA2_IS_CLK_DISABLED
__HAL_RCC_DMA2_IS_CLK_ENABLED
__HAL_RCC_DMAMUX1_IS_CLK_DISABLED
__HAL_RCC_DMAMUX1_IS_CLK_ENABLED
__HAL_RCC_FLASH_IS_CLK_DISABLED
__HAL_RCC_FLASH_IS_CLK_ENABLED
__HAL_RCC_FMAC_IS_CLK_DISABLED
__HAL_RCC_FMAC_IS_CLK_ENABLED
AHB2 Peripheral Clock Enabled or Disabled Status
__HAL_RCC_ADC12_IS_CLK_ENABLED
__HAL_RCC_ADC345_IS_CLK_DISABLED
__HAL_RCC_ADC345_IS_CLK_ENABLED
__HAL_RCC_DAC1_IS_CLK_DISABLED
__HAL_RCC_DAC1_IS_CLK_ENABLED
__HAL_RCC_DAC2_IS_CLK_DISABLED
__HAL_RCC_DAC2_IS_CLK_ENABLED
__HAL_RCC_DAC3_IS_CLK_DISABLED
__HAL_RCC_DAC3_IS_CLK_ENABLED
__HAL_RCC_DAC4_IS_CLK_DISABLED
__HAL_RCC_DAC4_IS_CLK_ENABLED
__HAL_RCC_GPIOA_IS_CLK_DISABLED
__HAL_RCC_GPIOA_IS_CLK_ENABLED
__HAL_RCC_GPIOB_IS_CLK_DISABLED
__HAL_RCC_GPIOB_IS_CLK_ENABLED
__HAL_RCC_GPIOC_IS_CLK_DISABLED
__HAL_RCC_GPIOC_IS_CLK_ENABLED
__HAL_RCC_GPIOD_IS_CLK_DISABLED
__HAL_RCC_GPIOD_IS_CLK_ENABLED
__HAL_RCC_GPIOE_IS_CLK_DISABLED
__HAL_RCC_GPIOE_IS_CLK_ENABLED
__HAL_RCC_GPIOF_IS_CLK_DISABLED
__HAL_RCC_GPIOF_IS_CLK_ENABLED
__HAL_RCC_GPIOG_IS_CLK_DISABLED
__HAL_RCC_GPIOG_IS_CLK_ENABLED
__HAL_RCC_RNG_IS_CLK_DISABLED
__HAL_RCC_RNG_IS_CLK_ENABLED
AHB3 Peripheral Clock Enabled or Disabled Status
__HAL_RCC_FMC_IS_CLK_ENABLED
__HAL_RCC_QSPI_IS_CLK_DISABLED
__HAL_RCC_QSPI_IS_CLK_ENABLED
APB1 Peripheral Clock Enabled or Disabled Status
__HAL_RCC_CRS_IS_CLK_ENABLED
__HAL_RCC_FDCAN_IS_CLK_DISABLED
__HAL_RCC_FDCAN_IS_CLK_ENABLED
__HAL_RCC_I2C1_IS_CLK_DISABLED
__HAL_RCC_I2C1_IS_CLK_ENABLED
__HAL_RCC_I2C2_IS_CLK_DISABLED
__HAL_RCC_I2C2_IS_CLK_ENABLED
__HAL_RCC_I2C3_IS_CLK_DISABLED
__HAL_RCC_I2C3_IS_CLK_ENABLED
__HAL_RCC_I2C4_IS_CLK_DISABLED
__HAL_RCC_I2C4_IS_CLK_ENABLED
__HAL_RCC_LPTIM1_IS_CLK_DISABLED
__HAL_RCC_LPTIM1_IS_CLK_ENABLED
__HAL_RCC_LPUART1_IS_CLK_DISABLED
__HAL_RCC_LPUART1_IS_CLK_ENABLED
__HAL_RCC_PWR_IS_CLK_DISABLED
__HAL_RCC_PWR_IS_CLK_ENABLED
__HAL_RCC_RTCAPB_IS_CLK_DISABLED
__HAL_RCC_RTCAPB_IS_CLK_ENABLED
__HAL_RCC_SPI2_IS_CLK_DISABLED
__HAL_RCC_SPI2_IS_CLK_ENABLED
__HAL_RCC_SPI3_IS_CLK_DISABLED
__HAL_RCC_SPI3_IS_CLK_ENABLED
__HAL_RCC_TIM2_IS_CLK_DISABLED
__HAL_RCC_TIM2_IS_CLK_ENABLED
__HAL_RCC_TIM3_IS_CLK_DISABLED
__HAL_RCC_TIM3_IS_CLK_ENABLED
__HAL_RCC_TIM4_IS_CLK_DISABLED
__HAL_RCC_TIM4_IS_CLK_ENABLED
__HAL_RCC_TIM5_IS_CLK_DISABLED
__HAL_RCC_TIM5_IS_CLK_ENABLED
__HAL_RCC_TIM6_IS_CLK_DISABLED
__HAL_RCC_TIM6_IS_CLK_ENABLED
__HAL_RCC_TIM7_IS_CLK_DISABLED
__HAL_RCC_TIM7_IS_CLK_ENABLED
__HAL_RCC_UART4_IS_CLK_DISABLED
__HAL_RCC_UART4_IS_CLK_ENABLED
__HAL_RCC_UART5_IS_CLK_DISABLED
__HAL_RCC_UART5_IS_CLK_ENABLED
__HAL_RCC_UCPD1_IS_CLK_DISABLED
__HAL_RCC_UCPD1_IS_CLK_ENABLED
__HAL_RCC_USART2_IS_CLK_DISABLED
__HAL_RCC_USART2_IS_CLK_ENABLED
__HAL_RCC_USART3_IS_CLK_DISABLED
__HAL_RCC_USART3_IS_CLK_ENABLED
__HAL_RCC_USB_IS_CLK_DISABLED
__HAL_RCC_USB_IS_CLK_ENABLED
__HAL_RCC_WWDG_IS_CLK_DISABLED
__HAL_RCC_WWDG_IS_CLK_ENABLED
APB2 Peripheral Clock Enabled or Disabled Status
__HAL_RCC_HRTIM1_IS_CLK_ENABLED
__HAL_RCC_SAI1_IS_CLK_DISABLED
__HAL_RCC_SAI1_IS_CLK_ENABLED
__HAL_RCC_SPI1_IS_CLK_DISABLED
__HAL_RCC_SPI1_IS_CLK_ENABLED
__HAL_RCC_SPI4_IS_CLK_DISABLED
__HAL_RCC_SPI4_IS_CLK_ENABLED
__HAL_RCC_SYSCFG_IS_CLK_DISABLED
__HAL_RCC_SYSCFG_IS_CLK_ENABLED
__HAL_RCC_TIM15_IS_CLK_DISABLED
__HAL_RCC_TIM15_IS_CLK_ENABLED
__HAL_RCC_TIM16_IS_CLK_DISABLED
__HAL_RCC_TIM16_IS_CLK_ENABLED
__HAL_RCC_TIM17_IS_CLK_DISABLED
__HAL_RCC_TIM17_IS_CLK_ENABLED
__HAL_RCC_TIM1_IS_CLK_DISABLED
__HAL_RCC_TIM1_IS_CLK_ENABLED
__HAL_RCC_TIM20_IS_CLK_DISABLED
__HAL_RCC_TIM20_IS_CLK_ENABLED
__HAL_RCC_TIM8_IS_CLK_DISABLED
__HAL_RCC_TIM8_IS_CLK_ENABLED
__HAL_RCC_USART1_IS_CLK_DISABLED
__HAL_RCC_USART1_IS_CLK_ENABLED
AHB1 Peripheral Force Release Reset
__HAL_RCC_AHB1_RELEASE_RESET
__HAL_RCC_CORDIC_FORCE_RESET
__HAL_RCC_CORDIC_RELEASE_RESET
__HAL_RCC_CRC_FORCE_RESET
__HAL_RCC_CRC_RELEASE_RESET
__HAL_RCC_DMA1_FORCE_RESET
__HAL_RCC_DMA1_RELEASE_RESET
__HAL_RCC_DMA2_FORCE_RESET
__HAL_RCC_DMA2_RELEASE_RESET
__HAL_RCC_DMAMUX1_FORCE_RESET
__HAL_RCC_DMAMUX1_RELEASE_RESET
__HAL_RCC_FLASH_FORCE_RESET
__HAL_RCC_FLASH_RELEASE_RESET
__HAL_RCC_FMAC_FORCE_RESET
__HAL_RCC_FMAC_RELEASE_RESET
AHB2 Peripheral Force Release Reset
__HAL_RCC_ADC12_RELEASE_RESET
__HAL_RCC_ADC345_FORCE_RESET
__HAL_RCC_ADC345_RELEASE_RESET
__HAL_RCC_AHB2_FORCE_RESET
__HAL_RCC_AHB2_RELEASE_RESET
__HAL_RCC_DAC1_FORCE_RESET
__HAL_RCC_DAC1_RELEASE_RESET
__HAL_RCC_DAC2_FORCE_RESET
__HAL_RCC_DAC2_RELEASE_RESET
__HAL_RCC_DAC3_FORCE_RESET
__HAL_RCC_DAC3_RELEASE_RESET
__HAL_RCC_DAC4_FORCE_RESET
__HAL_RCC_DAC4_RELEASE_RESET
__HAL_RCC_GPIOA_FORCE_RESET
__HAL_RCC_GPIOA_RELEASE_RESET
__HAL_RCC_GPIOB_FORCE_RESET
__HAL_RCC_GPIOB_RELEASE_RESET
__HAL_RCC_GPIOC_FORCE_RESET
__HAL_RCC_GPIOC_RELEASE_RESET
__HAL_RCC_GPIOD_FORCE_RESET
__HAL_RCC_GPIOD_RELEASE_RESET
__HAL_RCC_GPIOE_FORCE_RESET
__HAL_RCC_GPIOE_RELEASE_RESET
__HAL_RCC_GPIOF_FORCE_RESET
__HAL_RCC_GPIOF_RELEASE_RESET
__HAL_RCC_GPIOG_FORCE_RESET
__HAL_RCC_GPIOG_RELEASE_RESET
__HAL_RCC_RNG_FORCE_RESET
__HAL_RCC_RNG_RELEASE_RESET
AHB3 Peripheral Force Release Reset
__HAL_RCC_AHB3_RELEASE_RESET
__HAL_RCC_FMC_FORCE_RESET
__HAL_RCC_FMC_RELEASE_RESET
__HAL_RCC_QSPI_FORCE_RESET
__HAL_RCC_QSPI_RELEASE_RESET
APB1 Peripheral Force Release Reset
__HAL_RCC_APB1_RELEASE_RESET
__HAL_RCC_CRS_FORCE_RESET
__HAL_RCC_CRS_RELEASE_RESET
__HAL_RCC_FDCAN_FORCE_RESET
__HAL_RCC_FDCAN_RELEASE_RESET
__HAL_RCC_I2C1_FORCE_RESET
__HAL_RCC_I2C1_RELEASE_RESET
__HAL_RCC_I2C2_FORCE_RESET
__HAL_RCC_I2C2_RELEASE_RESET
__HAL_RCC_I2C3_FORCE_RESET
__HAL_RCC_I2C3_RELEASE_RESET
__HAL_RCC_I2C4_FORCE_RESET
__HAL_RCC_I2C4_RELEASE_RESET
__HAL_RCC_LPTIM1_FORCE_RESET
__HAL_RCC_LPTIM1_RELEASE_RESET
__HAL_RCC_LPUART1_FORCE_RESET
__HAL_RCC_LPUART1_RELEASE_RESET
__HAL_RCC_PWR_FORCE_RESET
__HAL_RCC_PWR_RELEASE_RESET
__HAL_RCC_SPI2_FORCE_RESET
__HAL_RCC_SPI2_RELEASE_RESET
__HAL_RCC_SPI3_FORCE_RESET
__HAL_RCC_SPI3_RELEASE_RESET
__HAL_RCC_TIM2_FORCE_RESET
__HAL_RCC_TIM2_RELEASE_RESET
__HAL_RCC_TIM3_FORCE_RESET
__HAL_RCC_TIM3_RELEASE_RESET
__HAL_RCC_TIM4_FORCE_RESET
__HAL_RCC_TIM4_RELEASE_RESET
__HAL_RCC_TIM5_FORCE_RESET
__HAL_RCC_TIM5_RELEASE_RESET
__HAL_RCC_TIM6_FORCE_RESET
__HAL_RCC_TIM6_RELEASE_RESET
__HAL_RCC_TIM7_FORCE_RESET
__HAL_RCC_TIM7_RELEASE_RESET
__HAL_RCC_UART4_FORCE_RESET
__HAL_RCC_UART4_RELEASE_RESET
__HAL_RCC_UART5_FORCE_RESET
__HAL_RCC_UART5_RELEASE_RESET
__HAL_RCC_UCPD1_FORCE_RESET
__HAL_RCC_UCPD1_RELEASE_RESET
__HAL_RCC_USART2_FORCE_RESET
__HAL_RCC_USART2_RELEASE_RESET
__HAL_RCC_USART3_FORCE_RESET
__HAL_RCC_USART3_RELEASE_RESET
__HAL_RCC_USB_FORCE_RESET
__HAL_RCC_USB_RELEASE_RESET
APB2 Peripheral Force Release Reset
__HAL_RCC_APB2_RELEASE_RESET
__HAL_RCC_HRTIM1_FORCE_RESET
__HAL_RCC_HRTIM1_RELEASE_RESET
__HAL_RCC_SAI1_FORCE_RESET
__HAL_RCC_SAI1_RELEASE_RESET
__HAL_RCC_SPI1_FORCE_RESET
__HAL_RCC_SPI1_RELEASE_RESET
__HAL_RCC_SPI4_FORCE_RESET
__HAL_RCC_SPI4_RELEASE_RESET
__HAL_RCC_SYSCFG_FORCE_RESET
__HAL_RCC_SYSCFG_RELEASE_RESET
__HAL_RCC_TIM15_FORCE_RESET
__HAL_RCC_TIM15_RELEASE_RESET
__HAL_RCC_TIM16_FORCE_RESET
__HAL_RCC_TIM16_RELEASE_RESET
__HAL_RCC_TIM17_FORCE_RESET
__HAL_RCC_TIM17_RELEASE_RESET
__HAL_RCC_TIM1_FORCE_RESET
__HAL_RCC_TIM1_RELEASE_RESET
__HAL_RCC_TIM20_FORCE_RESET
__HAL_RCC_TIM20_RELEASE_RESET
__HAL_RCC_TIM8_FORCE_RESET
__HAL_RCC_TIM8_RELEASE_RESET
__HAL_RCC_USART1_FORCE_RESET
__HAL_RCC_USART1_RELEASE_RESET
AHB1 Peripheral Clock Sleep Enable Disable
__HAL_RCC_CORDIC_CLK_SLEEP_ENABLE
__HAL_RCC_CRC_CLK_SLEEP_DISABLE
__HAL_RCC_CRC_CLK_SLEEP_ENABLE
__HAL_RCC_DMA1_CLK_SLEEP_DISABLE
__HAL_RCC_DMA1_CLK_SLEEP_ENABLE
__HAL_RCC_DMA2_CLK_SLEEP_DISABLE
__HAL_RCC_DMA2_CLK_SLEEP_ENABLE
__HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE
__HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE
__HAL_RCC_FLASH_CLK_SLEEP_DISABLE
__HAL_RCC_FLASH_CLK_SLEEP_ENABLE
__HAL_RCC_FMAC_CLK_SLEEP_DISABLE
__HAL_RCC_FMAC_CLK_SLEEP_ENABLE
__HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
__HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
AHB2 Peripheral Clock Sleep Enable Disable
__HAL_RCC_ADC12_CLK_SLEEP_ENABLE
__HAL_RCC_ADC345_CLK_SLEEP_DISABLE
__HAL_RCC_ADC345_CLK_SLEEP_ENABLE
__HAL_RCC_CCM_CLK_SLEEP_DISABLE
__HAL_RCC_CCM_CLK_SLEEP_ENABLE
__HAL_RCC_DAC1_CLK_SLEEP_DISABLE
__HAL_RCC_DAC1_CLK_SLEEP_ENABLE
__HAL_RCC_DAC2_CLK_SLEEP_DISABLE
__HAL_RCC_DAC2_CLK_SLEEP_ENABLE
__HAL_RCC_DAC3_CLK_SLEEP_DISABLE
__HAL_RCC_DAC3_CLK_SLEEP_ENABLE
__HAL_RCC_DAC4_CLK_SLEEP_DISABLE
__HAL_RCC_DAC4_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
__HAL_RCC_RNG_CLK_SLEEP_DISABLE
__HAL_RCC_RNG_CLK_SLEEP_ENABLE
__HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
__HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
AHB3 Peripheral Clock Sleep Enable Disable
__HAL_RCC_FMC_CLK_SLEEP_ENABLE
__HAL_RCC_QSPI_CLK_SLEEP_DISABLE
__HAL_RCC_QSPI_CLK_SLEEP_ENABLE
APB1 Peripheral Clock Sleep Enable Disable
__HAL_RCC_CRS_CLK_SLEEP_ENABLE
__HAL_RCC_FDCAN_CLK_SLEEP_DISABLE
__HAL_RCC_FDCAN_CLK_SLEEP_ENABLE
__HAL_RCC_I2C1_CLK_SLEEP_DISABLE
__HAL_RCC_I2C1_CLK_SLEEP_ENABLE
__HAL_RCC_I2C2_CLK_SLEEP_DISABLE
__HAL_RCC_I2C2_CLK_SLEEP_ENABLE
__HAL_RCC_I2C3_CLK_SLEEP_DISABLE
__HAL_RCC_I2C3_CLK_SLEEP_ENABLE
__HAL_RCC_I2C4_CLK_SLEEP_DISABLE
__HAL_RCC_I2C4_CLK_SLEEP_ENABLE
__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
__HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
__HAL_RCC_PWR_CLK_SLEEP_DISABLE
__HAL_RCC_PWR_CLK_SLEEP_ENABLE
__HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE
__HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE
__HAL_RCC_SPI2_CLK_SLEEP_DISABLE
__HAL_RCC_SPI2_CLK_SLEEP_ENABLE
__HAL_RCC_SPI3_CLK_SLEEP_DISABLE
__HAL_RCC_SPI3_CLK_SLEEP_ENABLE
__HAL_RCC_TIM2_CLK_SLEEP_DISABLE
__HAL_RCC_TIM2_CLK_SLEEP_ENABLE
__HAL_RCC_TIM3_CLK_SLEEP_DISABLE
__HAL_RCC_TIM3_CLK_SLEEP_ENABLE
__HAL_RCC_TIM4_CLK_SLEEP_DISABLE
__HAL_RCC_TIM4_CLK_SLEEP_ENABLE
__HAL_RCC_TIM5_CLK_SLEEP_DISABLE
__HAL_RCC_TIM5_CLK_SLEEP_ENABLE
__HAL_RCC_TIM6_CLK_SLEEP_DISABLE
__HAL_RCC_TIM6_CLK_SLEEP_ENABLE
__HAL_RCC_TIM7_CLK_SLEEP_DISABLE
__HAL_RCC_TIM7_CLK_SLEEP_ENABLE
__HAL_RCC_UART4_CLK_SLEEP_DISABLE
__HAL_RCC_UART4_CLK_SLEEP_ENABLE
__HAL_RCC_UART5_CLK_SLEEP_DISABLE
__HAL_RCC_UART5_CLK_SLEEP_ENABLE
__HAL_RCC_UCPD1_CLK_SLEEP_DISABLE
__HAL_RCC_UCPD1_CLK_SLEEP_ENABLE
__HAL_RCC_USART2_CLK_SLEEP_DISABLE
__HAL_RCC_USART2_CLK_SLEEP_ENABLE
__HAL_RCC_USART3_CLK_SLEEP_DISABLE
__HAL_RCC_USART3_CLK_SLEEP_ENABLE
__HAL_RCC_USB_CLK_SLEEP_DISABLE
__HAL_RCC_USB_CLK_SLEEP_ENABLE
__HAL_RCC_WWDG_CLK_SLEEP_DISABLE
__HAL_RCC_WWDG_CLK_SLEEP_ENABLE
APB2 Peripheral Clock Sleep Enable Disable
__HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE
__HAL_RCC_SAI1_CLK_SLEEP_DISABLE
__HAL_RCC_SAI1_CLK_SLEEP_ENABLE
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE
__HAL_RCC_SPI1_CLK_SLEEP_ENABLE
__HAL_RCC_SPI4_CLK_SLEEP_DISABLE
__HAL_RCC_SPI4_CLK_SLEEP_ENABLE
__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
__HAL_RCC_TIM15_CLK_SLEEP_DISABLE
__HAL_RCC_TIM15_CLK_SLEEP_ENABLE
__HAL_RCC_TIM16_CLK_SLEEP_DISABLE
__HAL_RCC_TIM16_CLK_SLEEP_ENABLE
__HAL_RCC_TIM17_CLK_SLEEP_DISABLE
__HAL_RCC_TIM17_CLK_SLEEP_ENABLE
__HAL_RCC_TIM1_CLK_SLEEP_DISABLE
__HAL_RCC_TIM1_CLK_SLEEP_ENABLE
__HAL_RCC_TIM20_CLK_SLEEP_DISABLE
__HAL_RCC_TIM20_CLK_SLEEP_ENABLE
__HAL_RCC_TIM8_CLK_SLEEP_DISABLE
__HAL_RCC_TIM8_CLK_SLEEP_ENABLE
__HAL_RCC_USART1_CLK_SLEEP_DISABLE
__HAL_RCC_USART1_CLK_SLEEP_ENABLE
AHB1 Peripheral Clock Sleep Enabled or Disabled Status
__HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED
AHB2 Peripheral Clock Sleep Enabled or Disabled Status
__HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED
__HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED
__HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED
AHB3 Peripheral Clock Sleep Enabled or Disabled Status
__HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED
__HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED
APB1 Peripheral Clock Sleep Enabled or Disabled Status
__HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED
__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED
__HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED
APB2 Peripheral Clock Sleep Enabled or Disabled Status
__HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED
RCC Backup Domain Reset
__HAL_RCC_BACKUPRESET_RELEASE
RCC RTC Clock Configuration
__HAL_RCC_RTC_ENABLE
Flags Interrupts Management
__HAL_RCC_CLEAR_RESET_FLAGS
__HAL_RCC_DISABLE_IT
__HAL_RCC_ENABLE_IT
__HAL_RCC_GET_FLAG
__HAL_RCC_GET_IT
Defines
__HAL_RCC_GET_PLLCLKOUT_CONFIG
__HAL_RCC_GET_RTC_SOURCE
__HAL_RCC_GET_SYSCLK_SOURCE
__HAL_RCC_HSE_CONFIG
__HAL_RCC_HSI48_DISABLE
__HAL_RCC_HSI48_ENABLE
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST
__HAL_RCC_HSI_DISABLE
__HAL_RCC_HSI_ENABLE
__HAL_RCC_HSISTOP_DISABLE
__HAL_RCC_HSISTOP_ENABLE
__HAL_RCC_LSE_CONFIG
__HAL_RCC_LSEDRIVE_CONFIG
__HAL_RCC_LSI_DISABLE
__HAL_RCC_LSI_ENABLE
__HAL_RCC_MCO1_CONFIG
__HAL_RCC_PLL_CONFIG
__HAL_RCC_PLL_DISABLE
__HAL_RCC_PLL_ENABLE
__HAL_RCC_PLL_PLLM_CONFIG
__HAL_RCC_PLL_PLLSOURCE_CONFIG
__HAL_RCC_PLLCLKOUT_DISABLE
__HAL_RCC_PLLCLKOUT_ENABLE
__HAL_RCC_RTC_CONFIG
__HAL_RCC_SYSCLK_CONFIG
RCCEx
DIVIDER_P_UPDATE
DIVIDER_Q_UPDATE
DIVIDER_R_UPDATE
LSCO_GPIO_PORT
LSCO_PIN
PLL_TIMEOUT_VALUE
RCCEx Private Functions
RCCEx Exported Functions
HAL_RCCEx_GetPeriphCLKFreq
HAL_RCCEx_PeriphCLKConfig
Extended Clock management functions
HAL_RCCEx_DisableLSECSS
HAL_RCCEx_EnableLSCO
HAL_RCCEx_EnableLSECSS
HAL_RCCEx_EnableLSECSS_IT
HAL_RCCEx_LSECSS_Callback
HAL_RCCEx_LSECSS_IRQHandler
Extended Clock Recovery System Control functions
HAL_RCCEx_CRS_ExpectedSyncCallback
HAL_RCCEx_CRS_IRQHandler
HAL_RCCEx_CRS_SyncOkCallback
HAL_RCCEx_CRS_SyncWarnCallback
HAL_RCCEx_CRSConfig
HAL_RCCEx_CRSGetSynchronizationInfo
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
HAL_RCCEx_CRSWaitSynchronization
RCCEx Exported Types
RCC_CRSInitTypeDef
RCC_CRSSynchroInfoTypeDef
RCCEx Exported Constants
RCC_LSCOSOURCE_LSI
Periph Clock Selection
RCC_PERIPHCLK_ADC345
RCC_PERIPHCLK_FDCAN
RCC_PERIPHCLK_I2C1
RCC_PERIPHCLK_I2C2
RCC_PERIPHCLK_I2C3
RCC_PERIPHCLK_I2C4
RCC_PERIPHCLK_I2S
RCC_PERIPHCLK_LPTIM1
RCC_PERIPHCLK_LPUART1
RCC_PERIPHCLK_QSPI
RCC_PERIPHCLK_RNG
RCC_PERIPHCLK_RTC
RCC_PERIPHCLK_SAI1
RCC_PERIPHCLK_UART4
RCC_PERIPHCLK_UART5
RCC_PERIPHCLK_USART1
RCC_PERIPHCLK_USART2
RCC_PERIPHCLK_USART3
RCC_PERIPHCLK_USB
USART1 Clock Source
RCC_USART1CLKSOURCE_LSE
RCC_USART1CLKSOURCE_PCLK2
RCC_USART1CLKSOURCE_SYSCLK
USART2 Clock Source
RCC_USART2CLKSOURCE_LSE
RCC_USART2CLKSOURCE_PCLK1
RCC_USART2CLKSOURCE_SYSCLK
USART3 Clock Source
RCC_USART3CLKSOURCE_LSE
RCC_USART3CLKSOURCE_PCLK1
RCC_USART3CLKSOURCE_SYSCLK
UART4 Clock Source
RCC_UART4CLKSOURCE_LSE
RCC_UART4CLKSOURCE_PCLK1
RCC_UART4CLKSOURCE_SYSCLK
UART5 Clock Source
RCC_UART5CLKSOURCE_LSE
RCC_UART5CLKSOURCE_PCLK1
RCC_UART5CLKSOURCE_SYSCLK
LPUART1 Clock Source
RCC_LPUART1CLKSOURCE_LSE
RCC_LPUART1CLKSOURCE_PCLK1
RCC_LPUART1CLKSOURCE_SYSCLK
I2C1 Clock Source
RCC_I2C1CLKSOURCE_PCLK1
RCC_I2C1CLKSOURCE_SYSCLK
I2C2 Clock Source
RCC_I2C2CLKSOURCE_PCLK1
RCC_I2C2CLKSOURCE_SYSCLK
I2C3 Clock Source
RCC_I2C3CLKSOURCE_PCLK1
RCC_I2C3CLKSOURCE_SYSCLK
LPTIM1 Clock Source
RCC_LPTIM1CLKSOURCE_LSE
RCC_LPTIM1CLKSOURCE_LSI
RCC_LPTIM1CLKSOURCE_PCLK1
SAI1 Clock Source
RCC_SAI1CLKSOURCE_HSI
RCC_SAI1CLKSOURCE_PLL
RCC_SAI1CLKSOURCE_SYSCLK
I2S Clock Source
RCC_I2SCLKSOURCE_HSI
RCC_I2SCLKSOURCE_PLL
RCC_I2SCLKSOURCE_SYSCLK
FDCAN Clock Source
RCC_FDCANCLKSOURCE_PCLK1
RCC_FDCANCLKSOURCE_PLL
RNG Clock Source
RCC_RNGCLKSOURCE_PLL
USB Clock Source
RCC_USBCLKSOURCE_PLL
ADC12 Clock Source
RCC_ADC12CLKSOURCE_PLL
RCC_ADC12CLKSOURCE_SYSCLK
ADC345 Clock Source
RCC_ADC345CLKSOURCE_PLL
RCC_ADC345CLKSOURCE_SYSCLK
I2C4 Clock Source
RCC_I2C4CLKSOURCE_PCLK1
RCC_I2C4CLKSOURCE_SYSCLK
QuadSPI Clock Source
RCC_QSPICLKSOURCE_PLL
RCC_QSPICLKSOURCE_SYSCLK
RCC LSE CSS external interrupt line
RCCEx CRS Status
RCC_CRS_SYNCERR
RCC_CRS_SYNCMISS
RCC_CRS_SYNCOK
RCC_CRS_SYNCWARN
RCC_CRS_TIMEOUT
RCC_CRS_TRIMOVF
RCCEx CRS SynchroSource
RCC_CRS_SYNC_SOURCE_LSE
RCC_CRS_SYNC_SOURCE_USB
RCCEx CRS SynchroDivider
RCC_CRS_SYNC_DIV128
RCC_CRS_SYNC_DIV16
RCC_CRS_SYNC_DIV2
RCC_CRS_SYNC_DIV32
RCC_CRS_SYNC_DIV4
RCC_CRS_SYNC_DIV64
RCC_CRS_SYNC_DIV8
RCCEx CRS SynchroPolarity
RCC_CRS_SYNC_POLARITY_RISING
RCCEx CRS ReloadValueDefault
RCCEx CRS ErrorLimitDefault
RCCEx CRS HSI48CalibrationDefault
RCCEx CRS FreqErrorDirection
RCC_CRS_FREQERRORDIR_UP
RCCEx CRS Interrupt Sources
RCC_CRS_IT_ESYNC
RCC_CRS_IT_SYNCERR
RCC_CRS_IT_SYNCMISS
RCC_CRS_IT_SYNCOK
RCC_CRS_IT_SYNCWARN
RCC_CRS_IT_TRIMOVF
RCCEx CRS Flags
RCC_CRS_FLAG_ESYNC
RCC_CRS_FLAG_SYNCERR
RCC_CRS_FLAG_SYNCMISS
RCC_CRS_FLAG_SYNCOK
RCC_CRS_FLAG_SYNCWARN
RCC_CRS_FLAG_TRIMOVF
RCCEx Exported Macros
__HAL_RCC_CRS_CLEAR_IT
__HAL_RCC_CRS_DISABLE_IT
__HAL_RCC_CRS_ENABLE_IT
__HAL_RCC_CRS_GET_FLAG
__HAL_RCC_CRS_GET_IT_SOURCE
__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG
__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_DISABLE_IT
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_IT
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT
__HAL_RCC_LSECSS_EXTI_GET_FLAG
RCC_CRS_FLAG_ERROR_MASK
RCC_CRS_IT_ERROR_MASK
RCCEx CRS Extended Features
__HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
__HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
__HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
__HAL_RCC_CRS_RELOADVALUE_CALCULATE
Defines
__HAL_RCC_ADC345_CONFIG
__HAL_RCC_FDCAN_CONFIG
__HAL_RCC_GET_ADC12_SOURCE
__HAL_RCC_GET_ADC345_SOURCE
__HAL_RCC_GET_FDCAN_SOURCE
__HAL_RCC_GET_I2C1_SOURCE
__HAL_RCC_GET_I2C2_SOURCE
__HAL_RCC_GET_I2C3_SOURCE
__HAL_RCC_GET_I2C4_SOURCE
__HAL_RCC_GET_I2S_SOURCE
__HAL_RCC_GET_LPTIM1_SOURCE
__HAL_RCC_GET_LPUART1_SOURCE
__HAL_RCC_GET_QSPI_SOURCE
__HAL_RCC_GET_RNG_SOURCE
__HAL_RCC_GET_SAI1_SOURCE
__HAL_RCC_GET_UART4_SOURCE
__HAL_RCC_GET_UART5_SOURCE
__HAL_RCC_GET_USART1_SOURCE
__HAL_RCC_GET_USART2_SOURCE
__HAL_RCC_GET_USART3_SOURCE
__HAL_RCC_GET_USB_SOURCE
__HAL_RCC_I2C1_CONFIG
__HAL_RCC_I2C2_CONFIG
__HAL_RCC_I2C3_CONFIG
__HAL_RCC_I2C4_CONFIG
__HAL_RCC_I2S_CONFIG
__HAL_RCC_LPTIM1_CONFIG
__HAL_RCC_LPUART1_CONFIG
__HAL_RCC_QSPI_CONFIG
__HAL_RCC_RNG_CONFIG
__HAL_RCC_SAI1_CONFIG
__HAL_RCC_UART4_CONFIG
__HAL_RCC_UART5_CONFIG
__HAL_RCC_USART1_CONFIG
__HAL_RCC_USART2_CONFIG
__HAL_RCC_USART3_CONFIG
__HAL_RCC_USB_CONFIG
RCCEx_Private_Macros
IS_RCC_ADC345CLKSOURCE
IS_RCC_CRS_ERRORLIMIT
IS_RCC_CRS_FREQERRORDIR
IS_RCC_CRS_HSI48CALIBRATION
IS_RCC_CRS_RELOADVALUE
IS_RCC_CRS_SYNC_DIV
IS_RCC_CRS_SYNC_POLARITY
IS_RCC_CRS_SYNC_SOURCE
IS_RCC_FDCANCLKSOURCE
IS_RCC_I2C1CLKSOURCE
IS_RCC_I2C2CLKSOURCE
IS_RCC_I2C3CLKSOURCE
IS_RCC_I2C4CLKSOURCE
IS_RCC_I2SCLKSOURCE
IS_RCC_LPTIM1CLKSOURCE
IS_RCC_LPUART1CLKSOURCE
IS_RCC_LSCOSOURCE
IS_RCC_PERIPHCLOCK
IS_RCC_QSPICLKSOURCE
IS_RCC_RNGCLKSOURCE
IS_RCC_SAI1CLKSOURCE
IS_RCC_UART4CLKSOURCE
IS_RCC_UART5CLKSOURCE
IS_RCC_USART1CLKSOURCE
IS_RCC_USART2CLKSOURCE
IS_RCC_USART3CLKSOURCE
IS_RCC_USBCLKSOURCE
RNG
RNG Exported Types
RNG State Structure definition
RNG Handle Structure definition
pRNG_ReadyDataCallbackTypeDef
RNG_HandleTypeDef
Enumerations
Data Structures
RNG Exported Constants
RNG_IT_DRDY
RNG_IT_SEI
RNG Flag definition
RNG_FLAG_DRDY
RNG_FLAG_SECS
RNG Clock Error Detection
RNG_CED_ENABLE
RNG Error Definition
HAL_RNG_ERROR_CLOCK
HAL_RNG_ERROR_INVALID_CALLBACK
HAL_RNG_ERROR_NONE
HAL_RNG_ERROR_SEED
HAL_RNG_ERROR_TIMEOUT
RNG Exported Macros
__HAL_RNG_CLEAR_IT
__HAL_RNG_DISABLE
__HAL_RNG_DISABLE_IT
__HAL_RNG_ENABLE
__HAL_RNG_ENABLE_IT
__HAL_RNG_GET_FLAG
__HAL_RNG_GET_IT
__HAL_RNG_RESET_HANDLE_STATE
RNG Exported Functions
HAL_RNG_Init
HAL_RNG_MspDeInit
HAL_RNG_MspInit
HAL_RNG_RegisterCallback
HAL_RNG_RegisterReadyDataCallback
HAL_RNG_UnRegisterCallback
HAL_RNG_UnRegisterReadyDataCallback
Peripheral Control functions
HAL_RNG_GenerateRandomNumber
HAL_RNG_GenerateRandomNumber_IT
HAL_RNG_IRQHandler
HAL_RNG_ReadLastRandomNumber
HAL_RNG_ReadyDataCallback
Peripheral State functions
HAL_RNG_GetState
RNG Private Macros
IS_RNG_FLAG
IS_RNG_IT
RTC
RTC_HandleTypeDef
Enumerations
HAL_RTCStateTypeDef
Data Structures
RTC_TimeTypeDef
RTC_DateTypeDef
RTC_AlarmTypeDef
__RTC_HandleTypeDef
RTC Exported Constants
RTC_HOURFORMAT_24
RTCEx Output Selection Definition
RTC_OUTPUT_ALARMB
RTC_OUTPUT_DISABLE
RTC_OUTPUT_TAMPER
RTC_OUTPUT_WAKEUP
RTC Output Polarity Definitions
RTC_OUTPUT_POLARITY_LOW
RTC Output Type ALARM OUT
RTC_OUTPUT_TYPE_PUSHPULL
RTC Output Pull-Up ALARM OUT
RTC_OUTPUT_PULLUP_ON
RTC Output ALARM OUT Remap
RTC_OUTPUT_REMAP_POS1
RTC AM PM Definitions
RTC_HOURFORMAT12_PM
RTC DayLightSaving Definitions
RTC_DAYLIGHTSAVING_NONE
RTC_DAYLIGHTSAVING_SUB1H
RTC StoreOperation Definitions
RTC_STOREOPERATION_SET
RTC Input Parameter Format Definitions
RTC_FORMAT_BIN
RTC Month Date Definitions
RTC_MONTH_AUGUST
RTC_MONTH_DECEMBER
RTC_MONTH_FEBRUARY
RTC_MONTH_JANUARY
RTC_MONTH_JULY
RTC_MONTH_JUNE
RTC_MONTH_MARCH
RTC_MONTH_MAY
RTC_MONTH_NOVEMBER
RTC_MONTH_OCTOBER
RTC_MONTH_SEPTEMBER
RTC WeekDay Definitions
RTC_WEEKDAY_MONDAY
RTC_WEEKDAY_SATURDAY
RTC_WEEKDAY_SUNDAY
RTC_WEEKDAY_THURSDAY
RTC_WEEKDAY_TUESDAY
RTC_WEEKDAY_WEDNESDAY
RTC AlarmDateWeekDay Definitions
RTC_ALARMDATEWEEKDAYSEL_WEEKDAY
RTC AlarmMask Definitions
RTC_ALARMMASK_DATEWEEKDAY
RTC_ALARMMASK_HOURS
RTC_ALARMMASK_MINUTES
RTC_ALARMMASK_NONE
RTC_ALARMMASK_SECONDS
RTC Alarms Definitions
RTC_ALARM_B
RTC Alarm Sub Seconds Masks Definitions
RTC_ALARMSUBSECONDMASK_NONE
RTC_ALARMSUBSECONDMASK_SS14
RTC_ALARMSUBSECONDMASK_SS14_1
RTC_ALARMSUBSECONDMASK_SS14_10
RTC_ALARMSUBSECONDMASK_SS14_11
RTC_ALARMSUBSECONDMASK_SS14_12
RTC_ALARMSUBSECONDMASK_SS14_13
RTC_ALARMSUBSECONDMASK_SS14_2
RTC_ALARMSUBSECONDMASK_SS14_3
RTC_ALARMSUBSECONDMASK_SS14_4
RTC_ALARMSUBSECONDMASK_SS14_5
RTC_ALARMSUBSECONDMASK_SS14_6
RTC_ALARMSUBSECONDMASK_SS14_7
RTC_ALARMSUBSECONDMASK_SS14_8
RTC_ALARMSUBSECONDMASK_SS14_9
RTC Interrupts Definitions
RTC_IT_ALRB
RTC_IT_TS
RTC_IT_WUT
RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
RTC Flags Definitions
RTC_FLAG_ALRAWF
RTC_FLAG_ALRBF
RTC_FLAG_ALRBWF
RTC_FLAG_INITF
RTC_FLAG_INITS
RTC_FLAG_ITSF
RTC_FLAG_RECALPF
RTC_FLAG_RSF
RTC_FLAG_SHPF
RTC_FLAG_TSF
RTC_FLAG_TSOVF
RTC_FLAG_WUTF
RTC_FLAG_WUTWF
RTC Clear Flags Definitions
RTC_CLEAR_ALRBF
RTC_CLEAR_ITSF
RTC_CLEAR_TSF
RTC_CLEAR_TSOVF
RTC_CLEAR_WUTF
RTC Exported Macros
__HAL_RTC_ALARM_DISABLE_IT
__HAL_RTC_ALARM_ENABLE_IT
__HAL_RTC_ALARM_EXTI_CLEAR_IT
__HAL_RTC_ALARM_EXTI_DISABLE_EVENT
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_DISABLE_IT
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_EVENT
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_IT
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_FALLING_IT
__HAL_RTC_ALARM_EXTI_RISING_IT
__HAL_RTC_ALARM_GET_FLAG
__HAL_RTC_ALARM_GET_IT
__HAL_RTC_ALARM_GET_IT_SOURCE
__HAL_RTC_ALARMA_DISABLE
__HAL_RTC_ALARMA_ENABLE
__HAL_RTC_ALARMB_DISABLE
__HAL_RTC_ALARMB_ENABLE
__HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H
__HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H
__HAL_RTC_IS_CALENDAR_INITIALIZED
__HAL_RTC_RESET_HANDLE_STATE
__HAL_RTC_WRITEPROTECTION_DISABLE
__HAL_RTC_WRITEPROTECTION_ENABLE
RTC Exported Functions
HAL_RTC_Init
HAL_RTC_MspDeInit
HAL_RTC_MspInit
HAL_RTC_RegisterCallback
HAL_RTC_UnRegisterCallback
RTC Time and Date functions
HAL_RTC_DST_ClearStoreOperation
HAL_RTC_DST_ReadStoreOperation
HAL_RTC_DST_SetStoreOperation
HAL_RTC_DST_Sub1Hour
HAL_RTC_GetDate
HAL_RTC_GetTime
HAL_RTC_SetDate
HAL_RTC_SetTime
RTC Alarm functions
HAL_RTC_AlarmIRQHandler
HAL_RTC_DeactivateAlarm
HAL_RTC_GetAlarm
HAL_RTC_PollForAlarmAEvent
HAL_RTC_SetAlarm
HAL_RTC_SetAlarm_IT
Peripheral Control functions
Peripheral State functions
RTC Private Constants
RTC_ICSR_RESERVED_MASK
RTC_INIT_MASK
RTC_RSF_MASK
RTC_TIMEOUT_VALUE
RTC_TR_RESERVED_MASK
RTC Private Macros
IS_RTC_ALARM_DATE_WEEKDAY_DATE
IS_RTC_ALARM_DATE_WEEKDAY_SEL
IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY
IS_RTC_ALARM_MASK
IS_RTC_ALARM_SUB_SECOND_MASK
IS_RTC_ALARM_SUB_SECOND_VALUE
IS_RTC_ASYNCH_PREDIV
IS_RTC_DATE
IS_RTC_DAYLIGHT_SAVING
IS_RTC_FORMAT
IS_RTC_HOUR12
IS_RTC_HOUR24
IS_RTC_HOUR_FORMAT
IS_RTC_HOURFORMAT12
IS_RTC_MINUTES
IS_RTC_MONTH
IS_RTC_OUTPUT
IS_RTC_OUTPUT_POL
IS_RTC_OUTPUT_PULLUP
IS_RTC_OUTPUT_REMAP
IS_RTC_OUTPUT_TYPE
IS_RTC_SECONDS
IS_RTC_STORE_OPERATION
IS_RTC_SYNCH_PREDIV
IS_RTC_WEEKDAY
IS_RTC_YEAR
RTC Private Functions
HAL_RTC_DST_ClearStoreOperation
HAL_RTC_DST_ReadStoreOperation
HAL_RTC_DST_SetStoreOperation
HAL_RTC_DST_Sub1Hour
RTC_Bcd2ToByte
RTC_ByteToBcd2
RTC_EnterInitMode
RTC_ExitInitMode
RTCEx
RTCEx Internal Tamper structure definition
RTCEx Exported Constants
RTC_TIMESTAMPEDGE_RISING
RTCEx TimeStamp Pin Selection
RTCEx Wakeup Timer Definitions
RTC_WAKEUPCLOCK_CK_SPRE_17BITS
RTC_WAKEUPCLOCK_RTCCLK_DIV16
RTC_WAKEUPCLOCK_RTCCLK_DIV2
RTC_WAKEUPCLOCK_RTCCLK_DIV4
RTC_WAKEUPCLOCK_RTCCLK_DIV8
RTCEx Smooth calib period Definitions
RTC_SMOOTHCALIB_PERIOD_32SEC
RTC_SMOOTHCALIB_PERIOD_8SEC
RTCEx Smooth calib Plus pulses Definitions
RTC_SMOOTHCALIB_PLUSPULSES_SET
RTCEx Calib Output selection Definitions
RTC_CALIBOUTPUT_512HZ
RTCEx Add 1 Second Parameter Definitions
RTC_SHIFTADD1S_SET
RTCEx Tamper Pins Definition
RTC_TAMPER_2
RTC_TAMPER_3
RTC_TAMPER_ALL
RTCEx Internal Tamper Pins Definition
RTC_INT_TAMPER_2
RTC_INT_TAMPER_3
RTC_INT_TAMPER_4
RTC_INT_TAMPER_5
RTC_INT_TAMPER_6
RTC_INT_TAMPER_7
RTC_INT_TAMPER_8
RTC_INT_TAMPER_ALL
RTCEx Tamper Trigger
RTC_TAMPERTRIGGER_HIGHLEVEL
RTC_TAMPERTRIGGER_LOWLEVEL
RTC_TAMPERTRIGGER_RISINGEDGE
RTCEx Tamper MaskFlag
RTC_TAMPERMASK_FLAG_ENABLE
RTCEx Tamper EraseBackUp
RTC_TAMPER_ERASE_BACKUP_ENABLE
RTCEx Tamper Filter
RTC_TAMPERFILTER_4SAMPLE
RTC_TAMPERFILTER_8SAMPLE
RTC_TAMPERFILTER_DISABLE
RTCEx Tamper Sampling Frequencies
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192
RTCEx Tamper Pin Precharge Duration
RTC_TAMPERPRECHARGEDURATION_2RTCCLK
RTC_TAMPERPRECHARGEDURATION_4RTCCLK
RTC_TAMPERPRECHARGEDURATION_8RTCCLK
RTCEx Tamper Pull UP
RTC_TAMPER_PULLUP_ENABLE
RTCEx Tamper TimeStamp On Tamper Detection
RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
RTCEx Internal Tamper Interrupt
RTC_IT_INT_TAMP_2
RTC_IT_INT_TAMP_3
RTC_IT_INT_TAMP_4
RTC_IT_INT_TAMP_5
RTC_IT_INT_TAMP_6
RTC_IT_INT_TAMP_7
RTC_IT_INT_TAMP_8
RTC_IT_INT_TAMP_ALL
RTC_IT_TAMP_1
RTC_IT_TAMP_2
RTC_IT_TAMP_3
RTC_IT_TAMP_ALL
RTCEx Flags
RTC_FLAG_INT_TAMP_2
RTC_FLAG_INT_TAMP_3
RTC_FLAG_INT_TAMP_4
RTC_FLAG_INT_TAMP_5
RTC_FLAG_INT_TAMP_6
RTC_FLAG_INT_TAMP_7
RTC_FLAG_INT_TAMP_8
RTC_FLAG_INT_TAMP_ALL
RTC_FLAG_TAMP_1
RTC_FLAG_TAMP_2
RTC_FLAG_TAMP_3
RTC_FLAG_TAMP_ALL
RTCEx Backup Registers Definition
RTC_BKP_DR1
RTC_BKP_DR10
RTC_BKP_DR11
RTC_BKP_DR12
RTC_BKP_DR13
RTC_BKP_DR14
RTC_BKP_DR15
RTC_BKP_DR16
RTC_BKP_DR17
RTC_BKP_DR18
RTC_BKP_DR19
RTC_BKP_DR2
RTC_BKP_DR20
RTC_BKP_DR21
RTC_BKP_DR22
RTC_BKP_DR23
RTC_BKP_DR24
RTC_BKP_DR25
RTC_BKP_DR26
RTC_BKP_DR27
RTC_BKP_DR28
RTC_BKP_DR29
RTC_BKP_DR3
RTC_BKP_DR30
RTC_BKP_DR31
RTC_BKP_DR4
RTC_BKP_DR5
RTC_BKP_DR6
RTC_BKP_DR7
RTC_BKP_DR8
RTC_BKP_DR9
RTC_BKP_NUMBER
RTCEx Exported Macros
__HAL_RTC_WAKEUPTIMER_DISABLE
__HAL_RTC_WAKEUPTIMER_DISABLE_IT
__HAL_RTC_WAKEUPTIMER_ENABLE
__HAL_RTC_WAKEUPTIMER_ENABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT
__HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT
__HAL_RTC_WAKEUPTIMER_GET_FLAG
__HAL_RTC_WAKEUPTIMER_GET_IT
__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE
RTC Timestamp
__HAL_RTC_INTERNAL_TIMESTAMP_DISABLE
__HAL_RTC_INTERNAL_TIMESTAMP_ENABLE
__HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG
__HAL_RTC_TAMPOE_DISABLE
__HAL_RTC_TAMPOE_ENABLE
__HAL_RTC_TAMPTS_DISABLE
__HAL_RTC_TAMPTS_ENABLE
__HAL_RTC_TIMESTAMP_CLEAR_FLAG
__HAL_RTC_TIMESTAMP_DISABLE
__HAL_RTC_TIMESTAMP_DISABLE_IT
__HAL_RTC_TIMESTAMP_ENABLE
__HAL_RTC_TIMESTAMP_ENABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG
__HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT
__HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT
__HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_FALLING_IT
__HAL_RTC_TIMESTAMP_EXTI_RISING_IT
__HAL_RTC_TIMESTAMP_GET_FLAG
__HAL_RTC_TIMESTAMP_GET_IT
__HAL_RTC_TIMESTAMP_GET_IT_SOURCE
RTC Calibration
__HAL_RTC_CALIBRATION_OUTPUT_ENABLE
__HAL_RTC_CLOCKREF_DETECTION_DISABLE
__HAL_RTC_CLOCKREF_DETECTION_ENABLE
__HAL_RTC_SHIFT_GET_FLAG
RTCEx tamper
__HAL_RTC_TAMPER_DISABLE
__HAL_RTC_TAMPER_DISABLE_IT
__HAL_RTC_TAMPER_ENABLE
__HAL_RTC_TAMPER_ENABLE_IT
__HAL_RTC_TAMPER_EXTI_CLEAR_IT
__HAL_RTC_TAMPER_EXTI_DISABLE_EVENT
__HAL_RTC_TAMPER_EXTI_DISABLE_IT
__HAL_RTC_TAMPER_EXTI_ENABLE_EVENT
__HAL_RTC_TAMPER_EXTI_ENABLE_IT
__HAL_RTC_TAMPER_EXTI_FALLING_IT
__HAL_RTC_TAMPER_EXTI_RISING_IT
__HAL_RTC_TAMPER_GET_FLAG
__HAL_RTC_TAMPER_GET_IT
__HAL_RTC_TAMPER_GET_IT_SOURCE
Defines
__HAL_RTC_GET_FLAG
RTCEx Exported Functions
HAL_RTCEx_DeactivateTimeStamp
HAL_RTCEx_GetTimeStamp
HAL_RTCEx_PollForTimeStampEvent
HAL_RTCEx_SetInternalTimeStamp
HAL_RTCEx_SetTimeStamp
HAL_RTCEx_SetTimeStamp_IT
HAL_RTCEx_TimeStampEventCallback
HAL_RTCEx_TimeStampIRQHandler
Extended RTC Wake-up functions
HAL_RTCEx_GetWakeUpTimer
HAL_RTCEx_PollForWakeUpTimerEvent
HAL_RTCEx_SetWakeUpTimer
HAL_RTCEx_SetWakeUpTimer_IT
HAL_RTCEx_WakeUpTimerEventCallback
HAL_RTCEx_WakeUpTimerIRQHandler
Extended Peripheral Control functions
HAL_RTCEx_DeactivateRefClock
HAL_RTCEx_DisableBypassShadow
HAL_RTCEx_EnableBypassShadow
HAL_RTCEx_SetCalibrationOutPut
HAL_RTCEx_SetRefClock
HAL_RTCEx_SetSmoothCalib
HAL_RTCEx_SetSynchroShift
Extended features functions
HAL_RTCEx_PollForAlarmBEvent
Extended RTC Tamper functions
HAL_RTCEx_DeactivateTamper
HAL_RTCEx_InternalTamper3EventCallback
HAL_RTCEx_InternalTamper4EventCallback
HAL_RTCEx_InternalTamper5EventCallback
HAL_RTCEx_InternalTamper6EventCallback
HAL_RTCEx_PollForInternalTamperEvent
HAL_RTCEx_PollForTamperEvent
HAL_RTCEx_SetInternalTamper
HAL_RTCEx_SetInternalTamper_IT
HAL_RTCEx_SetTamper
HAL_RTCEx_SetTamper_IT
HAL_RTCEx_Tamper1EventCallback
HAL_RTCEx_Tamper2EventCallback
HAL_RTCEx_Tamper3EventCallback
HAL_RTCEx_TamperIRQHandler
Extended RTC Backup register functions
HAL_RTCEx_BKUPWrite
RTCEx Private Constants
RTC_EXTI_LINE_TAMPER_EVENT
RTC_EXTI_LINE_TIMESTAMP_EVENT
RTC_EXTI_LINE_WAKEUPTIMER_EVENT
RTCEx Private Macros
IS_RTC_CALIB_OUTPUT
IS_RTC_INTERNAL_TAMPER
IS_RTC_LOW_POWER_CALIB
IS_RTC_SHIFT_ADD1S
IS_RTC_SHIFT_SUBFS
IS_RTC_SMOOTH_CALIB_MINUS
IS_RTC_SMOOTH_CALIB_PERIOD
IS_RTC_SMOOTH_CALIB_PLUS
IS_RTC_TAMPER
IS_RTC_TAMPER_ERASE_MODE
IS_RTC_TAMPER_FILTER
IS_RTC_TAMPER_MASKFLAG_STATE
IS_RTC_TAMPER_PRECHARGE_DURATION
IS_RTC_TAMPER_PULLUP_STATE
IS_RTC_TAMPER_SAMPLING_FREQ
IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT
IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
IS_RTC_TAMPER_TRIGGER
IS_RTC_TIMESTAMP_PIN
IS_RTC_TIMESTAMPONTAMPER_DETECTION
IS_RTC_WAKEUP_CLOCK
IS_RTC_WAKEUP_COUNTER
IS_TIMESTAMP_EDGE
SAI
SAI Private Constants
SAI_DEFAULT_TIMEOUT
SAI_LONG_TIMEOUT
SAI_SPDIF_FRAME_LENGTH
SAI Private Functions
SAI_DMAAbort
SAI_DMAError
SAI_DMARxCplt
SAI_DMARxHalfCplt
SAI_DMATxCplt
SAI_DMATxHalfCplt
SAI_FillFifo
SAI_InitI2S
SAI_InitPCM
SAI_InterruptFlag
SAI_Receive_IT16Bit
SAI_Receive_IT32Bit
SAI_Receive_IT8Bit
SAI_Transmit_IT16Bit
SAI_Transmit_IT32Bit
SAI_Transmit_IT8Bit
SAI Exported Functions
HAL_SAI_Init
HAL_SAI_InitProtocol
HAL_SAI_MspDeInit
HAL_SAI_MspInit
HAL_SAI_RegisterCallback
HAL_SAI_UnRegisterCallback
IO operation functions
HAL_SAI_DisableRxMuteMode
HAL_SAI_DisableTxMuteMode
HAL_SAI_DMAPause
HAL_SAI_DMAResume
HAL_SAI_DMAStop
HAL_SAI_EnableRxMuteMode
HAL_SAI_EnableTxMuteMode
HAL_SAI_ErrorCallback
HAL_SAI_IRQHandler
HAL_SAI_Receive
HAL_SAI_Receive_DMA
HAL_SAI_Receive_IT
HAL_SAI_RxCpltCallback
HAL_SAI_RxHalfCpltCallback
HAL_SAI_Transmit
HAL_SAI_Transmit_DMA
HAL_SAI_Transmit_IT
HAL_SAI_TxCpltCallback
HAL_SAI_TxHalfCpltCallback
Peripheral State functions
HAL_SAI_GetState
SAI Exported Types
SAI Init Structure definition
SAI Frame Structure definition
SAI Slot Structure definition
SAI Handle Structure definition
Data Structures
Typedefs
SAIcallback
Enumerations
HAL_SAI_StateTypeDef
SAI Exported Constants
HAL_SAI_ERROR_CNREADY
HAL_SAI_ERROR_DMA
HAL_SAI_ERROR_INVALID_CALLBACK
HAL_SAI_ERROR_LFSDET
HAL_SAI_ERROR_NONE
HAL_SAI_ERROR_OVR
HAL_SAI_ERROR_TIMEOUT
HAL_SAI_ERROR_UDR
HAL_SAI_ERROR_WCKCFG
SAI External synchronisation
SAI Block Master Clock Output
SAI_MCK_OUTPUT_ENABLE
SAI Supported protocol
SAI_I2S_MSBJUSTIFIED
SAI_I2S_STANDARD
SAI_PCM_LONG
SAI_PCM_SHORT
SAI protocol data size
SAI_PROTOCOL_DATASIZE_16BITEXTENDED
SAI_PROTOCOL_DATASIZE_24BIT
SAI_PROTOCOL_DATASIZE_32BIT
SAI Audio Frequency
SAI_AUDIO_FREQUENCY_16K
SAI_AUDIO_FREQUENCY_192K
SAI_AUDIO_FREQUENCY_22K
SAI_AUDIO_FREQUENCY_32K
SAI_AUDIO_FREQUENCY_44K
SAI_AUDIO_FREQUENCY_48K
SAI_AUDIO_FREQUENCY_8K
SAI_AUDIO_FREQUENCY_96K
SAI_AUDIO_FREQUENCY_MCKDIV
SAI Block Master Clock OverSampling
SAI_MCK_OVERSAMPLING_ENABLE
SAI PDM Clock Enable
SAI_PDM_CLOCK2_ENABLE
SAI Block Mode
SAI_MODEMASTER_TX
SAI_MODESLAVE_RX
SAI_MODESLAVE_TX
SAI Block Protocol
SAI_FREE_PROTOCOL
SAI_SPDIF_PROTOCOL
SAI Block Data Size
SAI_DATASIZE_16
SAI_DATASIZE_20
SAI_DATASIZE_24
SAI_DATASIZE_32
SAI_DATASIZE_8
SAI Block MSB LSB transmission
SAI_FIRSTBIT_MSB
SAI Block Clock Strobing
SAI_CLOCKSTROBING_RISINGEDGE
SAI Block Synchronization
SAI_SYNCHRONOUS
SAI Block Output Drive
SAI_OUTPUTDRIVE_ENABLE
SAI Block NoDivider
SAI_MASTERDIVIDER_ENABLE
SAI Block FS Definition
SAI_FS_STARTFRAME
SAI Block FS Polarity
SAI_FS_ACTIVE_LOW
SAI Block FS Offset
SAI_FS_FIRSTBIT
SAI Block Slot Size
SAI_SLOTSIZE_32B
SAI_SLOTSIZE_DATASIZE
SAI Block Slot Active
SAI_SLOTACTIVE_0
SAI_SLOTACTIVE_1
SAI_SLOTACTIVE_10
SAI_SLOTACTIVE_11
SAI_SLOTACTIVE_12
SAI_SLOTACTIVE_13
SAI_SLOTACTIVE_14
SAI_SLOTACTIVE_15
SAI_SLOTACTIVE_2
SAI_SLOTACTIVE_3
SAI_SLOTACTIVE_4
SAI_SLOTACTIVE_5
SAI_SLOTACTIVE_6
SAI_SLOTACTIVE_7
SAI_SLOTACTIVE_8
SAI_SLOTACTIVE_9
SAI_SLOTACTIVE_ALL
SAI Mono Stereo Mode
SAI_STEREOMODE
SAI TRIState Management
SAI_OUTPUT_RELEASED
SAI Block Fifo Threshold
SAI_FIFOTHRESHOLD_3QF
SAI_FIFOTHRESHOLD_EMPTY
SAI_FIFOTHRESHOLD_FULL
SAI_FIFOTHRESHOLD_HF
SAI Block Companding Mode
SAI_ALAW_2CPL_COMPANDING
SAI_NOCOMPANDING
SAI_ULAW_1CPL_COMPANDING
SAI_ULAW_2CPL_COMPANDING
SAI Block Mute Value
SAI_ZERO_VALUE
SAI Block Interrupts Definition
SAI_IT_CNRDY
SAI_IT_FREQ
SAI_IT_LFSDET
SAI_IT_MUTEDET
SAI_IT_OVRUDR
SAI_IT_WCKCFG
SAI Block Flags Definition
SAI_FLAG_CNRDY
SAI_FLAG_FREQ
SAI_FLAG_LFSDET
SAI_FLAG_MUTEDET
SAI_FLAG_OVRUDR
SAI_FLAG_WCKCFG
SAI Block Fifo Status Level
SAI_FIFOSTATUS_3QUARTERFULL
SAI_FIFOSTATUS_EMPTY
SAI_FIFOSTATUS_FULL
SAI_FIFOSTATUS_HALFFULL
SAI_FIFOSTATUS_LESS1QUARTERFULL
SAI Exported Macros
__HAL_SAI_DISABLE
__HAL_SAI_DISABLE_IT
__HAL_SAI_ENABLE
__HAL_SAI_ENABLE_IT
__HAL_SAI_GET_FLAG
__HAL_SAI_GET_IT_SOURCE
__HAL_SAI_RESET_HANDLE_STATE
SAI Private Macros
IS_SAI_BLOCK_ACTIVE_FRAME
IS_SAI_BLOCK_CLOCK_STROBING
IS_SAI_BLOCK_COMPANDING_MODE
IS_SAI_BLOCK_DATASIZE
IS_SAI_BLOCK_FIFO_THRESHOLD
IS_SAI_BLOCK_FIRST_BIT
IS_SAI_BLOCK_FIRSTBIT_OFFSET
IS_SAI_BLOCK_FRAME_LENGTH
IS_SAI_BLOCK_FS_DEFINITION
IS_SAI_BLOCK_FS_OFFSET
IS_SAI_BLOCK_FS_POLARITY
IS_SAI_BLOCK_MASTER_DIVIDER
IS_SAI_BLOCK_MCK_OUTPUT
IS_SAI_BLOCK_MCK_OVERSAMPLING
IS_SAI_BLOCK_MODE
IS_SAI_BLOCK_MUTE_COUNTER
IS_SAI_BLOCK_MUTE_VALUE
IS_SAI_BLOCK_NODIVIDER
IS_SAI_BLOCK_OUTPUT_DRIVE
IS_SAI_BLOCK_PROTOCOL
IS_SAI_BLOCK_SLOT_NUMBER
IS_SAI_BLOCK_SLOT_SIZE
IS_SAI_BLOCK_SYNCEXT
IS_SAI_BLOCK_SYNCHRO
IS_SAI_BLOCK_TRISTATE_MANAGEMENT
IS_SAI_MONO_STEREO_MODE
IS_SAI_PDM_CLOCK_ENABLE
IS_SAI_PDM_MIC_PAIRS_NUMBER
IS_SAI_PROTOCOL_DATASIZE
IS_SAI_SLOT_ACTIVE
IS_SAI_SUPPORTED_PROTOCOL
SAIEx
SAI_PDM_DELAY_OFFSET
SAI_PDM_RIGHT_DELAY_OFFSET
SAIEx Extended Exported Functions
SAIEx Exported Types
SAIEx Extended Private Macros
SMARTCARD
USART_BRR_MAX
USART_BRR_MIN
USART_CR1_FIELDS
USART_CR2_CLK_FIELDS
USART_CR2_FIELDS
USART_CR3_FIELDS
SMARTCARD Exported Functions
HAL_SMARTCARD_Init
HAL_SMARTCARD_MspDeInit
HAL_SMARTCARD_MspInit
HAL_SMARTCARD_RegisterCallback
HAL_SMARTCARD_UnRegisterCallback
IO operation functions
HAL_SMARTCARD_Abort_IT
HAL_SMARTCARD_AbortCpltCallback
HAL_SMARTCARD_AbortReceive
HAL_SMARTCARD_AbortReceive_IT
HAL_SMARTCARD_AbortReceiveCpltCallback
HAL_SMARTCARD_AbortTransmit
HAL_SMARTCARD_AbortTransmit_IT
HAL_SMARTCARD_AbortTransmitCpltCallback
HAL_SMARTCARD_ErrorCallback
HAL_SMARTCARD_IRQHandler
HAL_SMARTCARD_Receive
HAL_SMARTCARD_Receive_DMA
HAL_SMARTCARD_Receive_IT
HAL_SMARTCARD_RxCpltCallback
HAL_SMARTCARD_Transmit
HAL_SMARTCARD_Transmit_DMA
HAL_SMARTCARD_Transmit_IT
HAL_SMARTCARD_TxCpltCallback
Peripheral State and Errors functions
HAL_SMARTCARD_GetState
SMARTCARD Private Functions
SMARTCARD_CheckIdleState
SMARTCARD_DMAAbortOnError
SMARTCARD_DMAError
SMARTCARD_DMAReceiveCplt
SMARTCARD_DMARxAbortCallback
SMARTCARD_DMARxOnlyAbortCallback
SMARTCARD_DMATransmitCplt
SMARTCARD_DMATxAbortCallback
SMARTCARD_DMATxOnlyAbortCallback
SMARTCARD_EndRxTransfer
SMARTCARD_EndTransmit_IT
SMARTCARD_EndTxTransfer
SMARTCARD_InitCallbacksToDefault
SMARTCARD_RxISR
SMARTCARD_RxISR_FIFOEN
SMARTCARD_SetConfig
SMARTCARD_TxISR
SMARTCARD_TxISR_FIFOEN
SMARTCARD_WaitOnFlagUntilTimeout
SMARTCARD Exported Types
pSMARTCARD_CallbackTypeDef
SMARTCARD_HandleTypeDef
Enumerations
SMARTCARD_ClockSourceTypeDef
Data Structures
SMARTCARD_AdvFeatureInitTypeDef
__SMARTCARD_HandleTypeDef
SMARTCARD Exported Constants
HAL_SMARTCARD_STATE_BUSY_RX
HAL_SMARTCARD_STATE_BUSY_TX
HAL_SMARTCARD_STATE_BUSY_TX_RX
HAL_SMARTCARD_STATE_ERROR
HAL_SMARTCARD_STATE_READY
HAL_SMARTCARD_STATE_RESET
HAL_SMARTCARD_STATE_TIMEOUT
SMARTCARD Error Code Definition
HAL_SMARTCARD_ERROR_FE
HAL_SMARTCARD_ERROR_INVALID_CALLBACK
HAL_SMARTCARD_ERROR_NE
HAL_SMARTCARD_ERROR_NONE
HAL_SMARTCARD_ERROR_ORE
HAL_SMARTCARD_ERROR_PE
HAL_SMARTCARD_ERROR_RTO
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD_STOPBITS_1_5
SMARTCARD Parity
SMARTCARD_PARITY_ODD
SMARTCARD Transfer Mode
SMARTCARD_MODE_TX
SMARTCARD_MODE_TX_RX
SMARTCARD Clock Polarity
SMARTCARD_POLARITY_LOW
SMARTCARD Clock Phase
SMARTCARD_PHASE_2EDGE
SMARTCARD Last Bit
SMARTCARD_LASTBIT_ENABLE
SMARTCARD One Bit Sampling Method
SMARTCARD_ONE_BIT_SAMPLE_ENABLE
SMARTCARD NACK Enable
SMARTCARD_NACK_ENABLE
SMARTCARD Timeout Enable
SMARTCARD_TIMEOUT_ENABLE
SMARTCARD Clock Prescaler
SMARTCARD_PRESCALER_DIV10
SMARTCARD_PRESCALER_DIV12
SMARTCARD_PRESCALER_DIV128
SMARTCARD_PRESCALER_DIV16
SMARTCARD_PRESCALER_DIV2
SMARTCARD_PRESCALER_DIV256
SMARTCARD_PRESCALER_DIV32
SMARTCARD_PRESCALER_DIV4
SMARTCARD_PRESCALER_DIV6
SMARTCARD_PRESCALER_DIV64
SMARTCARD_PRESCALER_DIV8
SMARTCARD advanced feature TX pin active level inversion
SMARTCARD_ADVFEATURE_TXINV_ENABLE
SMARTCARD advanced feature RX pin active level inversion
SMARTCARD_ADVFEATURE_RXINV_ENABLE
SMARTCARD advanced feature Binary Data inversion
SMARTCARD_ADVFEATURE_DATAINV_ENABLE
SMARTCARD advanced feature RX TX pins swap
SMARTCARD_ADVFEATURE_SWAP_ENABLE
SMARTCARD advanced feature Overrun Disable
SMARTCARD_ADVFEATURE_OVERRUN_ENABLE
SMARTCARD advanced feature DMA Disable on Rx Error
SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR
SMARTCARD advanced feature MSB first
SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE
SMARTCARD Request Parameters
SMARTCARD_TXDATA_FLUSH_REQUEST
SMARTCARD interruptions flags mask
SMARTCARD_CR_POS
SMARTCARD_ISR_MASK
SMARTCARD_ISR_POS
SMARTCARD_IT_MASK
SMARTCARD Exported Macros
__HAL_SMARTCARD_CLEAR_FLAG
__HAL_SMARTCARD_CLEAR_IDLEFLAG
__HAL_SMARTCARD_CLEAR_IT
__HAL_SMARTCARD_CLEAR_NEFLAG
__HAL_SMARTCARD_CLEAR_OREFLAG
__HAL_SMARTCARD_CLEAR_PEFLAG
__HAL_SMARTCARD_DISABLE
__HAL_SMARTCARD_DISABLE_IT
__HAL_SMARTCARD_ENABLE
__HAL_SMARTCARD_ENABLE_IT
__HAL_SMARTCARD_FLUSH_DRREGISTER
__HAL_SMARTCARD_GET_FLAG
__HAL_SMARTCARD_GET_IT
__HAL_SMARTCARD_GET_IT_SOURCE
__HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE
__HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE
__HAL_SMARTCARD_RESET_HANDLE_STATE
__HAL_SMARTCARD_SEND_REQ
SMARTCARD Private Macros
IS_SMARTCARD_ADVFEATURE_DMAONRXERROR
IS_SMARTCARD_ADVFEATURE_INIT
IS_SMARTCARD_ADVFEATURE_MSBFIRST
IS_SMARTCARD_ADVFEATURE_RXINV
IS_SMARTCARD_ADVFEATURE_SWAP
IS_SMARTCARD_ADVFEATURE_TXINV
IS_SMARTCARD_AUTORETRY_COUNT
IS_SMARTCARD_BAUDRATE
IS_SMARTCARD_BLOCKLENGTH
IS_SMARTCARD_CLOCKPRESCALER
IS_SMARTCARD_LASTBIT
IS_SMARTCARD_MODE
IS_SMARTCARD_NACK
IS_SMARTCARD_ONE_BIT_SAMPLE
IS_SMARTCARD_OVERRUN
IS_SMARTCARD_PARITY
IS_SMARTCARD_PHASE
IS_SMARTCARD_POLARITY
IS_SMARTCARD_REQUEST_PARAMETER
IS_SMARTCARD_STOPBITS
IS_SMARTCARD_TIMEOUT
IS_SMARTCARD_TIMEOUT_VALUE
IS_SMARTCARD_WORD_LENGTH
SMARTCARD_GETCLOCKSOURCE
SMARTCARDEx
TX_FIFO_DEPTH
SMARTCARD Extended Exported Functions
HAL_SMARTCARDEx_DisableReceiverTimeOut
HAL_SMARTCARDEx_EnableReceiverTimeOut
HAL_SMARTCARDEx_TimeOut_Config
Extended Peripheral IO operation functions
HAL_SMARTCARDEx_TxFifoEmptyCallback
Extended Peripheral FIFO Control functions
HAL_SMARTCARDEx_EnableFifoMode
HAL_SMARTCARDEx_SetRxFifoThreshold
HAL_SMARTCARDEx_SetTxFifoThreshold
SMARTCARD Extended Private Functions
SMARTCARD Extended Private Macros
IS_SMARTCARD_RXFIFO_THRESHOLD
IS_SMARTCARD_TRANSMISSION_COMPLETION
IS_SMARTCARD_TXFIFO_THRESHOLD
SMARTCARD_TRANSMISSION_COMPLETION_FLAG
SMARTCARD_TRANSMISSION_COMPLETION_SETTING
SMARTCARD Extended Exported Constants
SMARTCARD_TCBGT
SMARTCARD advanced feature initialization type
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT
SMARTCARD_ADVFEATURE_MSBFIRST_INIT
SMARTCARD_ADVFEATURE_NO_INIT
SMARTCARD_ADVFEATURE_RXINVERT_INIT
SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT
SMARTCARD_ADVFEATURE_SWAP_INIT
SMARTCARD_ADVFEATURE_TXCOMPLETION
SMARTCARD_ADVFEATURE_TXINVERT_INIT
SMARTCARD FIFO mode
SMARTCARD_FIFOMODE_ENABLE
SMARTCARD TXFIFO threshold level
SMARTCARD_TXFIFO_THRESHOLD_1_4
SMARTCARD_TXFIFO_THRESHOLD_1_8
SMARTCARD_TXFIFO_THRESHOLD_3_4
SMARTCARD_TXFIFO_THRESHOLD_7_8
SMARTCARD_TXFIFO_THRESHOLD_8_8
SMARTCARD RXFIFO threshold level
SMARTCARD_RXFIFO_THRESHOLD_1_4
SMARTCARD_RXFIFO_THRESHOLD_1_8
SMARTCARD_RXFIFO_THRESHOLD_3_4
SMARTCARD_RXFIFO_THRESHOLD_7_8
SMARTCARD_RXFIFO_THRESHOLD_8_8
SMARTCARD Flags
SMARTCARD_FLAG_EOBF
SMARTCARD_FLAG_FE
SMARTCARD_FLAG_IDLE
SMARTCARD_FLAG_NE
SMARTCARD_FLAG_ORE
SMARTCARD_FLAG_PE
SMARTCARD_FLAG_REACK
SMARTCARD_FLAG_RTOF
SMARTCARD_FLAG_RXFF
SMARTCARD_FLAG_RXFNE
SMARTCARD_FLAG_RXFT
SMARTCARD_FLAG_RXNE
SMARTCARD_FLAG_TC
SMARTCARD_FLAG_TCBGT
SMARTCARD_FLAG_TEACK
SMARTCARD_FLAG_TXE
SMARTCARD_FLAG_TXFE
SMARTCARD_FLAG_TXFNF
SMARTCARD_FLAG_TXFT
SMARTCARD Interrupts Definition
SMARTCARD_IT_ERR
SMARTCARD_IT_FE
SMARTCARD_IT_IDLE
SMARTCARD_IT_NE
SMARTCARD_IT_ORE
SMARTCARD_IT_PE
SMARTCARD_IT_RTO
SMARTCARD_IT_RXFF
SMARTCARD_IT_RXFNE
SMARTCARD_IT_RXFT
SMARTCARD_IT_RXNE
SMARTCARD_IT_TC
SMARTCARD_IT_TCBGT
SMARTCARD_IT_TXE
SMARTCARD_IT_TXFE
SMARTCARD_IT_TXFNF
SMARTCARD_IT_TXFT
SMARTCARD Interruption Clear Flags
SMARTCARD_CLEAR_FEF
SMARTCARD_CLEAR_IDLEF
SMARTCARD_CLEAR_NEF
SMARTCARD_CLEAR_OREF
SMARTCARD_CLEAR_PEF
SMARTCARD_CLEAR_RTOF
SMARTCARD_CLEAR_TCBGTF
SMARTCARD_CLEAR_TCF
SMARTCARD_CLEAR_TXFECF
SMBUS
HAL_TIMEOUT_BUSY
HAL_TIMEOUT_DIR
HAL_TIMEOUT_RXNE
HAL_TIMEOUT_STOPF
HAL_TIMEOUT_TC
HAL_TIMEOUT_TCR
HAL_TIMEOUT_TXIS
MAX_NBYTE_SIZE
TIMING_CLEAR_MASK
SMBUS Exported Functions
HAL_SMBUS_ConfigDigitalFilter
HAL_SMBUS_DeInit
HAL_SMBUS_Init
HAL_SMBUS_MspDeInit
HAL_SMBUS_MspInit
HAL_SMBUS_RegisterAddrCallback
HAL_SMBUS_RegisterCallback
HAL_SMBUS_UnRegisterAddrCallback
HAL_SMBUS_UnRegisterCallback
Input and Output operation functions
Non-Blocking mode Interrupt
HAL_SMBUS_DisableListen_IT
HAL_SMBUS_EnableAlert_IT
HAL_SMBUS_EnableListen_IT
HAL_SMBUS_Master_Abort_IT
HAL_SMBUS_Master_Receive_IT
HAL_SMBUS_Master_Transmit_IT
HAL_SMBUS_Slave_Receive_IT
HAL_SMBUS_Slave_Transmit_IT
IRQ Handler and Callbacks
HAL_SMBUS_ER_IRQHandler
HAL_SMBUS_ErrorCallback
HAL_SMBUS_EV_IRQHandler
HAL_SMBUS_ListenCpltCallback
HAL_SMBUS_MasterRxCpltCallback
HAL_SMBUS_MasterTxCpltCallback
HAL_SMBUS_SlaveRxCpltCallback
HAL_SMBUS_SlaveTxCpltCallback
Peripheral State and Errors functions
HAL_SMBUS_GetState
Functions
HAL_SMBUS_DisableListen_IT
HAL_SMBUS_EnableAlert_IT
HAL_SMBUS_EnableListen_IT
HAL_SMBUS_IsDeviceReady
HAL_SMBUS_Master_Abort_IT
HAL_SMBUS_Master_Receive_IT
HAL_SMBUS_Master_Transmit_IT
HAL_SMBUS_Slave_Receive_IT
HAL_SMBUS_Slave_Transmit_IT
IRQ Handler and Callbacks
HAL_SMBUS_ER_IRQHandler
HAL_SMBUS_ErrorCallback
HAL_SMBUS_EV_IRQHandler
HAL_SMBUS_ListenCpltCallback
HAL_SMBUS_MasterRxCpltCallback
HAL_SMBUS_MasterTxCpltCallback
HAL_SMBUS_SlaveRxCpltCallback
HAL_SMBUS_SlaveTxCpltCallback
Peripheral State and Errors functions
HAL_SMBUS_GetState
SMBUS Private Functions
SMBUS_Disable_IRQ
SMBUS_Enable_IRQ
SMBUS_Flush_TXDR
SMBUS_ITErrorHandler
SMBUS_Master_ISR
SMBUS_Slave_ISR
SMBUS_TransferConfig
SMBUS_WaitOnFlagUntilTimeout
SMBUS Exported Types
HAL state definition
HAL_SMBUS_STATE_LISTEN
HAL_SMBUS_STATE_MASTER_BUSY_RX
HAL_SMBUS_STATE_MASTER_BUSY_TX
HAL_SMBUS_STATE_READY
HAL_SMBUS_STATE_RESET
HAL_SMBUS_STATE_SLAVE_BUSY_RX
HAL_SMBUS_STATE_SLAVE_BUSY_TX
SMBUS Error Code definition
HAL_SMBUS_ERROR_ALERT
HAL_SMBUS_ERROR_ARLO
HAL_SMBUS_ERROR_BERR
HAL_SMBUS_ERROR_BUSTIMEOUT
HAL_SMBUS_ERROR_HALTIMEOUT
HAL_SMBUS_ERROR_INVALID_CALLBACK
HAL_SMBUS_ERROR_INVALID_PARAM
HAL_SMBUS_ERROR_NONE
HAL_SMBUS_ERROR_OVR
HAL_SMBUS_ERROR_PECERR
SMBUS handle Structure definition
pSMBUS_CallbackTypeDef
SMBUS_HandleTypeDef
Enumerations
Data Structures
SMBUS Exported Constants
SMBUS_ANALOGFILTER_ENABLE
SMBUS addressing mode
SMBUS_ADDRESSINGMODE_7BIT
SMBUS dual addressing mode
SMBUS_DUALADDRESS_ENABLE
SMBUS ownaddress2 masks
SMBUS_OA2_MASK02
SMBUS_OA2_MASK03
SMBUS_OA2_MASK04
SMBUS_OA2_MASK05
SMBUS_OA2_MASK06
SMBUS_OA2_MASK07
SMBUS_OA2_NOMASK
SMBUS general call addressing mode
SMBUS_GENERALCALL_ENABLE
SMBUS nostretch mode
SMBUS_NOSTRETCH_ENABLE
SMBUS packet error check mode
SMBUS_PEC_ENABLE
SMBUS peripheral mode
SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE
SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP
SMBUS ReloadEndMode definition
SMBUS_RELOAD_MODE
SMBUS_SENDPEC_MODE
SMBUS_SOFTEND_MODE
SMBUS StartStopMode definition
SMBUS_GENERATE_START_WRITE
SMBUS_GENERATE_STOP
SMBUS_NO_STARTSTOP
SMBUS XferOptions definition
SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC
SMBUS_FIRST_FRAME
SMBUS_FIRST_FRAME_WITH_PEC
SMBUS_LAST_FRAME_NO_PEC
SMBUS_LAST_FRAME_WITH_PEC
SMBUS_NEXT_FRAME
SMBUS_OTHER_AND_LAST_FRAME_NO_PEC
SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC
SMBUS_OTHER_FRAME_NO_PEC
SMBUS_OTHER_FRAME_WITH_PEC
SMBUS Interrupt configuration definition
SMBUS_IT_ADDRI
SMBUS_IT_ALERT
SMBUS_IT_ERRI
SMBUS_IT_NACKI
SMBUS_IT_RX
SMBUS_IT_RXI
SMBUS_IT_STOPI
SMBUS_IT_TCI
SMBUS_IT_TX
SMBUS_IT_TXI
SMBUS Flag definition
SMBUS_FLAG_AF
SMBUS_FLAG_ALERT
SMBUS_FLAG_ARLO
SMBUS_FLAG_BERR
SMBUS_FLAG_BUSY
SMBUS_FLAG_DIR
SMBUS_FLAG_OVR
SMBUS_FLAG_PECERR
SMBUS_FLAG_RXNE
SMBUS_FLAG_STOPF
SMBUS_FLAG_TC
SMBUS_FLAG_TCR
SMBUS_FLAG_TIMEOUT
SMBUS_FLAG_TXE
SMBUS_FLAG_TXIS
SMBUS Exported Macros
__HAL_SMBUS_DISABLE
__HAL_SMBUS_DISABLE_IT
__HAL_SMBUS_ENABLE
__HAL_SMBUS_ENABLE_IT
__HAL_SMBUS_GENERATE_NACK
__HAL_SMBUS_GET_FLAG
__HAL_SMBUS_GET_IT_SOURCE
__HAL_SMBUS_RESET_HANDLE_STATE
SMBUS_FLAG_MASK
SMBUS Private Macros
IS_SMBUS_ANALOG_FILTER
IS_SMBUS_DIGITAL_FILTER
IS_SMBUS_DUAL_ADDRESS
IS_SMBUS_GENERAL_CALL
IS_SMBUS_NO_STRETCH
IS_SMBUS_OWN_ADDRESS1
IS_SMBUS_OWN_ADDRESS2
IS_SMBUS_OWN_ADDRESS2_MASK
IS_SMBUS_PEC
IS_SMBUS_PERIPHERAL_MODE
IS_SMBUS_TRANSFER_MODE
IS_SMBUS_TRANSFER_OPTIONS_REQUEST
IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST
IS_SMBUS_TRANSFER_REQUEST
SMBUS_CHECK_FLAG
SMBUS_CHECK_IT_SOURCE
SMBUS_GENERATE_START
SMBUS_GET_ADDR_MATCH
SMBUS_GET_ALERT_ENABLED
SMBUS_GET_DIR
SMBUS_GET_PEC_MODE
SMBUS_GET_STOP_MODE
SMBUS_RESET_CR1
SMBUS_RESET_CR2
SMBUS Private Functions
SMBUS_Disable_IRQ
SMBUS_Enable_IRQ
SMBUS_Flush_TXDR
SMBUS_ITErrorHandler
SMBUS_Master_ISR
SMBUS_Slave_ISR
SMBUS_TransferConfig
SMBUS_WaitOnFlagUntilTimeout
SMBUSEx
HAL_SMBUSEx_EnableWakeUp
Fast Mode Plus Functions
HAL_SMBUSEx_EnableFastModePlus
SMBUS Extended Exported Constants
SMBUS_FASTMODEPLUS_I2C2
SMBUS_FASTMODEPLUS_I2C3
SMBUS_FASTMODEPLUS_I2C4
SMBUS_FASTMODEPLUS_PB6
SMBUS_FASTMODEPLUS_PB7
SMBUS_FASTMODEPLUS_PB8
SMBUS_FASTMODEPLUS_PB9
SMBUS_FMP_NOT_SUPPORTED
SMBUS Extended Exported Macros
SMBUS Extended Private Constants
SMBUS Extended Private Macros
SMBUS Extended Private Functions
SPI
SPI Private Functions
SPI_2linesRxISR_16BITCRC
SPI_2linesRxISR_8BIT
SPI_2linesRxISR_8BITCRC
SPI_2linesTxISR_16BIT
SPI_2linesTxISR_8BIT
SPI_AbortRx_ISR
SPI_AbortTx_ISR
SPI_CloseRx_ISR
SPI_CloseRxTx_ISR
SPI_CloseTx_ISR
SPI_DMAAbortOnError
SPI_DMAError
SPI_DMAHalfReceiveCplt
SPI_DMAHalfTransmitCplt
SPI_DMAHalfTransmitReceiveCplt
SPI_DMAReceiveCplt
SPI_DMARxAbortCallback
SPI_DMATransmitCplt
SPI_DMATransmitReceiveCplt
SPI_DMATxAbortCallback
SPI_EndRxTransaction
SPI_EndRxTxTransaction
SPI_RxISR_16BIT
SPI_RxISR_16BITCRC
SPI_RxISR_8BIT
SPI_RxISR_8BITCRC
SPI_TxISR_16BIT
SPI_TxISR_8BIT
SPI_WaitFifoStateUntilTimeout
SPI_WaitFlagStateUntilTimeout
SPI Exported Functions
HAL_SPI_Init
HAL_SPI_MspDeInit
HAL_SPI_MspInit
HAL_SPI_RegisterCallback
HAL_SPI_UnRegisterCallback
IO operation functions
HAL_SPI_Abort_IT
HAL_SPI_AbortCpltCallback
HAL_SPI_DMAPause
HAL_SPI_DMAResume
HAL_SPI_DMAStop
HAL_SPI_ErrorCallback
HAL_SPI_IRQHandler
HAL_SPI_Receive
HAL_SPI_Receive_DMA
HAL_SPI_Receive_IT
HAL_SPI_RxCpltCallback
HAL_SPI_RxHalfCpltCallback
HAL_SPI_Transmit
HAL_SPI_Transmit_DMA
HAL_SPI_Transmit_IT
HAL_SPI_TransmitReceive
HAL_SPI_TransmitReceive_DMA
HAL_SPI_TransmitReceive_IT
HAL_SPI_TxCpltCallback
HAL_SPI_TxHalfCpltCallback
HAL_SPI_TxRxCpltCallback
HAL_SPI_TxRxHalfCpltCallback
Peripheral State and Errors functions
HAL_SPI_GetState
SPI Exported Types
SPI_HandleTypeDef
Enumerations
HAL_SPI_StateTypeDef
Data Structures
__SPI_HandleTypeDef
SPI Exported Constants
HAL_SPI_ERROR_CRC
HAL_SPI_ERROR_DMA
HAL_SPI_ERROR_FLAG
HAL_SPI_ERROR_FRE
HAL_SPI_ERROR_INVALID_CALLBACK
HAL_SPI_ERROR_MODF
HAL_SPI_ERROR_NONE
HAL_SPI_ERROR_OVR
SPI Mode
SPI_MODE_SLAVE
SPI Direction Mode
SPI_DIRECTION_2LINES
SPI_DIRECTION_2LINES_RXONLY
SPI Data Size
SPI_DATASIZE_11BIT
SPI_DATASIZE_12BIT
SPI_DATASIZE_13BIT
SPI_DATASIZE_14BIT
SPI_DATASIZE_15BIT
SPI_DATASIZE_16BIT
SPI_DATASIZE_4BIT
SPI_DATASIZE_5BIT
SPI_DATASIZE_6BIT
SPI_DATASIZE_7BIT
SPI_DATASIZE_8BIT
SPI_DATASIZE_9BIT
SPI Clock Polarity
SPI_POLARITY_LOW
SPI Clock Phase
SPI_PHASE_2EDGE
SPI Slave Select Management
SPI_NSS_HARD_OUTPUT
SPI_NSS_SOFT
SPI NSS Pulse Mode
SPI_NSS_PULSE_ENABLE
SPI BaudRate Prescaler
SPI_BAUDRATEPRESCALER_16
SPI_BAUDRATEPRESCALER_2
SPI_BAUDRATEPRESCALER_256
SPI_BAUDRATEPRESCALER_32
SPI_BAUDRATEPRESCALER_4
SPI_BAUDRATEPRESCALER_64
SPI_BAUDRATEPRESCALER_8
SPI MSB LSB Transmission
SPI_FIRSTBIT_MSB
SPI TI Mode
SPI_TIMODE_ENABLE
SPI CRC Calculation
SPI_CRCCALCULATION_ENABLE
SPI CRC Length
SPI_CRC_LENGTH_8BIT
SPI_CRC_LENGTH_DATASIZE
SPI FIFO Reception Threshold
SPI_RXFIFO_THRESHOLD_HF
SPI_RXFIFO_THRESHOLD_QF
SPI Interrupt Definition
SPI_IT_RXNE
SPI_IT_TXE
SPI Flags Definition
SPI_FLAG_CRCERR
SPI_FLAG_FRE
SPI_FLAG_FRLVL
SPI_FLAG_FTLVL
SPI_FLAG_MASK
SPI_FLAG_MODF
SPI_FLAG_OVR
SPI_FLAG_RXNE
SPI_FLAG_TXE
SPI Transmission FIFO Status Level
SPI_FTLVL_FULL
SPI_FTLVL_HALF_FULL
SPI_FTLVL_QUARTER_FULL
SPI Reception FIFO Status Level
SPI_FRLVL_FULL
SPI_FRLVL_HALF_FULL
SPI_FRLVL_QUARTER_FULL
SPI Exported Macros
__HAL_SPI_CLEAR_FREFLAG
__HAL_SPI_CLEAR_MODFFLAG
__HAL_SPI_CLEAR_OVRFLAG
__HAL_SPI_DISABLE
__HAL_SPI_DISABLE_IT
__HAL_SPI_ENABLE
__HAL_SPI_ENABLE_IT
__HAL_SPI_GET_FLAG
__HAL_SPI_GET_IT_SOURCE
__HAL_SPI_RESET_HANDLE_STATE
SPI Private Macros
IS_SPI_CPHA
IS_SPI_CPOL
IS_SPI_CRC_CALCULATION
IS_SPI_CRC_LENGTH
IS_SPI_CRC_POLYNOMIAL
IS_SPI_DATASIZE
IS_SPI_DIRECTION
IS_SPI_DIRECTION_2LINES
IS_SPI_DIRECTION_2LINES_OR_1LINE
IS_SPI_DMA_HANDLE
IS_SPI_FIRST_BIT
IS_SPI_MODE
IS_SPI_NSS
IS_SPI_NSSP
IS_SPI_TIMODE
SPI_1LINE_RX
SPI_1LINE_TX
SPI_CHECK_FLAG
SPI_CHECK_IT_SOURCE
SPI_RESET_CRC
SPIEx
SPIEx Exported Functions
SRAM
HAL_SRAM_DMA_XferCpltCallback
HAL_SRAM_DMA_XferErrorCallback
HAL_SRAM_Init
HAL_SRAM_MspDeInit
HAL_SRAM_MspInit
Input Output and memory control functions
HAL_SRAM_Read_32b
HAL_SRAM_Read_8b
HAL_SRAM_Read_DMA
HAL_SRAM_RegisterCallback
HAL_SRAM_RegisterDmaCallback
HAL_SRAM_UnRegisterCallback
HAL_SRAM_Write_16b
HAL_SRAM_Write_32b
HAL_SRAM_Write_8b
HAL_SRAM_Write_DMA
Control functions
HAL_SRAM_WriteOperation_Enable
Peripheral State functions
SRAM Private Functions
SRAM_DMACpltProt
SRAM_DMAError
TIM
HAL_TIM_Base_Init
HAL_TIM_Base_MspDeInit
HAL_TIM_Base_MspInit
HAL_TIM_Base_Start
HAL_TIM_Base_Start_DMA
HAL_TIM_Base_Start_IT
HAL_TIM_Base_Stop
HAL_TIM_Base_Stop_DMA
HAL_TIM_Base_Stop_IT
TIM Output Compare functions
HAL_TIM_OC_Init
HAL_TIM_OC_MspDeInit
HAL_TIM_OC_MspInit
HAL_TIM_OC_Start
HAL_TIM_OC_Start_DMA
HAL_TIM_OC_Start_IT
HAL_TIM_OC_Stop
HAL_TIM_OC_Stop_DMA
HAL_TIM_OC_Stop_IT
TIM PWM functions
HAL_TIM_PWM_Init
HAL_TIM_PWM_MspDeInit
HAL_TIM_PWM_MspInit
HAL_TIM_PWM_Start
HAL_TIM_PWM_Start_DMA
HAL_TIM_PWM_Start_IT
HAL_TIM_PWM_Stop
HAL_TIM_PWM_Stop_DMA
HAL_TIM_PWM_Stop_IT
TIM Input Capture functions
HAL_TIM_IC_Init
HAL_TIM_IC_MspDeInit
HAL_TIM_IC_MspInit
HAL_TIM_IC_Start
HAL_TIM_IC_Start_DMA
HAL_TIM_IC_Start_IT
HAL_TIM_IC_Stop
HAL_TIM_IC_Stop_DMA
HAL_TIM_IC_Stop_IT
TIM One Pulse functions
HAL_TIM_OnePulse_Init
HAL_TIM_OnePulse_MspDeInit
HAL_TIM_OnePulse_MspInit
HAL_TIM_OnePulse_Start
HAL_TIM_OnePulse_Start_IT
HAL_TIM_OnePulse_Stop
HAL_TIM_OnePulse_Stop_IT
TIM Encoder functions
HAL_TIM_Encoder_Init
HAL_TIM_Encoder_MspDeInit
HAL_TIM_Encoder_MspInit
HAL_TIM_Encoder_Start
HAL_TIM_Encoder_Start_DMA
HAL_TIM_Encoder_Start_IT
HAL_TIM_Encoder_Stop
HAL_TIM_Encoder_Stop_DMA
HAL_TIM_Encoder_Stop_IT
TIM IRQ handler management
TIM Peripheral Control functions
HAL_TIM_ConfigOCrefClear
HAL_TIM_ConfigTI1Input
HAL_TIM_DMABurst_MultiReadStart
HAL_TIM_DMABurst_MultiWriteStart
HAL_TIM_DMABurst_ReadStart
HAL_TIM_DMABurst_ReadStop
HAL_TIM_DMABurst_WriteStart
HAL_TIM_DMABurst_WriteStop
HAL_TIM_GenerateEvent
HAL_TIM_IC_ConfigChannel
HAL_TIM_OC_ConfigChannel
HAL_TIM_OnePulse_ConfigChannel
HAL_TIM_PWM_ConfigChannel
HAL_TIM_ReadCapturedValue
HAL_TIM_SlaveConfigSynchro
HAL_TIM_SlaveConfigSynchro_IT
TIM Callbacks functions
HAL_TIM_IC_CaptureCallback
HAL_TIM_IC_CaptureHalfCpltCallback
HAL_TIM_OC_DelayElapsedCallback
HAL_TIM_PeriodElapsedCallback
HAL_TIM_PeriodElapsedHalfCpltCallback
HAL_TIM_PWM_PulseFinishedCallback
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
HAL_TIM_RegisterCallback
HAL_TIM_TriggerCallback
HAL_TIM_TriggerHalfCpltCallback
HAL_TIM_UnRegisterCallback
TIM Peripheral State functions
HAL_TIM_DMABurstState
HAL_TIM_Encoder_GetState
HAL_TIM_GetActiveChannel
HAL_TIM_GetChannelState
HAL_TIM_IC_GetState
HAL_TIM_OC_GetState
HAL_TIM_OnePulse_GetState
HAL_TIM_PWM_GetState
TIM Private Functions
TIM_CCxChannelCmd
TIM_DMACaptureCplt
TIM_DMACaptureHalfCplt
TIM_DMADelayPulseCplt
TIM_DMADelayPulseHalfCplt
TIM_DMAError
TIM_DMAPeriodElapsedCplt
TIM_DMAPeriodElapsedHalfCplt
TIM_DMATriggerCplt
TIM_DMATriggerHalfCplt
TIM_ETR_SetConfig
TIM_ITRx_SetConfig
TIM_OC1_SetConfig
TIM_OC2_SetConfig
TIM_OC3_SetConfig
TIM_OC4_SetConfig
TIM_OC5_SetConfig
TIM_OC6_SetConfig
TIM_ResetCallback
TIM_SlaveTimer_SetConfig
TIM_TI1_ConfigInputStage
TIM_TI1_SetConfig
TIM_TI2_ConfigInputStage
TIM_TI2_SetConfig
TIM_TI3_SetConfig
TIM_TI4_SetConfig
TIM Exported Types
TIM_HandleTypeDef
Enumerations
HAL_TIM_CallbackIDTypeDef
HAL_TIM_ChannelStateTypeDef
HAL_TIM_DMABurstStateTypeDef
HAL_TIM_StateTypeDef
Data Structures
TIM_OC_InitTypeDef
TIM_OnePulse_InitTypeDef
TIM_IC_InitTypeDef
TIM_Encoder_InitTypeDef
TIM_ClockConfigTypeDef
TIM_ClearInputConfigTypeDef
TIM_MasterConfigTypeDef
TIM_SlaveConfigTypeDef
TIM_BreakDeadTimeConfigTypeDef
__TIM_HandleTypeDef
TIM Exported Constants
TIM_CLEARINPUTSOURCE_COMP2
TIM_CLEARINPUTSOURCE_COMP3
TIM_CLEARINPUTSOURCE_COMP4
TIM_CLEARINPUTSOURCE_COMP5
TIM_CLEARINPUTSOURCE_COMP6
TIM_CLEARINPUTSOURCE_COMP7
TIM_CLEARINPUTSOURCE_ETR
TIM_CLEARINPUTSOURCE_NONE
TIM DMA Base Address
TIM_DMABASE_AF2
TIM_DMABASE_ARR
TIM_DMABASE_BDTR
TIM_DMABASE_CCER
TIM_DMABASE_CCMR1
TIM_DMABASE_CCMR2
TIM_DMABASE_CCMR3
TIM_DMABASE_CCR1
TIM_DMABASE_CCR2
TIM_DMABASE_CCR3
TIM_DMABASE_CCR4
TIM_DMABASE_CCR5
TIM_DMABASE_CCR6
TIM_DMABASE_CNT
TIM_DMABASE_CR1
TIM_DMABASE_CR2
TIM_DMABASE_DIER
TIM_DMABASE_DTR2
TIM_DMABASE_ECR
TIM_DMABASE_EGR
TIM_DMABASE_OR
TIM_DMABASE_PSC
TIM_DMABASE_RCR
TIM_DMABASE_SMCR
TIM_DMABASE_SR
TIM_DMABASE_TISEL
TIM Event Source
TIM_EVENTSOURCE_BREAK2
TIM_EVENTSOURCE_CC1
TIM_EVENTSOURCE_CC2
TIM_EVENTSOURCE_CC3
TIM_EVENTSOURCE_CC4
TIM_EVENTSOURCE_COM
TIM_EVENTSOURCE_TRIGGER
TIM_EVENTSOURCE_UPDATE
TIM Input Channel polarity
TIM_INPUTCHANNELPOLARITY_FALLING
TIM_INPUTCHANNELPOLARITY_RISING
TIM ETR Polarity
TIM_ETRPOLARITY_NONINVERTED
TIM ETR Prescaler
TIM_ETRPRESCALER_DIV2
TIM_ETRPRESCALER_DIV4
TIM_ETRPRESCALER_DIV8
TIM Counter Mode
TIM_COUNTERMODE_CENTERALIGNED2
TIM_COUNTERMODE_CENTERALIGNED3
TIM_COUNTERMODE_DOWN
TIM_COUNTERMODE_UP
TIM Update Interrupt Flag Remap
TIM_UIFREMAP_ENABLE
TIM Clock Division
TIM_CLOCKDIVISION_DIV2
TIM_CLOCKDIVISION_DIV4
TIM Output Compare State
TIM_OUTPUTSTATE_ENABLE
TIM Auto-Reload Preload
TIM_AUTORELOAD_PRELOAD_ENABLE
TIM Output Fast State
TIM_OCFAST_ENABLE
TIM Complementary Output Compare State
TIM_OUTPUTNSTATE_ENABLE
TIM Output Compare Polarity
TIM_OCPOLARITY_LOW
TIM Complementary Output Compare Polarity
TIM_OCNPOLARITY_LOW
TIM Output Compare Idle State
TIM_OCIDLESTATE_SET
TIM Complementary Output Compare Idle State
TIM_OCNIDLESTATE_SET
TIM Input Capture Polarity
TIM_ICPOLARITY_FALLING
TIM_ICPOLARITY_RISING
TIM Encoder Input Polarity
TIM_ENCODERINPUTPOLARITY_RISING
TIM Input Capture Selection
TIM_ICSELECTION_INDIRECTTI
TIM_ICSELECTION_TRC
TIM Input Capture Prescaler
TIM_ICPSC_DIV2
TIM_ICPSC_DIV4
TIM_ICPSC_DIV8
TIM One Pulse Mode
TIM_OPMODE_SINGLE
TIM Encoder Mode
TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
TIM_ENCODERMODE_TI1
TIM_ENCODERMODE_TI12
TIM_ENCODERMODE_TI2
TIM_ENCODERMODE_X1_TI1
TIM_ENCODERMODE_X1_TI2
TIM interrupt Definition
TIM_IT_CC1
TIM_IT_CC2
TIM_IT_CC3
TIM_IT_CC4
TIM_IT_COM
TIM_IT_DIR
TIM_IT_IDX
TIM_IT_IERR
TIM_IT_TERR
TIM_IT_TRIGGER
TIM_IT_UPDATE
TIM Commutation Source
TIM_COMMUTATION_TRGI
TIM DMA Sources
TIM_DMA_CC2
TIM_DMA_CC3
TIM_DMA_CC4
TIM_DMA_COM
TIM_DMA_TRIGGER
TIM_DMA_UPDATE
CCx DMA request selection
TIM_CCDMAREQUEST_UPDATE
TIM Flag Definition
TIM_FLAG_BREAK2
TIM_FLAG_CC1
TIM_FLAG_CC1OF
TIM_FLAG_CC2
TIM_FLAG_CC2OF
TIM_FLAG_CC3
TIM_FLAG_CC3OF
TIM_FLAG_CC4
TIM_FLAG_CC4OF
TIM_FLAG_CC5
TIM_FLAG_CC6
TIM_FLAG_COM
TIM_FLAG_DIR
TIM_FLAG_IDX
TIM_FLAG_IERR
TIM_FLAG_SYSTEM_BREAK
TIM_FLAG_TERR
TIM_FLAG_TRIGGER
TIM_FLAG_UPDATE
TIM Channel
TIM_CHANNEL_2
TIM_CHANNEL_3
TIM_CHANNEL_4
TIM_CHANNEL_5
TIM_CHANNEL_6
TIM_CHANNEL_ALL
TIM Clock Source
TIM_CLOCKSOURCE_ETRMODE2
TIM_CLOCKSOURCE_INTERNAL
TIM_CLOCKSOURCE_ITR0
TIM_CLOCKSOURCE_ITR1
TIM_CLOCKSOURCE_ITR10
TIM_CLOCKSOURCE_ITR11
TIM_CLOCKSOURCE_ITR2
TIM_CLOCKSOURCE_ITR3
TIM_CLOCKSOURCE_ITR4
TIM_CLOCKSOURCE_ITR5
TIM_CLOCKSOURCE_ITR6
TIM_CLOCKSOURCE_ITR7
TIM_CLOCKSOURCE_ITR8
TIM_CLOCKSOURCE_ITR9
TIM_CLOCKSOURCE_TI1
TIM_CLOCKSOURCE_TI1ED
TIM_CLOCKSOURCE_TI2
TIM Clock Polarity
TIM_CLOCKPOLARITY_FALLING
TIM_CLOCKPOLARITY_INVERTED
TIM_CLOCKPOLARITY_NONINVERTED
TIM_CLOCKPOLARITY_RISING
TIM Clock Prescaler
TIM_CLOCKPRESCALER_DIV2
TIM_CLOCKPRESCALER_DIV4
TIM_CLOCKPRESCALER_DIV8
TIM Clear Input Polarity
TIM_CLEARINPUTPOLARITY_NONINVERTED
TIM Clear Input Prescaler
TIM_CLEARINPUTPRESCALER_DIV2
TIM_CLEARINPUTPRESCALER_DIV4
TIM_CLEARINPUTPRESCALER_DIV8
TIM OSSR OffState Selection for Run mode state
TIM_OSSR_ENABLE
TIM OSSI OffState Selection for Idle mode state
TIM_OSSI_ENABLE
TIM Lock level
TIM_LOCKLEVEL_2
TIM_LOCKLEVEL_3
TIM_LOCKLEVEL_OFF
TIM Break Input Enable
TIM_BREAK_ENABLE
TIM Break Input Polarity
TIM_BREAKPOLARITY_LOW
TIM Break Input Alternate Function Mode
TIM_BREAK_AFMODE_INPUT
TIM Break input 2 Enable
TIM_BREAK2_ENABLE
TIM Break Input 2 Polarity
TIM_BREAK2POLARITY_LOW
TIM Break2 Input Alternate Function Mode
TIM_BREAK2_AFMODE_INPUT
TIM Automatic Output Enable
TIM_AUTOMATICOUTPUT_ENABLE
TIM Group Channel 5 and Channel 1, 2 or 3
TIM_GROUPCH5_OC1REFC
TIM_GROUPCH5_OC2REFC
TIM_GROUPCH5_OC3REFC
TIM Master Mode Selection
TIM_TRGO_ENCODER_CLK
TIM_TRGO_OC1
TIM_TRGO_OC1REF
TIM_TRGO_OC2REF
TIM_TRGO_OC3REF
TIM_TRGO_OC4REF
TIM_TRGO_RESET
TIM_TRGO_UPDATE
TIM Master Mode Selection 2 (TRGO2)
TIM_TRGO2_OC1
TIM_TRGO2_OC1REF
TIM_TRGO2_OC2REF
TIM_TRGO2_OC3REF
TIM_TRGO2_OC4REF
TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING
TIM_TRGO2_OC4REF_RISING_OC6REF_RISING
TIM_TRGO2_OC4REF_RISINGFALLING
TIM_TRGO2_OC5REF
TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING
TIM_TRGO2_OC5REF_RISING_OC6REF_RISING
TIM_TRGO2_OC6REF
TIM_TRGO2_OC6REF_RISINGFALLING
TIM_TRGO2_RESET
TIM_TRGO2_UPDATE
TIM Master/Slave Mode
TIM_MASTERSLAVEMODE_ENABLE
TIM Slave mode
TIM_SLAVEMODE_COMBINED_RESETTRIGGER
TIM_SLAVEMODE_DISABLE
TIM_SLAVEMODE_EXTERNAL1
TIM_SLAVEMODE_GATED
TIM_SLAVEMODE_RESET
TIM_SLAVEMODE_TRIGGER
TIM Output Compare and PWM Modes
TIM_OCMODE_ASYMMETRIC_PWM1
TIM_OCMODE_ASYMMETRIC_PWM2
TIM_OCMODE_COMBINED_PWM1
TIM_OCMODE_COMBINED_PWM2
TIM_OCMODE_DIRECTION_OUTPUT
TIM_OCMODE_FORCED_ACTIVE
TIM_OCMODE_FORCED_INACTIVE
TIM_OCMODE_INACTIVE
TIM_OCMODE_PULSE_ON_COMPARE
TIM_OCMODE_PWM1
TIM_OCMODE_PWM2
TIM_OCMODE_RETRIGERRABLE_OPM1
TIM_OCMODE_RETRIGERRABLE_OPM2
TIM_OCMODE_TIMING
TIM_OCMODE_TOGGLE
TIM Trigger Selection
TIM_TS_ITR0
TIM_TS_ITR1
TIM_TS_ITR10
TIM_TS_ITR11
TIM_TS_ITR2
TIM_TS_ITR3
TIM_TS_ITR4
TIM_TS_ITR5
TIM_TS_ITR6
TIM_TS_ITR7
TIM_TS_ITR8
TIM_TS_ITR9
TIM_TS_NONE
TIM_TS_TI1F_ED
TIM_TS_TI1FP1
TIM_TS_TI2FP2
TIM Trigger Polarity
TIM_TRIGGERPOLARITY_FALLING
TIM_TRIGGERPOLARITY_INVERTED
TIM_TRIGGERPOLARITY_NONINVERTED
TIM_TRIGGERPOLARITY_RISING
TIM Trigger Prescaler
TIM_TRIGGERPRESCALER_DIV2
TIM_TRIGGERPRESCALER_DIV4
TIM_TRIGGERPRESCALER_DIV8
TIM TI1 Input Selection
TIM_TI1SELECTION_XORCOMBINATION
TIM DMA Burst Length
TIM_DMABURSTLENGTH_11TRANSFERS
TIM_DMABURSTLENGTH_12TRANSFERS
TIM_DMABURSTLENGTH_13TRANSFERS
TIM_DMABURSTLENGTH_14TRANSFERS
TIM_DMABURSTLENGTH_15TRANSFERS
TIM_DMABURSTLENGTH_16TRANSFERS
TIM_DMABURSTLENGTH_17TRANSFERS
TIM_DMABURSTLENGTH_18TRANSFERS
TIM_DMABURSTLENGTH_19TRANSFERS
TIM_DMABURSTLENGTH_1TRANSFER
TIM_DMABURSTLENGTH_20TRANSFERS
TIM_DMABURSTLENGTH_21TRANSFERS
TIM_DMABURSTLENGTH_22TRANSFERS
TIM_DMABURSTLENGTH_23TRANSFERS
TIM_DMABURSTLENGTH_24TRANSFERS
TIM_DMABURSTLENGTH_25TRANSFERS
TIM_DMABURSTLENGTH_26TRANSFERS
TIM_DMABURSTLENGTH_2TRANSFERS
TIM_DMABURSTLENGTH_3TRANSFERS
TIM_DMABURSTLENGTH_4TRANSFERS
TIM_DMABURSTLENGTH_5TRANSFERS
TIM_DMABURSTLENGTH_6TRANSFERS
TIM_DMABURSTLENGTH_7TRANSFERS
TIM_DMABURSTLENGTH_8TRANSFERS
TIM_DMABURSTLENGTH_9TRANSFERS
TIM DMA Handle Index
TIM_DMA_ID_CC2
TIM_DMA_ID_CC3
TIM_DMA_ID_CC4
TIM_DMA_ID_COMMUTATION
TIM_DMA_ID_TRIGGER
TIM_DMA_ID_UPDATE
TIM Capture/Compare Channel State
TIM_CCx_ENABLE
TIM_CCxN_DISABLE
TIM_CCxN_ENABLE
TIM Break System
TIM_BREAK_SYSTEM_LOCKUP
TIM_BREAK_SYSTEM_PVD
TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR
TIM Exported Macros
__HAL_TIM_CLEAR_IT
__HAL_TIM_DISABLE
__HAL_TIM_DISABLE_DMA
__HAL_TIM_DISABLE_IT
__HAL_TIM_DISABLE_OCxFAST
__HAL_TIM_DISABLE_OCxPRELOAD
__HAL_TIM_ENABLE
__HAL_TIM_ENABLE_DMA
__HAL_TIM_ENABLE_IT
__HAL_TIM_ENABLE_OCxFAST
__HAL_TIM_ENABLE_OCxPRELOAD
__HAL_TIM_GET_AUTORELOAD
__HAL_TIM_GET_CLOCKDIVISION
__HAL_TIM_GET_COMPARE
__HAL_TIM_GET_COUNTER
__HAL_TIM_GET_FLAG
__HAL_TIM_GET_ICPRESCALER
__HAL_TIM_GET_IT_SOURCE
__HAL_TIM_GET_UIFCPY
__HAL_TIM_IS_TIM_COUNTING_DOWN
__HAL_TIM_MOE_DISABLE
__HAL_TIM_MOE_DISABLE_UNCONDITIONALLY
__HAL_TIM_MOE_ENABLE
__HAL_TIM_RESET_HANDLE_STATE
__HAL_TIM_SELECT_CCDMAREQUEST
__HAL_TIM_SET_AUTORELOAD
__HAL_TIM_SET_CAPTUREPOLARITY
__HAL_TIM_SET_CLOCKDIVISION
__HAL_TIM_SET_COMPARE
__HAL_TIM_SET_COUNTER
__HAL_TIM_SET_ICPRESCALER
__HAL_TIM_SET_PRESCALER
__HAL_TIM_UIFREMAP_DISABLE
__HAL_TIM_UIFREMAP_ENABLE
__HAL_TIM_URS_DISABLE
__HAL_TIM_URS_ENABLE
TIM Private Constants
TIM_CCER_CCxNE_MASK
TIMx_AF2_OCRSEL
TIM Private Macros
IS_TIM_AUTORELOAD_PRELOAD
IS_TIM_BREAK2_AFMODE
IS_TIM_BREAK2_POLARITY
IS_TIM_BREAK2_STATE
IS_TIM_BREAK_AFMODE
IS_TIM_BREAK_FILTER
IS_TIM_BREAK_POLARITY
IS_TIM_BREAK_STATE
IS_TIM_BREAK_SYSTEM
IS_TIM_CCX_CHANNEL
IS_TIM_CHANNELS
IS_TIM_CLEARINPUT_FILTER
IS_TIM_CLEARINPUT_POLARITY
IS_TIM_CLEARINPUT_PRESCALER
IS_TIM_CLEARINPUT_SOURCE
IS_TIM_CLOCKDIVISION_DIV
IS_TIM_CLOCKFILTER
IS_TIM_CLOCKPOLARITY
IS_TIM_CLOCKPRESCALER
IS_TIM_CLOCKSOURCE
IS_TIM_COMPLEMENTARY_CHANNELS
IS_TIM_COUNTER_MODE
IS_TIM_DEADTIME
IS_TIM_DMA_BASE
IS_TIM_DMA_DATA_LENGTH
IS_TIM_DMA_LENGTH
IS_TIM_DMA_SOURCE
IS_TIM_ENCODER_MODE
IS_TIM_ENCODERINPUT_POLARITY
IS_TIM_EVENT_SOURCE
IS_TIM_FAST_STATE
IS_TIM_GROUPCH5
IS_TIM_IC_FILTER
IS_TIM_IC_POLARITY
IS_TIM_IC_PRESCALER
IS_TIM_IC_SELECTION
IS_TIM_LOCK_LEVEL
IS_TIM_MSM_STATE
IS_TIM_OC_MODE
IS_TIM_OC_POLARITY
IS_TIM_OCIDLE_STATE
IS_TIM_OCN_POLARITY
IS_TIM_OCNIDLE_STATE
IS_TIM_OPM_CHANNELS
IS_TIM_OPM_MODE
IS_TIM_OSSI_STATE
IS_TIM_OSSR_STATE
IS_TIM_PERIOD
IS_TIM_PWM_MODE
IS_TIM_SLAVE_MODE
IS_TIM_SLAVEMODE_TRIGGER_ENABLED
IS_TIM_TI1SELECTION
IS_TIM_TRGO2_SOURCE
IS_TIM_TRGO_SOURCE
IS_TIM_TRIGGERFILTER
IS_TIM_TRIGGERPOLARITY
IS_TIM_TRIGGERPRESCALER
IS_TIM_UIFREMAP_MODE
TIM_CHANNEL_N_STATE_GET
TIM_CHANNEL_N_STATE_SET
TIM_CHANNEL_N_STATE_SET_ALL
TIM_CHANNEL_STATE_GET
TIM_CHANNEL_STATE_SET
TIM_CHANNEL_STATE_SET_ALL
TIM_RESET_CAPTUREPOLARITY
TIM_RESET_ICPRESCALERVALUE
TIM_SET_CAPTUREPOLARITY
TIM_SET_ICPRESCALERVALUE
TIMEx
TIM Extended Exported Functions
HAL_TIMEx_HallSensor_Init
HAL_TIMEx_HallSensor_MspDeInit
HAL_TIMEx_HallSensor_MspInit
HAL_TIMEx_HallSensor_Start
HAL_TIMEx_HallSensor_Start_DMA
HAL_TIMEx_HallSensor_Start_IT
HAL_TIMEx_HallSensor_Stop
HAL_TIMEx_HallSensor_Stop_DMA
HAL_TIMEx_HallSensor_Stop_IT
Extended Timer Complementary Output Compare functions
HAL_TIMEx_OCN_Start_DMA
HAL_TIMEx_OCN_Start_IT
HAL_TIMEx_OCN_Stop
HAL_TIMEx_OCN_Stop_DMA
HAL_TIMEx_OCN_Stop_IT
Extended Timer Complementary PWM functions
HAL_TIMEx_PWMN_Start_DMA
HAL_TIMEx_PWMN_Start_IT
HAL_TIMEx_PWMN_Stop
HAL_TIMEx_PWMN_Stop_DMA
HAL_TIMEx_PWMN_Stop_IT
Extended Timer Complementary One Pulse functions
HAL_TIMEx_OnePulseN_Start_IT
HAL_TIMEx_OnePulseN_Stop
HAL_TIMEx_OnePulseN_Stop_IT
Extended Peripheral Control functions
HAL_TIMEx_ConfigBreakDeadTime
HAL_TIMEx_ConfigBreakInput
HAL_TIMEx_ConfigCommutEvent
HAL_TIMEx_ConfigCommutEvent_DMA
HAL_TIMEx_ConfigCommutEvent_IT
HAL_TIMEx_ConfigDeadTime
HAL_TIMEx_ConfigEncoderIndex
HAL_TIMEx_ConfigSlaveModePreload
HAL_TIMEx_DisableAsymmetricalDeadTime
HAL_TIMEx_DisableDeadTimePreload
HAL_TIMEx_DisableEncoderFirstIndex
HAL_TIMEx_DisableEncoderIndex
HAL_TIMEx_DisableSlaveModePreload
HAL_TIMEx_DisarmBreakInput
HAL_TIMEx_DitheringDisable
HAL_TIMEx_DitheringEnable
HAL_TIMEx_EnableAsymmetricalDeadTime
HAL_TIMEx_EnableDeadTimePreload
HAL_TIMEx_EnableEncoderFirstIndex
HAL_TIMEx_EnableEncoderIndex
HAL_TIMEx_EnableSlaveModePreload
HAL_TIMEx_GroupChannel5
HAL_TIMEx_MasterConfigSynchronization
HAL_TIMEx_OC_ConfigPulseOnCompare
HAL_TIMEx_ReArmBreakInput
HAL_TIMEx_RemapConfig
HAL_TIMEx_TISelection
Extended Callbacks functions
HAL_TIMEx_BreakCallback
HAL_TIMEx_CommutCallback
HAL_TIMEx_CommutHalfCpltCallback
HAL_TIMEx_DirectionChangeCallback
HAL_TIMEx_EncoderIndexCallback
HAL_TIMEx_IndexErrorCallback
HAL_TIMEx_TransitionErrorCallback
Extended Peripheral State functions
HAL_TIMEx_HallSensor_GetState
TIM Extended Private Functions
TIM_DMADelayPulseNCplt
TIM_DMAErrorCCxN
TIMEx_DMACommutationCplt
TIMEx_DMACommutationHalfCplt
TIM Extended Exported Types
TIMEx_BreakInputConfigTypeDef
TIMEx_EncoderIndexConfigTypeDef
TIM Extended Exported Constants
TIM_TIM1_ETR_ADC1_AWD2
TIM_TIM1_ETR_ADC1_AWD3
TIM_TIM1_ETR_ADC4_AWD1
TIM_TIM1_ETR_ADC4_AWD2
TIM_TIM1_ETR_ADC4_AWD3
TIM_TIM1_ETR_COMP1
TIM_TIM1_ETR_COMP2
TIM_TIM1_ETR_COMP3
TIM_TIM1_ETR_COMP4
TIM_TIM1_ETR_COMP5
TIM_TIM1_ETR_COMP6
TIM_TIM1_ETR_COMP7
TIM_TIM1_ETR_GPIO
TIM_TIM20_ETR_ADC3_AWD1
TIM_TIM20_ETR_ADC3_AWD2
TIM_TIM20_ETR_ADC3_AWD3
TIM_TIM20_ETR_ADC5_AWD1
TIM_TIM20_ETR_ADC5_AWD2
TIM_TIM20_ETR_ADC5_AWD3
TIM_TIM20_ETR_COMP1
TIM_TIM20_ETR_COMP2
TIM_TIM20_ETR_COMP3
TIM_TIM20_ETR_COMP4
TIM_TIM20_ETR_COMP5
TIM_TIM20_ETR_COMP6
TIM_TIM20_ETR_COMP7
TIM_TIM20_ETR_GPIO
TIM_TIM2_ETR_COMP1
TIM_TIM2_ETR_COMP2
TIM_TIM2_ETR_COMP3
TIM_TIM2_ETR_COMP4
TIM_TIM2_ETR_COMP5
TIM_TIM2_ETR_COMP6
TIM_TIM2_ETR_COMP7
TIM_TIM2_ETR_GPIO
TIM_TIM2_ETR_LSE
TIM_TIM2_ETR_TIM3_ETR
TIM_TIM2_ETR_TIM4_ETR
TIM_TIM2_ETR_TIM5_ETR
TIM_TIM3_ETR_ADC2_AWD1
TIM_TIM3_ETR_ADC2_AWD2
TIM_TIM3_ETR_ADC2_AWD3
TIM_TIM3_ETR_COMP1
TIM_TIM3_ETR_COMP2
TIM_TIM3_ETR_COMP3
TIM_TIM3_ETR_COMP4
TIM_TIM3_ETR_COMP5
TIM_TIM3_ETR_COMP6
TIM_TIM3_ETR_COMP7
TIM_TIM3_ETR_GPIO
TIM_TIM3_ETR_TIM2_ETR
TIM_TIM3_ETR_TIM4_ETR
TIM_TIM4_ETR_COMP1
TIM_TIM4_ETR_COMP2
TIM_TIM4_ETR_COMP3
TIM_TIM4_ETR_COMP4
TIM_TIM4_ETR_COMP5
TIM_TIM4_ETR_COMP6
TIM_TIM4_ETR_COMP7
TIM_TIM4_ETR_GPIO
TIM_TIM4_ETR_TIM3_ETR
TIM_TIM4_ETR_TIM5_ETR
TIM_TIM5_ETR_COMP1
TIM_TIM5_ETR_COMP2
TIM_TIM5_ETR_COMP3
TIM_TIM5_ETR_COMP4
TIM_TIM5_ETR_COMP5
TIM_TIM5_ETR_COMP6
TIM_TIM5_ETR_COMP7
TIM_TIM5_ETR_GPIO
TIM_TIM5_ETR_TIM2_ETR
TIM_TIM5_ETR_TIM3_ETR
TIM_TIM8_ETR_ADC2_AWD1
TIM_TIM8_ETR_ADC2_AWD2
TIM_TIM8_ETR_ADC2_AWD3
TIM_TIM8_ETR_ADC3_AWD1
TIM_TIM8_ETR_ADC3_AWD2
TIM_TIM8_ETR_ADC3_AWD3
TIM_TIM8_ETR_COMP1
TIM_TIM8_ETR_COMP2
TIM_TIM8_ETR_COMP3
TIM_TIM8_ETR_COMP4
TIM_TIM8_ETR_COMP5
TIM_TIM8_ETR_COMP6
TIM_TIM8_ETR_COMP7
TIM_TIM8_ETR_GPIO
TIM Extended Break input
TIM_BREAKINPUT_BRK2
TIM Extended Break input source
TIM_BREAKINPUTSOURCE_COMP1
TIM_BREAKINPUTSOURCE_COMP2
TIM_BREAKINPUTSOURCE_COMP3
TIM_BREAKINPUTSOURCE_COMP4
TIM_BREAKINPUTSOURCE_COMP5
TIM_BREAKINPUTSOURCE_COMP6
TIM_BREAKINPUTSOURCE_COMP7
TIM Extended Break input source enabling
TIM_BREAKINPUTSOURCE_ENABLE
TIM Extended Break input polarity
TIM_BREAKINPUTSOURCE_POLARITY_LOW
TIM Extended Timer input selection
TIM_TIM15_TI1_COMP2
TIM_TIM15_TI1_COMP5
TIM_TIM15_TI1_COMP7
TIM_TIM15_TI1_GPIO
TIM_TIM15_TI1_LSE
TIM_TIM15_TI2_COMP2
TIM_TIM15_TI2_COMP3
TIM_TIM15_TI2_COMP6
TIM_TIM15_TI2_COMP7
TIM_TIM15_TI2_GPIO
TIM_TIM16_TI1_COMP6
TIM_TIM16_TI1_GPIO
TIM_TIM16_TI1_HSE_32
TIM_TIM16_TI1_LSE
TIM_TIM16_TI1_LSI
TIM_TIM16_TI1_MCO
TIM_TIM16_TI1_RTC_WK
TIM_TIM17_TI1_COMP5
TIM_TIM17_TI1_GPIO
TIM_TIM17_TI1_HSE_32
TIM_TIM17_TI1_LSE
TIM_TIM17_TI1_LSI
TIM_TIM17_TI1_MCO
TIM_TIM17_TI1_RTC_WK
TIM_TIM1_TI1_COMP1
TIM_TIM1_TI1_COMP2
TIM_TIM1_TI1_COMP3
TIM_TIM1_TI1_COMP4
TIM_TIM1_TI1_GPIO
TIM_TIM20_TI1_COMP1
TIM_TIM20_TI1_COMP2
TIM_TIM20_TI1_COMP3
TIM_TIM20_TI1_COMP4
TIM_TIM20_TI1_GPIO
TIM_TIM2_TI1_COMP1
TIM_TIM2_TI1_COMP2
TIM_TIM2_TI1_COMP3
TIM_TIM2_TI1_COMP4
TIM_TIM2_TI1_COMP5
TIM_TIM2_TI1_GPIO
TIM_TIM2_TI2_COMP1
TIM_TIM2_TI2_COMP2
TIM_TIM2_TI2_COMP3
TIM_TIM2_TI2_COMP4
TIM_TIM2_TI2_COMP6
TIM_TIM2_TI2_GPIO
TIM_TIM2_TI3_COMP4
TIM_TIM2_TI3_GPIO
TIM_TIM2_TI4_COMP1
TIM_TIM2_TI4_COMP2
TIM_TIM2_TI4_GPIO
TIM_TIM3_TI1_COMP1
TIM_TIM3_TI1_COMP2
TIM_TIM3_TI1_COMP3
TIM_TIM3_TI1_COMP4
TIM_TIM3_TI1_COMP5
TIM_TIM3_TI1_COMP6
TIM_TIM3_TI1_COMP7
TIM_TIM3_TI1_GPIO
TIM_TIM3_TI2_COMP1
TIM_TIM3_TI2_COMP2
TIM_TIM3_TI2_COMP3
TIM_TIM3_TI2_COMP4
TIM_TIM3_TI2_COMP5
TIM_TIM3_TI2_COMP6
TIM_TIM3_TI2_COMP7
TIM_TIM3_TI2_GPIO
TIM_TIM3_TI3_COMP3
TIM_TIM3_TI3_GPIO
TIM_TIM4_TI1_COMP1
TIM_TIM4_TI1_COMP2
TIM_TIM4_TI1_COMP3
TIM_TIM4_TI1_COMP4
TIM_TIM4_TI1_COMP5
TIM_TIM4_TI1_COMP6
TIM_TIM4_TI1_COMP7
TIM_TIM4_TI1_GPIO
TIM_TIM4_TI2_COMP1
TIM_TIM4_TI2_COMP2
TIM_TIM4_TI2_COMP3
TIM_TIM4_TI2_COMP4
TIM_TIM4_TI2_COMP5
TIM_TIM4_TI2_COMP6
TIM_TIM4_TI2_COMP7
TIM_TIM4_TI2_GPIO
TIM_TIM4_TI3_COMP5
TIM_TIM4_TI3_GPIO
TIM_TIM4_TI4_COMP6
TIM_TIM4_TI4_GPIO
TIM_TIM5_TI1_COMP1
TIM_TIM5_TI1_COMP2
TIM_TIM5_TI1_COMP3
TIM_TIM5_TI1_COMP4
TIM_TIM5_TI1_COMP5
TIM_TIM5_TI1_COMP6
TIM_TIM5_TI1_COMP7
TIM_TIM5_TI1_GPIO
TIM_TIM5_TI1_LSE
TIM_TIM5_TI1_LSI
TIM_TIM5_TI1_RTC_WK
TIM_TIM5_TI2_COMP1
TIM_TIM5_TI2_COMP2
TIM_TIM5_TI2_COMP3
TIM_TIM5_TI2_COMP4
TIM_TIM5_TI2_COMP5
TIM_TIM5_TI2_COMP6
TIM_TIM5_TI2_COMP7
TIM_TIM5_TI2_GPIO
TIM_TIM8_TI1_COMP1
TIM_TIM8_TI1_COMP2
TIM_TIM8_TI1_COMP3
TIM_TIM8_TI1_COMP4
TIM_TIM8_TI1_GPIO
TIM Extended Bitfield SMS preload enabling
TIM_SMS_PRELOAD_SOURCE_UPDATE
TIM Extended Encoder index position
TIM_ENCODERINDEX_POSITION_00
TIM_ENCODERINDEX_POSITION_01
TIM_ENCODERINDEX_POSITION_1
TIM_ENCODERINDEX_POSITION_10
TIM_ENCODERINDEX_POSITION_11
TIM Extended Encoder index direction
TIM_ENCODERINDEX_DIRECTION_UP
TIM_ENCODERINDEX_DIRECTION_UP_DOWN
TIM Extended Encoder index polarity
TIM_ENCODERINDEX_POLARITY_NONINVERTED
TIM Extended Encodder index prescaler
TIM_ENCODERINDEX_PRESCALER_DIV2
TIM_ENCODERINDEX_PRESCALER_DIV4
TIM_ENCODERINDEX_PRESCALER_DIV8
TIM Extended Exported Macros
__HAL_TIM_CALC_PERIOD_BY_DELAY
__HAL_TIM_CALC_PERIOD_DITHER
__HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY
__HAL_TIM_CALC_PSC
__HAL_TIM_CALC_PULSE
__HAL_TIM_CALC_PULSE_DITHER
TIM Extended Private Macros
IS_TIM_BREAKINPUTSOURCE
IS_TIM_BREAKINPUTSOURCE_POLARITY
IS_TIM_BREAKINPUTSOURCE_STATE
IS_TIM_CLOCKSOURCE_INSTANCE
IS_TIM_ENCODERINDEX_DIRECTION
IS_TIM_ENCODERINDEX_FILTER
IS_TIM_ENCODERINDEX_POLARITY
IS_TIM_ENCODERINDEX_POSITION
IS_TIM_ENCODERINDEX_PRESCALER
IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE
IS_TIM_OC_CHANNEL_MODE
IS_TIM_PULSEONCOMPARE_CHANNEL
IS_TIM_PULSEONCOMPARE_INSTANCE
IS_TIM_PULSEONCOMPARE_WIDTH
IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER
IS_TIM_REMAP
IS_TIM_SLAVE_PRELOAD_SOURCE
IS_TIM_TISEL
IS_TIM_TISEL_TIX_INSTANCE
IS_TIM_TRIGGER_INSTANCE
UART
LPUART_BRR_MIN
UART_BRR_MAX
UART_BRR_MIN
USART_CR1_FIELDS
USART_CR3_FIELDS
UART Exported Functions
HAL_LIN_Init
HAL_MultiProcessor_Init
HAL_UART_DeInit
HAL_UART_Init
HAL_UART_MspDeInit
HAL_UART_MspInit
HAL_UART_RegisterCallback
HAL_UART_RegisterRxEventCallback
HAL_UART_UnRegisterCallback
HAL_UART_UnRegisterRxEventCallback
IO operation functions
HAL_UART_Abort_IT
HAL_UART_AbortCpltCallback
HAL_UART_AbortReceive
HAL_UART_AbortReceive_IT
HAL_UART_AbortReceiveCpltCallback
HAL_UART_AbortTransmit
HAL_UART_AbortTransmit_IT
HAL_UART_AbortTransmitCpltCallback
HAL_UART_DMAPause
HAL_UART_DMAResume
HAL_UART_DMAStop
HAL_UART_ErrorCallback
HAL_UART_IRQHandler
HAL_UART_Receive
HAL_UART_Receive_DMA
HAL_UART_Receive_IT
HAL_UART_RxCpltCallback
HAL_UART_RxHalfCpltCallback
HAL_UART_Transmit
HAL_UART_Transmit_DMA
HAL_UART_Transmit_IT
HAL_UART_TxCpltCallback
HAL_UART_TxHalfCpltCallback
HAL_UARTEx_RxEventCallback
Peripheral Control functions
HAL_HalfDuplex_EnableTransmitter
HAL_LIN_SendBreak
HAL_MultiProcessor_DisableMuteMode
HAL_MultiProcessor_EnableMuteMode
HAL_MultiProcessor_EnterMuteMode
HAL_UART_DisableReceiverTimeout
HAL_UART_EnableReceiverTimeout
HAL_UART_ReceiverTimeout_Config
Peripheral State and Error functions
HAL_UART_GetState
UART Private Functions
UART_CheckIdleState
UART_DMAAbortOnError
UART_DMAError
UART_DMAReceiveCplt
UART_DMARxAbortCallback
UART_DMARxHalfCplt
UART_DMARxOnlyAbortCallback
UART_DMATransmitCplt
UART_DMATxAbortCallback
UART_DMATxHalfCplt
UART_DMATxOnlyAbortCallback
UART_EndRxTransfer
UART_EndTransmit_IT
UART_EndTxTransfer
UART_InitCallbacksToDefault
UART_RxISR_16BIT
UART_RxISR_16BIT_FIFOEN
UART_RxISR_8BIT
UART_RxISR_8BIT_FIFOEN
UART_SetConfig
UART_Start_Receive_DMA
UART_Start_Receive_IT
UART_TxISR_16BIT
UART_TxISR_16BIT_FIFOEN
UART_TxISR_8BIT
UART_TxISR_8BIT_FIFOEN
UART_WaitOnFlagUntilTimeout
UART Exported Types
HAL_UART_RxTypeTypeDef
HAL_UART_StateTypeDef
pUART_CallbackTypeDef
pUART_RxEventCallbackTypeDef
UART_HandleTypeDef
Enumerations
UART_ClockSourceTypeDef
Data Structures
UART_AdvFeatureInitTypeDef
__UART_HandleTypeDef
UART Exported Constants
HAL_UART_STATE_BUSY_RX
HAL_UART_STATE_BUSY_TX
HAL_UART_STATE_BUSY_TX_RX
HAL_UART_STATE_ERROR
HAL_UART_STATE_READY
HAL_UART_STATE_RESET
HAL_UART_STATE_TIMEOUT
UART Error Definition
HAL_UART_ERROR_FE
HAL_UART_ERROR_INVALID_CALLBACK
HAL_UART_ERROR_NE
HAL_UART_ERROR_NONE
HAL_UART_ERROR_ORE
HAL_UART_ERROR_PE
HAL_UART_ERROR_RTO
UART Number of Stop Bits
UART_STOPBITS_1
UART_STOPBITS_1_5
UART_STOPBITS_2
UART Parity
UART_PARITY_NONE
UART_PARITY_ODD
UART Hardware Flow Control
UART_HWCONTROL_NONE
UART_HWCONTROL_RTS
UART_HWCONTROL_RTS_CTS
UART Transfer Mode
UART_MODE_TX
UART_MODE_TX_RX
UART State
UART_STATE_ENABLE
UART Over Sampling
UART_OVERSAMPLING_8
UART One Bit Sampling Method
UART_ONE_BIT_SAMPLE_ENABLE
UART Clock Prescaler
UART_PRESCALER_DIV10
UART_PRESCALER_DIV12
UART_PRESCALER_DIV128
UART_PRESCALER_DIV16
UART_PRESCALER_DIV2
UART_PRESCALER_DIV256
UART_PRESCALER_DIV32
UART_PRESCALER_DIV4
UART_PRESCALER_DIV6
UART_PRESCALER_DIV64
UART_PRESCALER_DIV8
UART Advanced Feature AutoBaud Rate Mode
UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME
UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE
UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT
UART Receiver Timeout
UART_RECEIVER_TIMEOUT_ENABLE
UART Local Interconnection Network mode
UART_LIN_ENABLE
UART LIN Break Detection
UART_LINBREAKDETECTLENGTH_11B
UART DMA Tx
UART_DMA_TX_ENABLE
UART DMA Rx
UART_DMA_RX_ENABLE
UART Half Duplex Selection
UART_HALF_DUPLEX_ENABLE
UART WakeUp Methods
UART_WAKEUPMETHOD_IDLELINE
UART Request Parameters
UART_MUTE_MODE_REQUEST
UART_RXDATA_FLUSH_REQUEST
UART_SENDBREAK_REQUEST
UART_TXDATA_FLUSH_REQUEST
UART Advanced Feature Initialization Type
UART_ADVFEATURE_DATAINVERT_INIT
UART_ADVFEATURE_DMADISABLEONERROR_INIT
UART_ADVFEATURE_MSBFIRST_INIT
UART_ADVFEATURE_NO_INIT
UART_ADVFEATURE_RXINVERT_INIT
UART_ADVFEATURE_RXOVERRUNDISABLE_INIT
UART_ADVFEATURE_SWAP_INIT
UART_ADVFEATURE_TXINVERT_INIT
UART Advanced Feature TX Pin Active Level Inversion
UART_ADVFEATURE_TXINV_ENABLE
UART Advanced Feature RX Pin Active Level Inversion
UART_ADVFEATURE_RXINV_ENABLE
UART Advanced Feature Binary Data Inversion
UART_ADVFEATURE_DATAINV_ENABLE
UART Advanced Feature RX TX Pins Swap
UART_ADVFEATURE_SWAP_ENABLE
UART Advanced Feature Overrun Disable
UART_ADVFEATURE_OVERRUN_ENABLE
UART Advanced Feature Auto BaudRate Enable
UART_ADVFEATURE_AUTOBAUDRATE_ENABLE
UART Advanced Feature DMA Disable On Rx Error
UART_ADVFEATURE_DMA_ENABLEONRXERROR
UART Advanced Feature MSB First
UART_ADVFEATURE_MSBFIRST_ENABLE
UART Advanced Feature Stop Mode Enable
UART_ADVFEATURE_STOPMODE_ENABLE
UART Advanced Feature Mute Mode Enable
UART_ADVFEATURE_MUTEMODE_ENABLE
UART Address-matching LSB Position In CR2 Register
UART WakeUp From Stop Selection
UART_WAKEUP_ON_READDATA_NONEMPTY
UART_WAKEUP_ON_STARTBIT
UART DriverEnable Polarity
UART_DE_POLARITY_LOW
UART Driver Enable Assertion Time LSB Position In CR1 Register
UART Driver Enable DeAssertion Time LSB Position In CR1 Register
UART Interruptions Flag Mask
UART polling-based communications time-out value
UART Status Flags
UART_FLAG_ABRF
UART_FLAG_BUSY
UART_FLAG_CMF
UART_FLAG_CTS
UART_FLAG_CTSIF
UART_FLAG_FE
UART_FLAG_IDLE
UART_FLAG_LBDF
UART_FLAG_NE
UART_FLAG_ORE
UART_FLAG_PE
UART_FLAG_REACK
UART_FLAG_RTOF
UART_FLAG_RWU
UART_FLAG_RXFF
UART_FLAG_RXFNE
UART_FLAG_RXFT
UART_FLAG_RXNE
UART_FLAG_SBKF
UART_FLAG_TC
UART_FLAG_TEACK
UART_FLAG_TXE
UART_FLAG_TXFE
UART_FLAG_TXFNF
UART_FLAG_TXFT
UART_FLAG_WUF
UART Interrupts Definition
UART_IT_CTS
UART_IT_ERR
UART_IT_FE
UART_IT_IDLE
UART_IT_LBD
UART_IT_NE
UART_IT_ORE
UART_IT_PE
UART_IT_RTO
UART_IT_RXFF
UART_IT_RXFNE
UART_IT_RXFT
UART_IT_RXNE
UART_IT_TC
UART_IT_TXE
UART_IT_TXFE
UART_IT_TXFNF
UART_IT_TXFT
UART_IT_WUF
UART Interruption Clear Flags
UART_CLEAR_CTSF
UART_CLEAR_FEF
UART_CLEAR_IDLEF
UART_CLEAR_LBDF
UART_CLEAR_NEF
UART_CLEAR_OREF
UART_CLEAR_PEF
UART_CLEAR_RTOF
UART_CLEAR_TCF
UART_CLEAR_TXFECF
UART_CLEAR_WUF
UART Reception type values
HAL_UART_RECEPTION_TOCHARMATCH
HAL_UART_RECEPTION_TOIDLE
HAL_UART_RECEPTION_TORTO
UART RxEvent type values
HAL_UART_RXEVENT_IDLE
HAL_UART_RXEVENT_TC
UART Exported Macros
__HAL_UART_CLEAR_FLAG
__HAL_UART_CLEAR_IDLEFLAG
__HAL_UART_CLEAR_IT
__HAL_UART_CLEAR_NEFLAG
__HAL_UART_CLEAR_OREFLAG
__HAL_UART_CLEAR_PEFLAG
__HAL_UART_CLEAR_TXFECF
__HAL_UART_DISABLE
__HAL_UART_DISABLE_IT
__HAL_UART_ENABLE
__HAL_UART_ENABLE_IT
__HAL_UART_FLUSH_DRREGISTER
__HAL_UART_GET_FLAG
__HAL_UART_GET_IT
__HAL_UART_GET_IT_SOURCE
__HAL_UART_HWCONTROL_CTS_DISABLE
__HAL_UART_HWCONTROL_CTS_ENABLE
__HAL_UART_HWCONTROL_RTS_DISABLE
__HAL_UART_HWCONTROL_RTS_ENABLE
__HAL_UART_ONE_BIT_SAMPLE_DISABLE
__HAL_UART_ONE_BIT_SAMPLE_ENABLE
__HAL_UART_RESET_HANDLE_STATE
__HAL_UART_SEND_REQ
UART Private Macros
IS_UART_ADVFEATURE_AUTOBAUDRATE
IS_UART_ADVFEATURE_AUTOBAUDRATEMODE
IS_UART_ADVFEATURE_DATAINV
IS_UART_ADVFEATURE_DMAONRXERROR
IS_UART_ADVFEATURE_INIT
IS_UART_ADVFEATURE_MSBFIRST
IS_UART_ADVFEATURE_RXINV
IS_UART_ADVFEATURE_STOPMODE
IS_UART_ADVFEATURE_SWAP
IS_UART_ADVFEATURE_TXINV
IS_UART_ASSERTIONTIME
IS_UART_BAUDRATE
IS_UART_DE_POLARITY
IS_UART_DEASSERTIONTIME
IS_UART_DMA_RX
IS_UART_DMA_TX
IS_UART_HALF_DUPLEX
IS_UART_HARDWARE_FLOW_CONTROL
IS_UART_LIN
IS_UART_LIN_BREAK_DETECT_LENGTH
IS_UART_MODE
IS_UART_MUTE_MODE
IS_UART_ONE_BIT_SAMPLE
IS_UART_OVERRUN
IS_UART_OVERSAMPLING
IS_UART_PARITY
IS_UART_PRESCALER
IS_UART_RECEIVER_TIMEOUT
IS_UART_RECEIVER_TIMEOUT_VALUE
IS_UART_REQUEST_PARAMETER
IS_UART_STATE
IS_UART_STOPBITS
IS_UART_WAKEUP_SELECTION
IS_UART_WAKEUPMETHOD
UART_DIV_LPUART
UART_DIV_SAMPLING16
UART_DIV_SAMPLING8
UART_GET_DIV_FACTOR
UART_INSTANCE_LOWPOWER
UART Private variables
UARTPrescTable
UARTEx
TX_FIFO_DEPTH
UARTEx Private Functions
UARTEx_Wakeup_AddressConfig
UARTEx Exported Functions
IO operation functions
HAL_UARTEx_TxFifoEmptyCallback
HAL_UARTEx_WakeupCallback
Peripheral Control functions
HAL_UARTEx_DisableFifoMode
HAL_UARTEx_DisableStopMode
HAL_UARTEx_EnableFifoMode
HAL_UARTEx_EnableStopMode
HAL_UARTEx_GetRxEventType
HAL_UARTEx_ReceiveToIdle
HAL_UARTEx_ReceiveToIdle_DMA
HAL_UARTEx_ReceiveToIdle_IT
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_StopModeWakeUpSourceConfig
UARTEx Exported Types
UARTEx Exported Constants
UART_WORDLENGTH_8B
UART_WORDLENGTH_9B
UARTEx WakeUp Address Length
UART_ADDRESS_DETECT_7B
UARTEx FIFO mode
UART_FIFOMODE_ENABLE
UARTEx TXFIFO threshold level
UART_TXFIFO_THRESHOLD_1_4
UART_TXFIFO_THRESHOLD_1_8
UART_TXFIFO_THRESHOLD_3_4
UART_TXFIFO_THRESHOLD_7_8
UART_TXFIFO_THRESHOLD_8_8
UARTEx RXFIFO threshold level
UART_RXFIFO_THRESHOLD_1_4
UART_RXFIFO_THRESHOLD_1_8
UART_RXFIFO_THRESHOLD_3_4
UART_RXFIFO_THRESHOLD_7_8
UART_RXFIFO_THRESHOLD_8_8
UARTEx Private Macros
IS_UART_RXFIFO_THRESHOLD
IS_UART_TXFIFO_THRESHOLD
IS_UART_WORD_LENGTH
UART_GETCLOCKSOURCE
UART_MASK_COMPUTATION
USART
USART_BRR_MIN
USART_CR1_FIELDS
USART_CR2_FIELDS
USART_CR3_FIELDS
USART_DUMMY_DATA
USART_TEACK_REACK_TIMEOUT
USART Exported Functions
HAL_USART_Init
HAL_USART_MspDeInit
HAL_USART_MspInit
HAL_USART_RegisterCallback
HAL_USART_UnRegisterCallback
IO operation functions
HAL_USART_Abort_IT
HAL_USART_AbortCpltCallback
HAL_USART_DMAPause
HAL_USART_DMAResume
HAL_USART_DMAStop
HAL_USART_ErrorCallback
HAL_USART_IRQHandler
HAL_USART_Receive
HAL_USART_Receive_DMA
HAL_USART_Receive_IT
HAL_USART_RxCpltCallback
HAL_USART_RxHalfCpltCallback
HAL_USART_Transmit
HAL_USART_Transmit_DMA
HAL_USART_Transmit_IT
HAL_USART_TransmitReceive
HAL_USART_TransmitReceive_DMA
HAL_USART_TransmitReceive_IT
HAL_USART_TxCpltCallback
HAL_USART_TxHalfCpltCallback
HAL_USART_TxRxCpltCallback
Peripheral State and Error functions
HAL_USART_GetState
USART Private Functions
USART_DMAAbortOnError
USART_DMAError
USART_DMAReceiveCplt
USART_DMARxAbortCallback
USART_DMARxHalfCplt
USART_DMATransmitCplt
USART_DMATxAbortCallback
USART_DMATxHalfCplt
USART_EndTransfer
USART_EndTransmit_IT
USART_InitCallbacksToDefault
USART_RxISR_16BIT
USART_RxISR_16BIT_FIFOEN
USART_RxISR_8BIT
USART_RxISR_8BIT_FIFOEN
USART_SetConfig
USART_TxISR_16BIT
USART_TxISR_16BIT_FIFOEN
USART_TxISR_8BIT
USART_TxISR_8BIT_FIFOEN
USART_WaitOnFlagUntilTimeout
USART Exported Types
USART_HandleTypeDef
Enumerations
HAL_USART_StateTypeDef
USART_ClockSourceTypeDef
Data Structures
__USART_HandleTypeDef
USART Exported Constants
HAL_USART_ERROR_FE
HAL_USART_ERROR_INVALID_CALLBACK
HAL_USART_ERROR_NE
HAL_USART_ERROR_NONE
HAL_USART_ERROR_ORE
HAL_USART_ERROR_PE
HAL_USART_ERROR_RTO
HAL_USART_ERROR_UDR
USART Number of Stop Bits
USART_STOPBITS_1
USART_STOPBITS_1_5
USART_STOPBITS_2
USART Parity
USART_PARITY_NONE
USART_PARITY_ODD
USART Mode
USART_MODE_TX
USART_MODE_TX_RX
USART Clock
USART_CLOCK_ENABLE
USART Clock Polarity
USART_POLARITY_LOW
USART Clock Phase
USART_PHASE_2EDGE
USART Last Bit
USART_LASTBIT_ENABLE
USART Clock Prescaler
USART_PRESCALER_DIV10
USART_PRESCALER_DIV12
USART_PRESCALER_DIV128
USART_PRESCALER_DIV16
USART_PRESCALER_DIV2
USART_PRESCALER_DIV256
USART_PRESCALER_DIV32
USART_PRESCALER_DIV4
USART_PRESCALER_DIV6
USART_PRESCALER_DIV64
USART_PRESCALER_DIV8
USART Request Parameters
USART_TXDATA_FLUSH_REQUEST
USART Flags
USART_FLAG_FE
USART_FLAG_IDLE
USART_FLAG_NE
USART_FLAG_ORE
USART_FLAG_PE
USART_FLAG_REACK
USART_FLAG_RTOF
USART_FLAG_RXFF
USART_FLAG_RXFNE
USART_FLAG_RXFT
USART_FLAG_RXNE
USART_FLAG_TC
USART_FLAG_TEACK
USART_FLAG_TXE
USART_FLAG_TXFE
USART_FLAG_TXFNF
USART_FLAG_TXFT
USART_FLAG_UDR
USART Interrupts Definition
USART_IT_FE
USART_IT_IDLE
USART_IT_NE
USART_IT_ORE
USART_IT_PE
USART_IT_RXFF
USART_IT_RXFNE
USART_IT_RXFT
USART_IT_RXNE
USART_IT_TC
USART_IT_TXE
USART_IT_TXFE
USART_IT_TXFNF
USART_IT_TXFT
USART Interruption Clear Flags
USART_CLEAR_IDLEF
USART_CLEAR_NEF
USART_CLEAR_OREF
USART_CLEAR_PEF
USART_CLEAR_RTOF
USART_CLEAR_TCF
USART_CLEAR_TXFECF
USART_CLEAR_UDRF
USART Interruption Flags Mask
USART_CR_POS
USART_ISR_MASK
USART_ISR_POS
USART_IT_MASK
USART Exported Macros
__HAL_USART_CLEAR_FLAG
__HAL_USART_CLEAR_IDLEFLAG
__HAL_USART_CLEAR_IT
__HAL_USART_CLEAR_NEFLAG
__HAL_USART_CLEAR_OREFLAG
__HAL_USART_CLEAR_PEFLAG
__HAL_USART_CLEAR_TXFECF
__HAL_USART_CLEAR_UDRFLAG
__HAL_USART_DISABLE
__HAL_USART_DISABLE_IT
__HAL_USART_ENABLE
__HAL_USART_ENABLE_IT
__HAL_USART_GET_FLAG
__HAL_USART_GET_IT
__HAL_USART_GET_IT_SOURCE
__HAL_USART_ONE_BIT_SAMPLE_DISABLE
__HAL_USART_ONE_BIT_SAMPLE_ENABLE
__HAL_USART_RESET_HANDLE_STATE
__HAL_USART_SEND_REQ
USART Private Macros
IS_USART_CLOCK
IS_USART_LASTBIT
IS_USART_MODE
IS_USART_PARITY
IS_USART_PHASE
IS_USART_POLARITY
IS_USART_PRESCALER
IS_USART_REQUEST_PARAMETER
IS_USART_STOPBITS
USART_DIV_SAMPLING8
USART_GET_DIV_FACTOR
USART_GETCLOCKSOURCE
USARTEx
TX_FIFO_DEPTH
USARTEx Private Functions
USARTEx Exported Functions
HAL_USARTEx_TxFifoEmptyCallback
Peripheral Control functions
HAL_USARTEx_DisableFifoMode
HAL_USARTEx_DisableSlaveMode
HAL_USARTEx_EnableFifoMode
HAL_USARTEx_EnableSlaveMode
HAL_USARTEx_SetRxFifoThreshold
HAL_USARTEx_SetTxFifoThreshold
USARTEx Exported Constants
USART_WORDLENGTH_8B
USART_WORDLENGTH_9B
USARTEx Slave Select Management
USART_NSS_SOFT
USARTEx Synchronous Slave mode enable
USART_SLAVEMODE_ENABLE
USARTEx FIFO mode
USART_FIFOMODE_ENABLE
USARTEx TXFIFO threshold level
USART_TXFIFO_THRESHOLD_1_4
USART_TXFIFO_THRESHOLD_1_8
USART_TXFIFO_THRESHOLD_3_4
USART_TXFIFO_THRESHOLD_7_8
USART_TXFIFO_THRESHOLD_8_8
USARTEx RXFIFO threshold level
USART_RXFIFO_THRESHOLD_1_4
USART_RXFIFO_THRESHOLD_1_8
USART_RXFIFO_THRESHOLD_3_4
USART_RXFIFO_THRESHOLD_7_8
USART_RXFIFO_THRESHOLD_8_8
USARTEx Private Macros
IS_USART_NSS
IS_USART_RXFIFO_THRESHOLD
IS_USART_SLAVEMODE
IS_USART_TXFIFO_THRESHOLD
IS_USART_WORD_LENGTH
USART_MASK_COMPUTATION
WWDG
HAL_WWDG_MspInit
HAL_WWDG_RegisterCallback
HAL_WWDG_UnRegisterCallback
IO operation functions
HAL_WWDG_IRQHandler
HAL_WWDG_Refresh
WWDG Exported Types
WWDG_HandleTypeDef
Enumerations
Data Structures
__WWDG_HandleTypeDef
WWDG Exported Constants
WWDG Flag definition
WWDG Prescaler
WWDG_PRESCALER_128
WWDG_PRESCALER_16
WWDG_PRESCALER_2
WWDG_PRESCALER_32
WWDG_PRESCALER_4
WWDG_PRESCALER_64
WWDG_PRESCALER_8
WWDG Early Wakeup Interrupt Mode
WWDG_EWI_ENABLE
WWDG Private Macros
IS_WWDG_EWI_MODE
IS_WWDG_PRESCALER
IS_WWDG_WINDOW
WWDG Exported Macros
__HAL_WWDG_CLEAR_IT
__HAL_WWDG_ENABLE
__HAL_WWDG_ENABLE_IT
__HAL_WWDG_GET_FLAG
__HAL_WWDG_GET_IT
__HAL_WWDG_GET_IT_SOURCE
CRYP
CRYPEx
OPAMPEx
STM32G4xx_LL_Driver
ADC_AWD_CR12_REGOFFSETGAP_VAL
ADC_AWD_CR1_CHANNEL_MASK
ADC_AWD_CR1_REGOFFSET
ADC_AWD_CR23_CHANNEL_MASK
ADC_AWD_CR2_REGOFFSET
ADC_AWD_CR3_REGOFFSET
ADC_AWD_CR_ALL_CHANNEL_MASK
ADC_AWD_CRX_REGOFFSET_MASK
ADC_AWD_CRX_REGOFFSET_POS
ADC_AWD_TR1_REGOFFSET
ADC_AWD_TR2_REGOFFSET
ADC_AWD_TR3_REGOFFSET
ADC_AWD_TRX_BIT_HIGH_MASK
ADC_AWD_TRX_BIT_HIGH_POS
ADC_AWD_TRX_BIT_HIGH_SHIFT4
ADC_AWD_TRX_REGOFFSET_MASK
ADC_AWD_TRX_REGOFFSET_POS
ADC_CFGR_AWD1EN_BITOFFSET_POS
ADC_CFGR_AWD1SGL_BITOFFSET_POS
ADC_CFGR_JAWD1EN_BITOFFSET_POS
ADC_CFGR_RES_BITOFFSET_POS
ADC_CHANNEL_0_BITFIELD
ADC_CHANNEL_0_NUMBER
ADC_CHANNEL_0_SMP
ADC_CHANNEL_10_BITFIELD
ADC_CHANNEL_10_NUMBER
ADC_CHANNEL_10_SMP
ADC_CHANNEL_11_BITFIELD
ADC_CHANNEL_11_NUMBER
ADC_CHANNEL_11_SMP
ADC_CHANNEL_12_BITFIELD
ADC_CHANNEL_12_NUMBER
ADC_CHANNEL_12_SMP
ADC_CHANNEL_13_BITFIELD
ADC_CHANNEL_13_NUMBER
ADC_CHANNEL_13_SMP
ADC_CHANNEL_14_BITFIELD
ADC_CHANNEL_14_NUMBER
ADC_CHANNEL_14_SMP
ADC_CHANNEL_15_BITFIELD
ADC_CHANNEL_15_NUMBER
ADC_CHANNEL_15_SMP
ADC_CHANNEL_16_BITFIELD
ADC_CHANNEL_16_NUMBER
ADC_CHANNEL_16_SMP
ADC_CHANNEL_17_BITFIELD
ADC_CHANNEL_17_NUMBER
ADC_CHANNEL_17_SMP
ADC_CHANNEL_18_BITFIELD
ADC_CHANNEL_18_NUMBER
ADC_CHANNEL_18_SMP
ADC_CHANNEL_1_BITFIELD
ADC_CHANNEL_1_NUMBER
ADC_CHANNEL_1_SMP
ADC_CHANNEL_2_BITFIELD
ADC_CHANNEL_2_NUMBER
ADC_CHANNEL_2_SMP
ADC_CHANNEL_3_BITFIELD
ADC_CHANNEL_3_NUMBER
ADC_CHANNEL_3_SMP
ADC_CHANNEL_4_BITFIELD
ADC_CHANNEL_4_NUMBER
ADC_CHANNEL_4_SMP
ADC_CHANNEL_5_BITFIELD
ADC_CHANNEL_5_NUMBER
ADC_CHANNEL_5_SMP
ADC_CHANNEL_6_BITFIELD
ADC_CHANNEL_6_NUMBER
ADC_CHANNEL_6_SMP
ADC_CHANNEL_7_BITFIELD
ADC_CHANNEL_7_NUMBER
ADC_CHANNEL_7_SMP
ADC_CHANNEL_8_BITFIELD
ADC_CHANNEL_8_NUMBER
ADC_CHANNEL_8_SMP
ADC_CHANNEL_9_BITFIELD
ADC_CHANNEL_9_NUMBER
ADC_CHANNEL_9_SMP
ADC_CHANNEL_ID_BITFIELD_MASK
ADC_CHANNEL_ID_INTERNAL_CH
ADC_CHANNEL_ID_INTERNAL_CH_2
ADC_CHANNEL_ID_INTERNAL_CH_MASK
ADC_CHANNEL_ID_MASK
ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
ADC_CHANNEL_ID_NUMBER_MASK
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
ADC_CHANNEL_SMPRX_REGOFFSET_MASK
ADC_CHANNEL_SMPx_BITOFFSET_MASK
ADC_CHANNEL_SMPx_BITOFFSET_POS
ADC_CLOCK_RATIO_VS_CPU_HIGHEST
ADC_CR_BITS_PROPERTY_RS
ADC_INJ_JDRX_REGOFFSET_MASK
ADC_INJ_RANK_1_JSQR_BITOFFSET_POS
ADC_INJ_RANK_2_JSQR_BITOFFSET_POS
ADC_INJ_RANK_3_JSQR_BITOFFSET_POS
ADC_INJ_RANK_4_JSQR_BITOFFSET_POS
ADC_INJ_RANK_ID_JSQR_MASK
ADC_INJ_TRIG_EDGE_MASK
ADC_INJ_TRIG_EXT_EDGE_DEFAULT
ADC_INJ_TRIG_EXTEN_BITOFFSET_POS
ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS
ADC_INJ_TRIG_SOURCE_MASK
ADC_JDR1_REGOFFSET
ADC_JDR2_REGOFFSET
ADC_JDR3_REGOFFSET
ADC_JDR4_REGOFFSET
ADC_JDRX_REGOFFSET_POS
ADC_OFR1_REGOFFSET
ADC_OFR2_REGOFFSET
ADC_OFR3_REGOFFSET
ADC_OFR4_REGOFFSET
ADC_OFRx_REGOFFSET_MASK
ADC_REG_RANK_10_SQRX_BITOFFSET_POS
ADC_REG_RANK_11_SQRX_BITOFFSET_POS
ADC_REG_RANK_12_SQRX_BITOFFSET_POS
ADC_REG_RANK_13_SQRX_BITOFFSET_POS
ADC_REG_RANK_14_SQRX_BITOFFSET_POS
ADC_REG_RANK_15_SQRX_BITOFFSET_POS
ADC_REG_RANK_16_SQRX_BITOFFSET_POS
ADC_REG_RANK_1_SQRX_BITOFFSET_POS
ADC_REG_RANK_2_SQRX_BITOFFSET_POS
ADC_REG_RANK_3_SQRX_BITOFFSET_POS
ADC_REG_RANK_4_SQRX_BITOFFSET_POS
ADC_REG_RANK_5_SQRX_BITOFFSET_POS
ADC_REG_RANK_6_SQRX_BITOFFSET_POS
ADC_REG_RANK_7_SQRX_BITOFFSET_POS
ADC_REG_RANK_8_SQRX_BITOFFSET_POS
ADC_REG_RANK_9_SQRX_BITOFFSET_POS
ADC_REG_RANK_ID_SQRX_MASK
ADC_REG_SQRX_REGOFFSET_MASK
ADC_REG_TRIG_EDGE_MASK
ADC_REG_TRIG_EXT_EDGE_DEFAULT
ADC_REG_TRIG_EXTEN_BITOFFSET_POS
ADC_REG_TRIG_EXTSEL_BITOFFSET_POS
ADC_REG_TRIG_SOURCE_MASK
ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK
ADC_SINGLEDIFF_CALIB_F_BIT_D_POS
ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4
ADC_SINGLEDIFF_CALIB_FACTOR_MASK
ADC_SINGLEDIFF_CALIB_START_MASK
ADC_SINGLEDIFF_CHANNEL_MASK
ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK
ADC_SMPR1_REGOFFSET
ADC_SMPR2_REGOFFSET
ADC_SMPRX_REGOFFSET_POS
ADC_SQR1_REGOFFSET
ADC_SQR2_REGOFFSET
ADC_SQR3_REGOFFSET
ADC_SQR4_REGOFFSET
ADC_SQRX_REGOFFSET_POS
ADC_TIMEOUT_DISABLE_CPU_CYCLES
ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES
ADC_TR1_HT1_BITOFFSET_POS
TEMPSENSOR_CAL1_ADDR
TEMPSENSOR_CAL1_TEMP
TEMPSENSOR_CAL2_ADDR
TEMPSENSOR_CAL2_TEMP
TEMPSENSOR_CAL_VREFANALOG
VREFINT_CAL_ADDR
VREFINT_CAL_VREF
ADC Private Macros
IS_LL_ADC_COMMON_CLOCK
IS_LL_ADC_DATA_ALIGN
IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE
IS_LL_ADC_INJ_SEQ_SCAN_LENGTH
IS_LL_ADC_INJ_TRIG_AUTO
IS_LL_ADC_INJ_TRIG_EXT_EDGE
IS_LL_ADC_INJ_TRIG_SOURCE
IS_LL_ADC_LOW_POWER
IS_LL_ADC_MULTI_DMA_TRANSFER
IS_LL_ADC_MULTI_MASTER_SLAVE
IS_LL_ADC_MULTI_MODE
IS_LL_ADC_MULTI_TWOSMP_DELAY
IS_LL_ADC_REG_CONTINUOUS_MODE
IS_LL_ADC_REG_DMA_TRANSFER
IS_LL_ADC_REG_OVR_DATA_BEHAVIOR
IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE
IS_LL_ADC_REG_SEQ_SCAN_LENGTH
IS_LL_ADC_REG_TRIG_SOURCE
IS_LL_ADC_RESOLUTION
ADC Exported Init structure
LL_ADC_InitTypeDef
LL_ADC_REG_InitTypeDef
LL_ADC_INJ_InitTypeDef
ADC Exported Constants
LL_ADC_FLAG_ADRDY_MST
LL_ADC_FLAG_ADRDY_SLV
LL_ADC_FLAG_AWD1
LL_ADC_FLAG_AWD1_MST
LL_ADC_FLAG_AWD1_SLV
LL_ADC_FLAG_AWD2
LL_ADC_FLAG_AWD2_MST
LL_ADC_FLAG_AWD2_SLV
LL_ADC_FLAG_AWD3
LL_ADC_FLAG_AWD3_MST
LL_ADC_FLAG_AWD3_SLV
LL_ADC_FLAG_EOC
LL_ADC_FLAG_EOC_MST
LL_ADC_FLAG_EOC_SLV
LL_ADC_FLAG_EOS
LL_ADC_FLAG_EOS_MST
LL_ADC_FLAG_EOS_SLV
LL_ADC_FLAG_EOSMP
LL_ADC_FLAG_EOSMP_MST
LL_ADC_FLAG_EOSMP_SLV
LL_ADC_FLAG_JEOC
LL_ADC_FLAG_JEOC_MST
LL_ADC_FLAG_JEOC_SLV
LL_ADC_FLAG_JEOS
LL_ADC_FLAG_JEOS_MST
LL_ADC_FLAG_JEOS_SLV
LL_ADC_FLAG_JQOVF
LL_ADC_FLAG_JQOVF_MST
LL_ADC_FLAG_JQOVF_SLV
LL_ADC_FLAG_OVR
LL_ADC_FLAG_OVR_MST
LL_ADC_FLAG_OVR_SLV
ADC interruptions for configuration (interruption enable or disable)
LL_ADC_IT_AWD1
LL_ADC_IT_AWD2
LL_ADC_IT_AWD3
LL_ADC_IT_EOC
LL_ADC_IT_EOS
LL_ADC_IT_EOSMP
LL_ADC_IT_JEOC
LL_ADC_IT_JEOS
LL_ADC_IT_JQOVF
LL_ADC_IT_OVR
ADC registers compliant with specific purpose
LL_ADC_DMA_REG_REGULAR_DATA_MULTI
ADC common - Clock source
LL_ADC_CLOCK_ASYNC_DIV10
LL_ADC_CLOCK_ASYNC_DIV12
LL_ADC_CLOCK_ASYNC_DIV128
LL_ADC_CLOCK_ASYNC_DIV16
LL_ADC_CLOCK_ASYNC_DIV2
LL_ADC_CLOCK_ASYNC_DIV256
LL_ADC_CLOCK_ASYNC_DIV32
LL_ADC_CLOCK_ASYNC_DIV4
LL_ADC_CLOCK_ASYNC_DIV6
LL_ADC_CLOCK_ASYNC_DIV64
LL_ADC_CLOCK_ASYNC_DIV8
LL_ADC_CLOCK_SYNC_PCLK_DIV1
LL_ADC_CLOCK_SYNC_PCLK_DIV2
LL_ADC_CLOCK_SYNC_PCLK_DIV4
ADC common - Measurement path to internal channels
LL_ADC_PATH_INTERNAL_TEMPSENSOR
LL_ADC_PATH_INTERNAL_VBAT
LL_ADC_PATH_INTERNAL_VREFINT
ADC instance - Resolution
LL_ADC_RESOLUTION_12B
LL_ADC_RESOLUTION_6B
LL_ADC_RESOLUTION_8B
ADC instance - Data alignment
LL_ADC_DATA_ALIGN_RIGHT
ADC instance - Low power mode
LL_ADC_LP_MODE_NONE
ADC instance - Offset instance
LL_ADC_OFFSET_2
LL_ADC_OFFSET_3
LL_ADC_OFFSET_4
ADC instance - Offset state
LL_ADC_OFFSET_ENABLE
ADC instance - Offset sign
LL_ADC_OFFSET_SIGN_POSITIVE
ADC instance - Offset saturation mode
LL_ADC_OFFSET_SATURATION_ENABLE
ADC instance - Groups
LL_ADC_GROUP_REGULAR
LL_ADC_GROUP_REGULAR_INJECTED
ADC instance - Channel number
LL_ADC_CHANNEL_1
LL_ADC_CHANNEL_10
LL_ADC_CHANNEL_11
LL_ADC_CHANNEL_12
LL_ADC_CHANNEL_13
LL_ADC_CHANNEL_14
LL_ADC_CHANNEL_15
LL_ADC_CHANNEL_16
LL_ADC_CHANNEL_17
LL_ADC_CHANNEL_18
LL_ADC_CHANNEL_2
LL_ADC_CHANNEL_3
LL_ADC_CHANNEL_4
LL_ADC_CHANNEL_5
LL_ADC_CHANNEL_6
LL_ADC_CHANNEL_7
LL_ADC_CHANNEL_8
LL_ADC_CHANNEL_9
LL_ADC_CHANNEL_TEMPSENSOR_ADC1
LL_ADC_CHANNEL_TEMPSENSOR_ADC5
LL_ADC_CHANNEL_VBAT
LL_ADC_CHANNEL_VOPAMP1
LL_ADC_CHANNEL_VOPAMP2
LL_ADC_CHANNEL_VOPAMP3_ADC2
LL_ADC_CHANNEL_VOPAMP3_ADC3
LL_ADC_CHANNEL_VOPAMP4
LL_ADC_CHANNEL_VOPAMP5
LL_ADC_CHANNEL_VOPAMP6
LL_ADC_CHANNEL_VREFINT
ADC group regular - Trigger source
LL_ADC_REG_TRIG_EXT_EXTI_LINE2
LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
LL_ADC_REG_TRIG_EXT_HRTIM_TRG2
LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
LL_ADC_REG_TRIG_EXT_HRTIM_TRG4
LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
LL_ADC_REG_TRIG_EXT_LPTIM_OUT
LL_ADC_REG_TRIG_EXT_TIM15_TRGO
LL_ADC_REG_TRIG_EXT_TIM1_CH1
LL_ADC_REG_TRIG_EXT_TIM1_CH2
LL_ADC_REG_TRIG_EXT_TIM1_CH3
LL_ADC_REG_TRIG_EXT_TIM1_TRGO
LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
LL_ADC_REG_TRIG_EXT_TIM20_CH1
LL_ADC_REG_TRIG_EXT_TIM20_CH2
LL_ADC_REG_TRIG_EXT_TIM20_CH3
LL_ADC_REG_TRIG_EXT_TIM20_TRGO
LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
LL_ADC_REG_TRIG_EXT_TIM2_CH1
LL_ADC_REG_TRIG_EXT_TIM2_CH2
LL_ADC_REG_TRIG_EXT_TIM2_CH3
LL_ADC_REG_TRIG_EXT_TIM2_TRGO
LL_ADC_REG_TRIG_EXT_TIM3_CH1
LL_ADC_REG_TRIG_EXT_TIM3_CH4
LL_ADC_REG_TRIG_EXT_TIM3_TRGO
LL_ADC_REG_TRIG_EXT_TIM4_CH1
LL_ADC_REG_TRIG_EXT_TIM4_CH4
LL_ADC_REG_TRIG_EXT_TIM4_TRGO
LL_ADC_REG_TRIG_EXT_TIM6_TRGO
LL_ADC_REG_TRIG_EXT_TIM7_TRGO
LL_ADC_REG_TRIG_EXT_TIM8_CH1
LL_ADC_REG_TRIG_EXT_TIM8_TRGO
LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
LL_ADC_REG_TRIG_SOFTWARE
ADC group regular - Trigger edge
LL_ADC_REG_TRIG_EXT_RISING
LL_ADC_REG_TRIG_EXT_RISINGFALLING
ADC group regular - Sampling mode
LL_ADC_REG_SAMPLING_MODE_NORMAL
LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
ADC group regular - Continuous mode
LL_ADC_REG_CONV_SINGLE
ADC group regular - DMA transfer of ADC conversion data
LL_ADC_REG_DMA_TRANSFER_NONE
LL_ADC_REG_DMA_TRANSFER_UNLIMITED
ADC instance - ADC sampling time common configuration
LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
ADC group regular - Overrun behavior on conversion data
LL_ADC_REG_OVR_DATA_PRESERVED
ADC group regular - Sequencer scan length
LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
ADC group regular - Sequencer discontinuous mode
LL_ADC_REG_SEQ_DISCONT_2RANKS
LL_ADC_REG_SEQ_DISCONT_3RANKS
LL_ADC_REG_SEQ_DISCONT_4RANKS
LL_ADC_REG_SEQ_DISCONT_5RANKS
LL_ADC_REG_SEQ_DISCONT_6RANKS
LL_ADC_REG_SEQ_DISCONT_7RANKS
LL_ADC_REG_SEQ_DISCONT_8RANKS
LL_ADC_REG_SEQ_DISCONT_DISABLE
ADC group regular - Sequencer ranks
LL_ADC_REG_RANK_10
LL_ADC_REG_RANK_11
LL_ADC_REG_RANK_12
LL_ADC_REG_RANK_13
LL_ADC_REG_RANK_14
LL_ADC_REG_RANK_15
LL_ADC_REG_RANK_16
LL_ADC_REG_RANK_2
LL_ADC_REG_RANK_3
LL_ADC_REG_RANK_4
LL_ADC_REG_RANK_5
LL_ADC_REG_RANK_6
LL_ADC_REG_RANK_7
LL_ADC_REG_RANK_8
LL_ADC_REG_RANK_9
ADC group injected - Trigger source
LL_ADC_INJ_TRIG_EXT_EXTI_LINE3
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
LL_ADC_INJ_TRIG_EXT_TIM16_CH1
LL_ADC_INJ_TRIG_EXT_TIM1_CH3
LL_ADC_INJ_TRIG_EXT_TIM1_CH4
LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
LL_ADC_INJ_TRIG_EXT_TIM20_CH2
LL_ADC_INJ_TRIG_EXT_TIM20_CH4
LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
LL_ADC_INJ_TRIG_EXT_TIM2_CH1
LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
LL_ADC_INJ_TRIG_EXT_TIM3_CH1
LL_ADC_INJ_TRIG_EXT_TIM3_CH3
LL_ADC_INJ_TRIG_EXT_TIM3_CH4
LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
LL_ADC_INJ_TRIG_EXT_TIM4_CH3
LL_ADC_INJ_TRIG_EXT_TIM4_CH4
LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
LL_ADC_INJ_TRIG_EXT_TIM8_CH2
LL_ADC_INJ_TRIG_EXT_TIM8_CH4
LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
LL_ADC_INJ_TRIG_SOFTWARE
ADC group injected - Trigger edge
LL_ADC_INJ_TRIG_EXT_RISING
LL_ADC_INJ_TRIG_EXT_RISINGFALLING
ADC group injected - Automatic trigger mode
LL_ADC_INJ_TRIG_INDEPENDENT
ADC group injected - Context queue mode
LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
LL_ADC_INJ_QUEUE_DISABLE
ADC group injected - Sequencer scan length
LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
ADC group injected - Sequencer discontinuous mode
LL_ADC_INJ_SEQ_DISCONT_DISABLE
ADC group injected - Sequencer ranks
LL_ADC_INJ_RANK_2
LL_ADC_INJ_RANK_3
LL_ADC_INJ_RANK_4
Channel - Sampling time
LL_ADC_SAMPLINGTIME_247CYCLES_5
LL_ADC_SAMPLINGTIME_24CYCLES_5
LL_ADC_SAMPLINGTIME_2CYCLES_5
LL_ADC_SAMPLINGTIME_47CYCLES_5
LL_ADC_SAMPLINGTIME_640CYCLES_5
LL_ADC_SAMPLINGTIME_6CYCLES_5
LL_ADC_SAMPLINGTIME_92CYCLES_5
Channel - Single or differential ending
LL_ADC_DIFFERENTIAL_ENDED
LL_ADC_SINGLE_ENDED
Analog watchdog - Analog watchdog number
LL_ADC_AWD2
LL_ADC_AWD3
Analog watchdog - Monitored channels
LL_ADC_AWD_ALL_CHANNELS_REG
LL_ADC_AWD_ALL_CHANNELS_REG_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ
LL_ADC_AWD_CH_VBAT_INJ
LL_ADC_AWD_CH_VBAT_REG
LL_ADC_AWD_CH_VBAT_REG_INJ
LL_ADC_AWD_CH_VOPAMP1_INJ
LL_ADC_AWD_CH_VOPAMP1_REG
LL_ADC_AWD_CH_VOPAMP1_REG_INJ
LL_ADC_AWD_CH_VOPAMP2_INJ
LL_ADC_AWD_CH_VOPAMP2_REG
LL_ADC_AWD_CH_VOPAMP2_REG_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC2_REG
LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC3_REG
LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ
LL_ADC_AWD_CH_VOPAMP4_INJ
LL_ADC_AWD_CH_VOPAMP4_REG
LL_ADC_AWD_CH_VOPAMP4_REG_INJ
LL_ADC_AWD_CH_VOPAMP5_INJ
LL_ADC_AWD_CH_VOPAMP5_REG
LL_ADC_AWD_CH_VOPAMP5_REG_INJ
LL_ADC_AWD_CH_VOPAMP6_INJ
LL_ADC_AWD_CH_VOPAMP6_REG
LL_ADC_AWD_CH_VOPAMP6_REG_INJ
LL_ADC_AWD_CH_VREFINT_INJ
LL_ADC_AWD_CH_VREFINT_REG
LL_ADC_AWD_CH_VREFINT_REG_INJ
LL_ADC_AWD_CHANNEL_0_INJ
LL_ADC_AWD_CHANNEL_0_REG
LL_ADC_AWD_CHANNEL_0_REG_INJ
LL_ADC_AWD_CHANNEL_10_INJ
LL_ADC_AWD_CHANNEL_10_REG
LL_ADC_AWD_CHANNEL_10_REG_INJ
LL_ADC_AWD_CHANNEL_11_INJ
LL_ADC_AWD_CHANNEL_11_REG
LL_ADC_AWD_CHANNEL_11_REG_INJ
LL_ADC_AWD_CHANNEL_12_INJ
LL_ADC_AWD_CHANNEL_12_REG
LL_ADC_AWD_CHANNEL_12_REG_INJ
LL_ADC_AWD_CHANNEL_13_INJ
LL_ADC_AWD_CHANNEL_13_REG
LL_ADC_AWD_CHANNEL_13_REG_INJ
LL_ADC_AWD_CHANNEL_14_INJ
LL_ADC_AWD_CHANNEL_14_REG
LL_ADC_AWD_CHANNEL_14_REG_INJ
LL_ADC_AWD_CHANNEL_15_INJ
LL_ADC_AWD_CHANNEL_15_REG
LL_ADC_AWD_CHANNEL_15_REG_INJ
LL_ADC_AWD_CHANNEL_16_INJ
LL_ADC_AWD_CHANNEL_16_REG
LL_ADC_AWD_CHANNEL_16_REG_INJ
LL_ADC_AWD_CHANNEL_17_INJ
LL_ADC_AWD_CHANNEL_17_REG
LL_ADC_AWD_CHANNEL_17_REG_INJ
LL_ADC_AWD_CHANNEL_18_INJ
LL_ADC_AWD_CHANNEL_18_REG
LL_ADC_AWD_CHANNEL_18_REG_INJ
LL_ADC_AWD_CHANNEL_1_INJ
LL_ADC_AWD_CHANNEL_1_REG
LL_ADC_AWD_CHANNEL_1_REG_INJ
LL_ADC_AWD_CHANNEL_2_INJ
LL_ADC_AWD_CHANNEL_2_REG
LL_ADC_AWD_CHANNEL_2_REG_INJ
LL_ADC_AWD_CHANNEL_3_INJ
LL_ADC_AWD_CHANNEL_3_REG
LL_ADC_AWD_CHANNEL_3_REG_INJ
LL_ADC_AWD_CHANNEL_4_INJ
LL_ADC_AWD_CHANNEL_4_REG
LL_ADC_AWD_CHANNEL_4_REG_INJ
LL_ADC_AWD_CHANNEL_5_INJ
LL_ADC_AWD_CHANNEL_5_REG
LL_ADC_AWD_CHANNEL_5_REG_INJ
LL_ADC_AWD_CHANNEL_6_INJ
LL_ADC_AWD_CHANNEL_6_REG
LL_ADC_AWD_CHANNEL_6_REG_INJ
LL_ADC_AWD_CHANNEL_7_INJ
LL_ADC_AWD_CHANNEL_7_REG
LL_ADC_AWD_CHANNEL_7_REG_INJ
LL_ADC_AWD_CHANNEL_8_INJ
LL_ADC_AWD_CHANNEL_8_REG
LL_ADC_AWD_CHANNEL_8_REG_INJ
LL_ADC_AWD_CHANNEL_9_INJ
LL_ADC_AWD_CHANNEL_9_REG
LL_ADC_AWD_CHANNEL_9_REG_INJ
LL_ADC_AWD_DISABLE
Analog watchdog - Thresholds
LL_ADC_AWD_THRESHOLD_LOW
LL_ADC_AWD_THRESHOLDS_HIGH_LOW
Analog watchdog - filtering config
LL_ADC_AWD_FILTERING_3SAMPLES
LL_ADC_AWD_FILTERING_4SAMPLES
LL_ADC_AWD_FILTERING_5SAMPLES
LL_ADC_AWD_FILTERING_6SAMPLES
LL_ADC_AWD_FILTERING_7SAMPLES
LL_ADC_AWD_FILTERING_8SAMPLES
LL_ADC_AWD_FILTERING_NONE
Oversampling - Oversampling scope
LL_ADC_OVS_GRP_INJ_REG_RESUMED
LL_ADC_OVS_GRP_INJECTED
LL_ADC_OVS_GRP_REGULAR_CONTINUED
LL_ADC_OVS_GRP_REGULAR_RESUMED
Oversampling - Discontinuous mode
LL_ADC_OVS_REG_DISCONT
Oversampling - Ratio
LL_ADC_OVS_RATIO_16
LL_ADC_OVS_RATIO_2
LL_ADC_OVS_RATIO_256
LL_ADC_OVS_RATIO_32
LL_ADC_OVS_RATIO_4
LL_ADC_OVS_RATIO_64
LL_ADC_OVS_RATIO_8
Oversampling - Data right shift
LL_ADC_OVS_SHIFT_RIGHT_1
LL_ADC_OVS_SHIFT_RIGHT_2
LL_ADC_OVS_SHIFT_RIGHT_3
LL_ADC_OVS_SHIFT_RIGHT_4
LL_ADC_OVS_SHIFT_RIGHT_5
LL_ADC_OVS_SHIFT_RIGHT_6
LL_ADC_OVS_SHIFT_RIGHT_7
LL_ADC_OVS_SHIFT_RIGHT_8
Multimode - Mode
LL_ADC_MULTI_DUAL_INJ_SIMULT
LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
LL_ADC_MULTI_DUAL_REG_INTERL
LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
LL_ADC_MULTI_DUAL_REG_SIMULT
LL_ADC_MULTI_INDEPENDENT
Multimode - DMA transfer
LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
Multimode - Delay between two sampling phases
LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
Multimode - ADC master or slave
LL_ADC_MULTI_MASTER_SLAVE
LL_ADC_MULTI_SLAVE
Definitions of constants used by helper macro
Definitions of ADC hardware constraints delays
LL_ADC_DELAY_INTERNAL_REGUL_STAB_US
LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US
LL_ADC_DELAY_TEMPSENSOR_STAB_US
LL_ADC_DELAY_VREFINT_STAB_US
ADC Exported Macros
LL_ADC_WriteReg
ADC helper macro
__LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
__LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION
__LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW
__LL_ADC_CALC_DATA_TO_VOLTAGE
__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE
__LL_ADC_CALC_TEMPERATURE
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS
__LL_ADC_CALC_VREFANALOG_VOLTAGE
__LL_ADC_CALIB_FACTOR_SINGLE_DIFF
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL
__LL_ADC_CHANNEL_TO_DECIMAL_NB
__LL_ADC_COMMON_INSTANCE
__LL_ADC_CONVERT_DATA_RESOLUTION
__LL_ADC_DECIMAL_NB_TO_CHANNEL
__LL_ADC_DIGITAL_SCALE
__LL_ADC_IS_CHANNEL_INTERNAL
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE
__LL_ADC_MULTI_INSTANCE_MASTER
ADC Exported Functions
Configuration of ADC hierarchical scope: common to several
LL_ADC_GetCommonPathInternalCh
LL_ADC_SetCommonClock
LL_ADC_SetCommonPathInternalCh
LL_ADC_SetCommonPathInternalChAdd
LL_ADC_SetCommonPathInternalChRem
Configuration of ADC hierarchical scope: ADC instance
LL_ADC_GetDataAlignment
LL_ADC_GetGainCompensation
LL_ADC_GetLowPowerMode
LL_ADC_GetOffsetChannel
LL_ADC_GetOffsetLevel
LL_ADC_GetOffsetSaturation
LL_ADC_GetOffsetSign
LL_ADC_GetOffsetState
LL_ADC_GetResolution
LL_ADC_GetSamplingTimeCommonConfig
LL_ADC_SetCalibrationFactor
LL_ADC_SetDataAlignment
LL_ADC_SetGainCompensation
LL_ADC_SetLowPowerMode
LL_ADC_SetOffset
LL_ADC_SetOffsetSaturation
LL_ADC_SetOffsetSign
LL_ADC_SetOffsetState
LL_ADC_SetResolution
LL_ADC_SetSamplingTimeCommonConfig
Configuration of ADC hierarchical scope: group regular
LL_ADC_REG_GetDMATransfer
LL_ADC_REG_GetOverrun
LL_ADC_REG_GetSamplingMode
LL_ADC_REG_GetSequencerDiscont
LL_ADC_REG_GetSequencerLength
LL_ADC_REG_GetSequencerRanks
LL_ADC_REG_GetTriggerEdge
LL_ADC_REG_GetTriggerSource
LL_ADC_REG_IsTriggerSourceSWStart
LL_ADC_REG_SetContinuousMode
LL_ADC_REG_SetDMATransfer
LL_ADC_REG_SetOverrun
LL_ADC_REG_SetSamplingMode
LL_ADC_REG_SetSequencerDiscont
LL_ADC_REG_SetSequencerLength
LL_ADC_REG_SetSequencerRanks
LL_ADC_REG_SetTriggerEdge
LL_ADC_REG_SetTriggerSource
Configuration of ADC hierarchical scope: group injected
LL_ADC_INJ_GetQueueMode
LL_ADC_INJ_GetSequencerDiscont
LL_ADC_INJ_GetSequencerLength
LL_ADC_INJ_GetSequencerRanks
LL_ADC_INJ_GetTrigAuto
LL_ADC_INJ_GetTriggerEdge
LL_ADC_INJ_GetTriggerSource
LL_ADC_INJ_IsTriggerSourceSWStart
LL_ADC_INJ_SetQueueMode
LL_ADC_INJ_SetSequencerDiscont
LL_ADC_INJ_SetSequencerLength
LL_ADC_INJ_SetSequencerRanks
LL_ADC_INJ_SetTrigAuto
LL_ADC_INJ_SetTriggerEdge
LL_ADC_INJ_SetTriggerSource
Configuration of ADC hierarchical scope: channels
LL_ADC_GetChannelSingleDiff
LL_ADC_SetChannelSamplingTime
LL_ADC_SetChannelSingleDiff
Configuration of ADC transversal scope: analog watchdog
LL_ADC_GetAnalogWDMonitChannels
LL_ADC_GetAnalogWDThresholds
LL_ADC_GetAWDFilteringConfiguration
LL_ADC_SetAnalogWDMonitChannels
LL_ADC_SetAnalogWDThresholds
LL_ADC_SetAWDFilteringConfiguration
Configuration of ADC transversal scope: oversampling
LL_ADC_GetOverSamplingDiscont
LL_ADC_GetOverSamplingRatio
LL_ADC_GetOverSamplingScope
LL_ADC_GetOverSamplingShift
LL_ADC_SetOverSamplingDiscont
LL_ADC_SetOverSamplingScope
Configuration of ADC hierarchical scope: multimode
LL_ADC_GetMultimode
LL_ADC_GetMultiTwoSamplingDelay
LL_ADC_SetMultiDMATransfer
LL_ADC_SetMultimode
LL_ADC_SetMultiTwoSamplingDelay
Operation on ADC hierarchical scope: ADC instance
LL_ADC_DisableDeepPowerDown
LL_ADC_DisableInternalRegulator
LL_ADC_Enable
LL_ADC_EnableDeepPowerDown
LL_ADC_EnableInternalRegulator
LL_ADC_IsCalibrationOnGoing
LL_ADC_IsDeepPowerDownEnabled
LL_ADC_IsDisableOngoing
LL_ADC_IsEnabled
LL_ADC_IsInternalRegulatorEnabled
LL_ADC_StartCalibration
Operation on ADC hierarchical scope: group regular
LL_ADC_REG_IsStopConversionOngoing
LL_ADC_REG_ReadConversionData10
LL_ADC_REG_ReadConversionData12
LL_ADC_REG_ReadConversionData32
LL_ADC_REG_ReadConversionData6
LL_ADC_REG_ReadConversionData8
LL_ADC_REG_ReadMultiConversionData32
LL_ADC_REG_StartConversion
LL_ADC_REG_StartSamplingPhase
LL_ADC_REG_StopConversion
LL_ADC_REG_StopSamplingPhase
Operation on ADC hierarchical scope: group injected
LL_ADC_INJ_IsStopConversionOngoing
LL_ADC_INJ_ReadConversionData10
LL_ADC_INJ_ReadConversionData12
LL_ADC_INJ_ReadConversionData32
LL_ADC_INJ_ReadConversionData6
LL_ADC_INJ_ReadConversionData8
LL_ADC_INJ_StartConversion
LL_ADC_INJ_StopConversion
ADC flag management
LL_ADC_ClearFlag_AWD1
LL_ADC_ClearFlag_AWD2
LL_ADC_ClearFlag_AWD3
LL_ADC_ClearFlag_EOC
LL_ADC_ClearFlag_EOS
LL_ADC_ClearFlag_EOSMP
LL_ADC_ClearFlag_JEOC
LL_ADC_ClearFlag_JEOS
LL_ADC_ClearFlag_JQOVF
LL_ADC_ClearFlag_OVR
LL_ADC_IsActiveFlag_ADRDY
LL_ADC_IsActiveFlag_AWD1
LL_ADC_IsActiveFlag_AWD2
LL_ADC_IsActiveFlag_AWD3
LL_ADC_IsActiveFlag_EOC
LL_ADC_IsActiveFlag_EOS
LL_ADC_IsActiveFlag_EOSMP
LL_ADC_IsActiveFlag_JEOC
LL_ADC_IsActiveFlag_JEOS
LL_ADC_IsActiveFlag_JQOVF
LL_ADC_IsActiveFlag_MST_ADRDY
LL_ADC_IsActiveFlag_MST_AWD1
LL_ADC_IsActiveFlag_MST_AWD2
LL_ADC_IsActiveFlag_MST_AWD3
LL_ADC_IsActiveFlag_MST_EOC
LL_ADC_IsActiveFlag_MST_EOS
LL_ADC_IsActiveFlag_MST_EOSMP
LL_ADC_IsActiveFlag_MST_JEOC
LL_ADC_IsActiveFlag_MST_JEOS
LL_ADC_IsActiveFlag_MST_JQOVF
LL_ADC_IsActiveFlag_MST_OVR
LL_ADC_IsActiveFlag_OVR
LL_ADC_IsActiveFlag_SLV_ADRDY
LL_ADC_IsActiveFlag_SLV_AWD1
LL_ADC_IsActiveFlag_SLV_AWD2
LL_ADC_IsActiveFlag_SLV_AWD3
LL_ADC_IsActiveFlag_SLV_EOC
LL_ADC_IsActiveFlag_SLV_EOS
LL_ADC_IsActiveFlag_SLV_EOSMP
LL_ADC_IsActiveFlag_SLV_JEOC
LL_ADC_IsActiveFlag_SLV_JEOS
LL_ADC_IsActiveFlag_SLV_JQOVF
LL_ADC_IsActiveFlag_SLV_OVR
ADC IT management
LL_ADC_DisableIT_AWD1
LL_ADC_DisableIT_AWD2
LL_ADC_DisableIT_AWD3
LL_ADC_DisableIT_EOC
LL_ADC_DisableIT_EOS
LL_ADC_DisableIT_EOSMP
LL_ADC_DisableIT_JEOC
LL_ADC_DisableIT_JEOS
LL_ADC_DisableIT_JQOVF
LL_ADC_DisableIT_OVR
LL_ADC_EnableIT_ADRDY
LL_ADC_EnableIT_AWD1
LL_ADC_EnableIT_AWD2
LL_ADC_EnableIT_AWD3
LL_ADC_EnableIT_EOC
LL_ADC_EnableIT_EOS
LL_ADC_EnableIT_EOSMP
LL_ADC_EnableIT_JEOC
LL_ADC_EnableIT_JEOS
LL_ADC_EnableIT_JQOVF
LL_ADC_EnableIT_OVR
LL_ADC_IsEnabledIT_ADRDY
LL_ADC_IsEnabledIT_AWD1
LL_ADC_IsEnabledIT_AWD2
LL_ADC_IsEnabledIT_AWD3
LL_ADC_IsEnabledIT_EOC
LL_ADC_IsEnabledIT_EOS
LL_ADC_IsEnabledIT_EOSMP
LL_ADC_IsEnabledIT_JEOC
LL_ADC_IsEnabledIT_JEOS
LL_ADC_IsEnabledIT_JQOVF
LL_ADC_IsEnabledIT_OVR
Initialization and de-initialization functions
LL_ADC_CommonInit
LL_ADC_CommonStructInit
LL_ADC_DeInit
LL_ADC_Init
LL_ADC_INJ_Init
LL_ADC_INJ_StructInit
LL_ADC_REG_Init
LL_ADC_REG_StructInit
LL_ADC_StructInit
BUS
LL_AHB1_GRP1_PERIPH_CORDIC
LL_AHB1_GRP1_PERIPH_CRC
LL_AHB1_GRP1_PERIPH_DMA1
LL_AHB1_GRP1_PERIPH_DMA2
LL_AHB1_GRP1_PERIPH_DMAMUX1
LL_AHB1_GRP1_PERIPH_FLASH
LL_AHB1_GRP1_PERIPH_FMAC
LL_AHB1_GRP1_PERIPH_SRAM1
AHB2 GRP1 PERIPH
LL_AHB2_GRP1_PERIPH_ADC345
LL_AHB2_GRP1_PERIPH_ALL
LL_AHB2_GRP1_PERIPH_CCM
LL_AHB2_GRP1_PERIPH_DAC1
LL_AHB2_GRP1_PERIPH_DAC2
LL_AHB2_GRP1_PERIPH_DAC3
LL_AHB2_GRP1_PERIPH_DAC4
LL_AHB2_GRP1_PERIPH_GPIOA
LL_AHB2_GRP1_PERIPH_GPIOB
LL_AHB2_GRP1_PERIPH_GPIOC
LL_AHB2_GRP1_PERIPH_GPIOD
LL_AHB2_GRP1_PERIPH_GPIOE
LL_AHB2_GRP1_PERIPH_GPIOF
LL_AHB2_GRP1_PERIPH_GPIOG
LL_AHB2_GRP1_PERIPH_RNG
LL_AHB2_GRP1_PERIPH_SRAM2
AHB3 GRP1 PERIPH
LL_AHB3_GRP1_PERIPH_FMC
LL_AHB3_GRP1_PERIPH_QSPI
APB1 GRP1 PERIPH
LL_APB1_GRP1_PERIPH_CRS
LL_APB1_GRP1_PERIPH_FDCAN
LL_APB1_GRP1_PERIPH_I2C1
LL_APB1_GRP1_PERIPH_I2C2
LL_APB1_GRP1_PERIPH_I2C3
LL_APB1_GRP1_PERIPH_LPTIM1
LL_APB1_GRP1_PERIPH_PWR
LL_APB1_GRP1_PERIPH_RTCAPB
LL_APB1_GRP1_PERIPH_SPI2
LL_APB1_GRP1_PERIPH_SPI3
LL_APB1_GRP1_PERIPH_TIM2
LL_APB1_GRP1_PERIPH_TIM3
LL_APB1_GRP1_PERIPH_TIM4
LL_APB1_GRP1_PERIPH_TIM5
LL_APB1_GRP1_PERIPH_TIM6
LL_APB1_GRP1_PERIPH_TIM7
LL_APB1_GRP1_PERIPH_UART4
LL_APB1_GRP1_PERIPH_UART5
LL_APB1_GRP1_PERIPH_USART2
LL_APB1_GRP1_PERIPH_USART3
LL_APB1_GRP1_PERIPH_USB
LL_APB1_GRP1_PERIPH_WWDG
APB1 GRP2 PERIPH
LL_APB1_GRP2_PERIPH_I2C4
LL_APB1_GRP2_PERIPH_LPUART1
LL_APB1_GRP2_PERIPH_UCPD1
APB2 GRP1 PERIPH
LL_APB2_GRP1_PERIPH_HRTIM1
LL_APB2_GRP1_PERIPH_SAI1
LL_APB2_GRP1_PERIPH_SPI1
LL_APB2_GRP1_PERIPH_SPI4
LL_APB2_GRP1_PERIPH_SYSCFG
LL_APB2_GRP1_PERIPH_TIM1
LL_APB2_GRP1_PERIPH_TIM15
LL_APB2_GRP1_PERIPH_TIM16
LL_APB2_GRP1_PERIPH_TIM17
LL_APB2_GRP1_PERIPH_TIM20
LL_APB2_GRP1_PERIPH_TIM8
LL_APB2_GRP1_PERIPH_USART1
BUS Exported Functions
LL_AHB1_GRP1_DisableClockStopSleep
LL_AHB1_GRP1_EnableClock
LL_AHB1_GRP1_EnableClockStopSleep
LL_AHB1_GRP1_ForceReset
LL_AHB1_GRP1_IsEnabledClock
LL_AHB1_GRP1_ReleaseReset
AHB2
LL_AHB2_GRP1_DisableClockStopSleep
LL_AHB2_GRP1_EnableClock
LL_AHB2_GRP1_EnableClockStopSleep
LL_AHB2_GRP1_ForceReset
LL_AHB2_GRP1_IsEnabledClock
LL_AHB2_GRP1_ReleaseReset
AHB3
LL_AHB3_GRP1_DisableClockStopSleep
LL_AHB3_GRP1_EnableClock
LL_AHB3_GRP1_EnableClockStopSleep
LL_AHB3_GRP1_ForceReset
LL_AHB3_GRP1_IsEnabledClock
LL_AHB3_GRP1_ReleaseReset
APB1
LL_APB1_GRP1_DisableClockStopSleep
LL_APB1_GRP1_EnableClock
LL_APB1_GRP1_EnableClockStopSleep
LL_APB1_GRP1_ForceReset
LL_APB1_GRP1_IsEnabledClock
LL_APB1_GRP1_ReleaseReset
LL_APB1_GRP2_DisableClock
LL_APB1_GRP2_DisableClockStopSleep
LL_APB1_GRP2_EnableClock
LL_APB1_GRP2_EnableClockStopSleep
LL_APB1_GRP2_ForceReset
LL_APB1_GRP2_IsEnabledClock
LL_APB1_GRP2_ReleaseReset
APB2
LL_APB2_GRP1_DisableClockStopSleep
LL_APB2_GRP1_EnableClock
LL_APB2_GRP1_EnableClockStopSleep
LL_APB2_GRP1_ForceReset
LL_APB2_GRP1_IsEnabledClock
LL_APB2_GRP1_ReleaseReset
COMP
IS_LL_COMP_INPUT_MINUS
IS_LL_COMP_INPUT_PLUS
IS_LL_COMP_OUTPUT_BLANKING_SOURCE
IS_LL_COMP_OUTPUT_POLARITY
COMP Exported Init structure
COMP Exported Constants
LL_COMP_INPUT_PLUS_IO2
Comparator inputs - Input minus (input inverting) selection
LL_COMP_INPUT_MINUS_1_4VREFINT
LL_COMP_INPUT_MINUS_3_4VREFINT
LL_COMP_INPUT_MINUS_DAC1_CH1
LL_COMP_INPUT_MINUS_DAC1_CH2
LL_COMP_INPUT_MINUS_DAC2_CH1
LL_COMP_INPUT_MINUS_DAC3_CH1
LL_COMP_INPUT_MINUS_DAC3_CH2
LL_COMP_INPUT_MINUS_DAC4_CH1
LL_COMP_INPUT_MINUS_DAC4_CH2
LL_COMP_INPUT_MINUS_IO1
LL_COMP_INPUT_MINUS_IO2
LL_COMP_INPUT_MINUS_VREFINT
Comparator input - Hysteresis
LL_COMP_HYSTERESIS_20MV
LL_COMP_HYSTERESIS_30MV
LL_COMP_HYSTERESIS_40MV
LL_COMP_HYSTERESIS_50MV
LL_COMP_HYSTERESIS_60MV
LL_COMP_HYSTERESIS_70MV
LL_COMP_HYSTERESIS_HIGH
LL_COMP_HYSTERESIS_LOW
LL_COMP_HYSTERESIS_MEDIUM
LL_COMP_HYSTERESIS_NONE
Comparator output - Output polarity
LL_COMP_OUTPUTPOL_NONINVERTED
Comparator output - Blanking source
LL_COMP_BLANKINGSRC_TIM15_OC1
LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
LL_COMP_BLANKINGSRC_TIM20_OC5
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
LL_COMP_BLANKINGSRC_TIM4_OC3
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
Comparator output - Output level
LL_COMP_OUTPUT_LEVEL_LOW
Definitions of COMP hardware constraints delays
LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US
COMP Exported Macros
LL_COMP_WriteReg
COMP helper macro
COMP Exported Functions
LL_COMP_GetInputHysteresis
LL_COMP_GetInputMinus
LL_COMP_GetInputPlus
LL_COMP_SetInputHysteresis
LL_COMP_SetInputMinus
LL_COMP_SetInputPlus
Configuration of comparator output
LL_COMP_GetOutputPolarity
LL_COMP_SetOutputBlankingSource
LL_COMP_SetOutputPolarity
Operation on comparator instance
LL_COMP_Enable
LL_COMP_IsEnabled
LL_COMP_IsLocked
LL_COMP_Lock
LL_COMP_ReadOutputLevel
Initialization and de-initialization functions
LL_COMP_Init
LL_COMP_StructInit
CORDIC
IT Defines
FUNCTION
LL_CORDIC_FUNCTION_COSINE
LL_CORDIC_FUNCTION_HARCTANGENT
LL_CORDIC_FUNCTION_HCOSINE
LL_CORDIC_FUNCTION_HSINE
LL_CORDIC_FUNCTION_MODULUS
LL_CORDIC_FUNCTION_NATURALLOG
LL_CORDIC_FUNCTION_PHASE
LL_CORDIC_FUNCTION_SINE
LL_CORDIC_FUNCTION_SQUAREROOT
PRECISION
LL_CORDIC_PRECISION_11CYCLES
LL_CORDIC_PRECISION_12CYCLES
LL_CORDIC_PRECISION_13CYCLES
LL_CORDIC_PRECISION_14CYCLES
LL_CORDIC_PRECISION_15CYCLES
LL_CORDIC_PRECISION_1CYCLE
LL_CORDIC_PRECISION_2CYCLES
LL_CORDIC_PRECISION_3CYCLES
LL_CORDIC_PRECISION_4CYCLES
LL_CORDIC_PRECISION_5CYCLES
LL_CORDIC_PRECISION_6CYCLES
LL_CORDIC_PRECISION_7CYCLES
LL_CORDIC_PRECISION_8CYCLES
LL_CORDIC_PRECISION_9CYCLES
SCALE
LL_CORDIC_SCALE_1
LL_CORDIC_SCALE_2
LL_CORDIC_SCALE_3
LL_CORDIC_SCALE_4
LL_CORDIC_SCALE_5
LL_CORDIC_SCALE_6
LL_CORDIC_SCALE_7
NBWRITE
LL_CORDIC_NBWRITE_2
NBREAD
LL_CORDIC_NBREAD_2
INSIZE
LL_CORDIC_INSIZE_32BITS
OUTSIZE
LL_CORDIC_OUTSIZE_32BITS
DMA register data
LL_CORDIC_DMA_REG_DATA_OUT
CORDIC Exported Macros
LL_CORDIC_WriteReg
CORDIC Exported Functions
LL_CORDIC_GetFunction
LL_CORDIC_GetInSize
LL_CORDIC_GetNbRead
LL_CORDIC_GetNbWrite
LL_CORDIC_GetOutSize
LL_CORDIC_GetPrecision
LL_CORDIC_GetScale
LL_CORDIC_SetFunction
LL_CORDIC_SetInSize
LL_CORDIC_SetNbRead
LL_CORDIC_SetNbWrite
LL_CORDIC_SetOutSize
LL_CORDIC_SetPrecision
LL_CORDIC_SetScale
IT_Management
LL_CORDIC_EnableIT
LL_CORDIC_IsEnabledIT
DMA_Management
LL_CORDIC_DisableDMAReq_WR
LL_CORDIC_DMA_GetRegAddr
LL_CORDIC_EnableDMAReq_RD
LL_CORDIC_EnableDMAReq_WR
LL_CORDIC_IsEnabledDMAReq_RD
LL_CORDIC_IsEnabledDMAReq_WR
FLAG_Management
Data_Management
LL_CORDIC_WriteData
Initialization and de-initialization functions
CORTEX
LL_SYSTICK_CLKSOURCE_HCLK_DIV8
Handler Fault type
LL_HANDLER_FAULT_MEM
LL_HANDLER_FAULT_USG
MPU Control
LL_MPU_CTRL_HFNMI_PRIVDEF
LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
LL_MPU_CTRL_PRIVILEGED_DEFAULT
MPU Region Number
LL_MPU_REGION_NUMBER1
LL_MPU_REGION_NUMBER2
LL_MPU_REGION_NUMBER3
LL_MPU_REGION_NUMBER4
LL_MPU_REGION_NUMBER5
LL_MPU_REGION_NUMBER6
LL_MPU_REGION_NUMBER7
MPU Region Size
LL_MPU_REGION_SIZE_128KB
LL_MPU_REGION_SIZE_128MB
LL_MPU_REGION_SIZE_16KB
LL_MPU_REGION_SIZE_16MB
LL_MPU_REGION_SIZE_1GB
LL_MPU_REGION_SIZE_1KB
LL_MPU_REGION_SIZE_1MB
LL_MPU_REGION_SIZE_256B
LL_MPU_REGION_SIZE_256KB
LL_MPU_REGION_SIZE_256MB
LL_MPU_REGION_SIZE_2GB
LL_MPU_REGION_SIZE_2KB
LL_MPU_REGION_SIZE_2MB
LL_MPU_REGION_SIZE_32B
LL_MPU_REGION_SIZE_32KB
LL_MPU_REGION_SIZE_32MB
LL_MPU_REGION_SIZE_4GB
LL_MPU_REGION_SIZE_4KB
LL_MPU_REGION_SIZE_4MB
LL_MPU_REGION_SIZE_512B
LL_MPU_REGION_SIZE_512KB
LL_MPU_REGION_SIZE_512MB
LL_MPU_REGION_SIZE_64B
LL_MPU_REGION_SIZE_64KB
LL_MPU_REGION_SIZE_64MB
LL_MPU_REGION_SIZE_8KB
LL_MPU_REGION_SIZE_8MB
MPU Region Privileges
LL_MPU_REGION_NO_ACCESS
LL_MPU_REGION_PRIV_RO
LL_MPU_REGION_PRIV_RO_URO
LL_MPU_REGION_PRIV_RW
LL_MPU_REGION_PRIV_RW_URO
MPU TEX Level
LL_MPU_TEX_LEVEL1
LL_MPU_TEX_LEVEL2
LL_MPU_TEX_LEVEL4
MPU Instruction Access
LL_MPU_INSTRUCTION_ACCESS_ENABLE
MPU Shareable Access
LL_MPU_ACCESS_SHAREABLE
MPU Cacheable Access
LL_MPU_ACCESS_NOT_CACHEABLE
MPU Bufferable Access
LL_MPU_ACCESS_NOT_BUFFERABLE
CORTEX Exported Functions
LL_SYSTICK_EnableIT
LL_SYSTICK_GetClkSource
LL_SYSTICK_IsActiveCounterFlag
LL_SYSTICK_IsEnabledIT
LL_SYSTICK_SetClkSource
LOW POWER MODE
LL_LPM_DisableSleepOnExit
LL_LPM_EnableDeepSleep
LL_LPM_EnableEventOnPend
LL_LPM_EnableSleep
LL_LPM_EnableSleepOnExit
HANDLER
LL_HANDLER_EnableFault
MCU INFO
LL_CPUID_GetImplementer
LL_CPUID_GetParNo
LL_CPUID_GetRevision
LL_CPUID_GetVariant
MPU
LL_MPU_Disable
LL_MPU_DisableRegion
LL_MPU_Enable
LL_MPU_EnableRegion
LL_MPU_IsEnabled
CRC
LL_CRC_POLYLENGTH_32B
LL_CRC_POLYLENGTH_7B
LL_CRC_POLYLENGTH_8B
Input Data Reverse
LL_CRC_INDATA_REVERSE_HALFWORD
LL_CRC_INDATA_REVERSE_NONE
LL_CRC_INDATA_REVERSE_WORD
Output Data Reverse
LL_CRC_OUTDATA_REVERSE_NONE
Default CRC generating polynomial value
Default CRC computation initialization value
CRC Exported Macros
LL_CRC_WriteReg
CRC Exported Functions
LL_CRC_GetInputDataReverseMode
LL_CRC_GetOutputDataReverseMode
LL_CRC_GetPolynomialCoef
LL_CRC_GetPolynomialSize
LL_CRC_ResetCRCCalculationUnit
LL_CRC_SetInitialData
LL_CRC_SetInputDataReverseMode
LL_CRC_SetOutputDataReverseMode
LL_CRC_SetPolynomialCoef
LL_CRC_SetPolynomialSize
Data_Management
LL_CRC_FeedData32
LL_CRC_FeedData8
LL_CRC_Read_IDR
LL_CRC_ReadData16
LL_CRC_ReadData32
LL_CRC_ReadData7
LL_CRC_ReadData8
LL_CRC_Write_IDR
Initialization and de-initialization functions
CRS
LL_CRS_ISR_ESYNCF
LL_CRS_ISR_SYNCERR
LL_CRS_ISR_SYNCMISS
LL_CRS_ISR_SYNCOKF
LL_CRS_ISR_SYNCWARNF
LL_CRS_ISR_TRIMOVF
IT Defines
LL_CRS_CR_ESYNCIE
LL_CRS_CR_SYNCOKIE
LL_CRS_CR_SYNCWARNIE
Synchronization Signal Divider
LL_CRS_SYNC_DIV_128
LL_CRS_SYNC_DIV_16
LL_CRS_SYNC_DIV_2
LL_CRS_SYNC_DIV_32
LL_CRS_SYNC_DIV_4
LL_CRS_SYNC_DIV_64
LL_CRS_SYNC_DIV_8
Synchronization Signal Source
LL_CRS_SYNC_SOURCE_LSE
LL_CRS_SYNC_SOURCE_USB
Synchronization Signal Polarity
LL_CRS_SYNC_POLARITY_RISING
Frequency Error Direction
LL_CRS_FREQ_ERROR_DIR_UP
Default Values
LL_CRS_HSI48CALIBRATION_DEFAULT
LL_CRS_RELOADVALUE_DEFAULT
CRS Exported Macros
LL_CRS_WriteReg
Exported_Macros_Calculate_Reload
CRS Exported Functions
LL_CRS_DisableAutoTrimming
LL_CRS_DisableFreqErrorCounter
LL_CRS_EnableAutoTrimming
LL_CRS_EnableFreqErrorCounter
LL_CRS_GetFreqErrorLimit
LL_CRS_GetHSI48SmoothTrimming
LL_CRS_GetReloadCounter
LL_CRS_GetSyncDivider
LL_CRS_GetSyncPolarity
LL_CRS_GetSyncSignalSource
LL_CRS_IsEnabledAutoTrimming
LL_CRS_IsEnabledFreqErrorCounter
LL_CRS_SetFreqErrorLimit
LL_CRS_SetHSI48SmoothTrimming
LL_CRS_SetReloadCounter
LL_CRS_SetSyncDivider
LL_CRS_SetSyncPolarity
LL_CRS_SetSyncSignalSource
CRS_Management
LL_CRS_GetFreqErrorCapture
LL_CRS_GetFreqErrorDirection
FLAG_Management
LL_CRS_ClearFlag_ESYNC
LL_CRS_ClearFlag_SYNCOK
LL_CRS_ClearFlag_SYNCWARN
LL_CRS_IsActiveFlag_ERR
LL_CRS_IsActiveFlag_ESYNC
LL_CRS_IsActiveFlag_SYNCERR
LL_CRS_IsActiveFlag_SYNCMISS
LL_CRS_IsActiveFlag_SYNCOK
LL_CRS_IsActiveFlag_SYNCWARN
LL_CRS_IsActiveFlag_TRIMOVF
IT_Management
LL_CRS_DisableIT_ESYNC
LL_CRS_DisableIT_SYNCOK
LL_CRS_DisableIT_SYNCWARN
LL_CRS_EnableIT_ERR
LL_CRS_EnableIT_ESYNC
LL_CRS_EnableIT_SYNCOK
LL_CRS_EnableIT_SYNCWARN
LL_CRS_IsEnabledIT_ERR
LL_CRS_IsEnabledIT_ESYNC
LL_CRS_IsEnabledIT_SYNCOK
LL_CRS_IsEnabledIT_SYNCWARN
Initialization and de-initialization functions
DAC
DAC_CR_CH2_BITOFFSET
DAC_CR_CHX_BITOFFSET_MASK
DAC_DHR12LD_DACC2DHR_BITOFFSET_POS
DAC_DHR12RD_DACC2DHR_BITOFFSET_POS
DAC_DHR8RD_DACC2DHR_BITOFFSET_POS
DAC_DIGITAL_SCALE_12BITS
DAC_REG_DHR12L1_REGOFFSET
DAC_REG_DHR12L2_REGOFFSET
DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR12LX_REGOFFSET_MASK
DAC_REG_DHR12R1_REGOFFSET
DAC_REG_DHR12R2_REGOFFSET
DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR12RX_REGOFFSET_MASK
DAC_REG_DHR8R1_REGOFFSET
DAC_REG_DHR8R2_REGOFFSET
DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR8RX_REGOFFSET_MASK
DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
DAC_REG_DHRX_REGOFFSET_MASK
DAC_REG_DOR1_REGOFFSET
DAC_REG_DOR2_REGOFFSET
DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
DAC_REG_DORX_REGOFFSET_MASK
DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
DAC_REG_SHSR1_REGOFFSET
DAC_REG_SHSR2_REGOFFSET
DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
DAC_REG_SHSRX_REGOFFSET_MASK
DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
DAC_REG_STR1_REGOFFSET
DAC_REG_STR2_REGOFFSET
DAC_REG_STRX_REGOFFSET_BITOFFSET_POS
DAC_REG_STRX_REGOFFSET_MASK
DAC_REG_STRX_REGOFFSET_MASK_POSBIT0
DAC_SWTR_CH1
DAC_SWTR_CH2
DAC_SWTR_CHX_MASK
DAC_SWTRB_CH1
DAC_SWTRB_CH2
DAC_SWTRB_CHX_MASK
DAC Private Macros
IS_LL_DAC_CHANNEL
IS_LL_DAC_OUTPUT_BUFFER
IS_LL_DAC_OUTPUT_CONNECTION
IS_LL_DAC_OUTPUT_MODE
IS_LL_DAC_TRIGGER_SOURCE
IS_LL_DAC_TRIGGER_SOURCE2
IS_LL_DAC_WAVE_AUTO_GENER_CONFIG
IS_LL_DAC_WAVE_AUTO_GENER_MODE
DAC Exported Init structure
DAC Exported Constants
LL_DAC_FLAG_BWST2
LL_DAC_FLAG_CAL1
LL_DAC_FLAG_CAL2
LL_DAC_FLAG_DAC1RDY
LL_DAC_FLAG_DAC2RDY
LL_DAC_FLAG_DMAUDR1
LL_DAC_FLAG_DMAUDR2
LL_DAC_FLAG_DORSTAT1
LL_DAC_FLAG_DORSTAT2
DAC interruptions
LL_DAC_IT_DMAUDRIE2
DAC channels
LL_DAC_CHANNEL_2
DAC high frequency interface mode
LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
LL_DAC_HIGH_FREQ_MODE_DISABLE
DAC operating mode
LL_DAC_MODE_NORMAL_OPERATION
DAC trigger source
LL_DAC_TRIG_EXT_EXTI_LINE9
LL_DAC_TRIG_EXT_HRTIM_RST_TRG1
LL_DAC_TRIG_EXT_HRTIM_RST_TRG2
LL_DAC_TRIG_EXT_HRTIM_RST_TRG3
LL_DAC_TRIG_EXT_HRTIM_RST_TRG4
LL_DAC_TRIG_EXT_HRTIM_RST_TRG5
LL_DAC_TRIG_EXT_HRTIM_RST_TRG6
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6
LL_DAC_TRIG_EXT_HRTIM_TRGO1
LL_DAC_TRIG_EXT_HRTIM_TRGO2
LL_DAC_TRIG_EXT_HRTIM_TRGO3
LL_DAC_TRIG_EXT_TIM15_TRGO
LL_DAC_TRIG_EXT_TIM1_TRGO
LL_DAC_TRIG_EXT_TIM2_TRGO
LL_DAC_TRIG_EXT_TIM3_TRGO
LL_DAC_TRIG_EXT_TIM4_TRGO
LL_DAC_TRIG_EXT_TIM6_TRGO
LL_DAC_TRIG_EXT_TIM7_TRGO
LL_DAC_TRIG_EXT_TIM8_TRGO
LL_DAC_TRIG_SOFTWARE
DAC waveform automatic generation mode
LL_DAC_WAVE_AUTO_GENERATION_NONE
LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
DAC wave generation - Noise LFSR unmask bits
LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
DAC wave generation - Triangle amplitude
LL_DAC_TRIANGLE_AMPLITUDE_1023
LL_DAC_TRIANGLE_AMPLITUDE_127
LL_DAC_TRIANGLE_AMPLITUDE_15
LL_DAC_TRIANGLE_AMPLITUDE_2047
LL_DAC_TRIANGLE_AMPLITUDE_255
LL_DAC_TRIANGLE_AMPLITUDE_3
LL_DAC_TRIANGLE_AMPLITUDE_31
LL_DAC_TRIANGLE_AMPLITUDE_4095
LL_DAC_TRIANGLE_AMPLITUDE_511
LL_DAC_TRIANGLE_AMPLITUDE_63
LL_DAC_TRIANGLE_AMPLITUDE_7
DAC wave generation - Sawtooth polarity mode
LL_DAC_SAWTOOTH_POLARITY_INCREMENT
DAC channel output mode
LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
DAC channel output buffer
LL_DAC_OUTPUT_BUFFER_ENABLE
DAC channel output connection
LL_DAC_OUTPUT_CONNECT_INTERNAL
DAC channel signed format
LL_DAC_SIGNED_FORMAT_ENABLE
DAC channel output resolution
LL_DAC_RESOLUTION_8B
DAC registers compliant with specific purpose
LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
Definitions of DAC hardware constraints delays
LL_DAC_DELAY_VOLTAGE_SETTLING_US
DAC Exported Macros
LL_DAC_WriteReg
DAC helper macro
__LL_DAC_CHANNEL_TO_DECIMAL_NB
__LL_DAC_DECIMAL_NB_TO_CHANNEL
__LL_DAC_DIGITAL_SCALE
__LL_DAC_FORMAT_SAWTOOTHWAVECONFIG
DAC Exported Functions
LL_DAC_SetHighFrequencyMode
Configuration of DAC channels
LL_DAC_GetMode
LL_DAC_GetOutputBuffer
LL_DAC_GetOutputConnection
LL_DAC_GetOutputMode
LL_DAC_GetSampleAndHoldHoldTime
LL_DAC_GetSampleAndHoldRefreshTime
LL_DAC_GetSampleAndHoldSampleTime
LL_DAC_GetSignedFormat
LL_DAC_GetTriggerSource
LL_DAC_GetTrimmingValue
LL_DAC_GetWaveAutoGeneration
LL_DAC_GetWaveNoiseLFSR
LL_DAC_GetWaveSawtoothPolarity
LL_DAC_GetWaveSawtoothResetData
LL_DAC_GetWaveSawtoothResetTriggerSource
LL_DAC_GetWaveSawtoothStepData
LL_DAC_GetWaveSawtoothStepTriggerSource
LL_DAC_GetWaveTriangleAmplitude
LL_DAC_SetMode
LL_DAC_SetOutputBuffer
LL_DAC_SetOutputConnection
LL_DAC_SetOutputMode
LL_DAC_SetSampleAndHoldHoldTime
LL_DAC_SetSampleAndHoldRefreshTime
LL_DAC_SetSampleAndHoldSampleTime
LL_DAC_SetSignedFormat
LL_DAC_SetTriggerSource
LL_DAC_SetTrimmingValue
LL_DAC_SetWaveAutoGeneration
LL_DAC_SetWaveNoiseLFSR
LL_DAC_SetWaveSawtoothPolarity
LL_DAC_SetWaveSawtoothResetData
LL_DAC_SetWaveSawtoothResetTriggerSource
LL_DAC_SetWaveSawtoothStepData
LL_DAC_SetWaveSawtoothStepTriggerSource
LL_DAC_SetWaveTriangleAmplitude
DMA Management
LL_DAC_DisableDMAReq
LL_DAC_DMA_GetRegAddr
LL_DAC_EnableDMADoubleDataMode
LL_DAC_EnableDMAReq
LL_DAC_IsDMADoubleDataModeEnabled
LL_DAC_IsDMAReqEnabled
Operation on DAC channels
LL_DAC_ConvertData12RightAligned
LL_DAC_ConvertData8RightAligned
LL_DAC_ConvertDualData12LeftAligned
LL_DAC_ConvertDualData12RightAligned
LL_DAC_ConvertDualData8RightAligned
LL_DAC_Disable
LL_DAC_DisableTrigger
LL_DAC_Enable
LL_DAC_EnableTrigger
LL_DAC_IsEnabled
LL_DAC_IsReady
LL_DAC_IsTriggerEnabled
LL_DAC_RetrieveOutputData
LL_DAC_TrigSWConversion
LL_DAC_TrigSWConversion2
FLAG Management
LL_DAC_ClearFlag_DMAUDR2
LL_DAC_IsActiveFlag_BWST1
LL_DAC_IsActiveFlag_BWST2
LL_DAC_IsActiveFlag_CAL1
LL_DAC_IsActiveFlag_CAL2
LL_DAC_IsActiveFlag_DAC1RDY
LL_DAC_IsActiveFlag_DAC2RDY
LL_DAC_IsActiveFlag_DMAUDR1
LL_DAC_IsActiveFlag_DMAUDR2
LL_DAC_IsActiveFlag_DORSTAT1
LL_DAC_IsActiveFlag_DORSTAT2
IT management
LL_DAC_DisableIT_DMAUDR2
LL_DAC_EnableIT_DMAUDR1
LL_DAC_EnableIT_DMAUDR2
LL_DAC_IsEnabledIT_DMAUDR1
LL_DAC_IsEnabledIT_DMAUDR2
Initialization and de-initialization functions
LL_DAC_Init
LL_DAC_StructInit
DMA
DMA Private Constants
DMA_POSITION_CSELR_CXS
DMA Private Macros
IS_LL_DMA_DIRECTION
IS_LL_DMA_MEMORYDATASIZE
IS_LL_DMA_MEMORYINCMODE
IS_LL_DMA_MODE
IS_LL_DMA_NBDATA
IS_LL_DMA_PERIPHDATASIZE
IS_LL_DMA_PERIPHINCMODE
IS_LL_DMA_PERIPHREQUEST
IS_LL_DMA_PRIORITY
DMA Exported Init structure
DMA Exported Constants
LL_DMA_IFCR_CGIF2
LL_DMA_IFCR_CGIF3
LL_DMA_IFCR_CGIF4
LL_DMA_IFCR_CGIF5
LL_DMA_IFCR_CGIF6
LL_DMA_IFCR_CGIF7
LL_DMA_IFCR_CGIF8
LL_DMA_IFCR_CHTIF1
LL_DMA_IFCR_CHTIF2
LL_DMA_IFCR_CHTIF3
LL_DMA_IFCR_CHTIF4
LL_DMA_IFCR_CHTIF5
LL_DMA_IFCR_CHTIF6
LL_DMA_IFCR_CHTIF7
LL_DMA_IFCR_CHTIF8
LL_DMA_IFCR_CTCIF1
LL_DMA_IFCR_CTCIF2
LL_DMA_IFCR_CTCIF3
LL_DMA_IFCR_CTCIF4
LL_DMA_IFCR_CTCIF5
LL_DMA_IFCR_CTCIF6
LL_DMA_IFCR_CTCIF7
LL_DMA_IFCR_CTCIF8
LL_DMA_IFCR_CTEIF1
LL_DMA_IFCR_CTEIF2
LL_DMA_IFCR_CTEIF3
LL_DMA_IFCR_CTEIF4
LL_DMA_IFCR_CTEIF5
LL_DMA_IFCR_CTEIF6
LL_DMA_IFCR_CTEIF7
LL_DMA_IFCR_CTEIF8
Get Flags Defines
LL_DMA_ISR_GIF2
LL_DMA_ISR_GIF3
LL_DMA_ISR_GIF4
LL_DMA_ISR_GIF5
LL_DMA_ISR_GIF6
LL_DMA_ISR_GIF7
LL_DMA_ISR_GIF8
LL_DMA_ISR_HTIF1
LL_DMA_ISR_HTIF2
LL_DMA_ISR_HTIF3
LL_DMA_ISR_HTIF4
LL_DMA_ISR_HTIF5
LL_DMA_ISR_HTIF6
LL_DMA_ISR_HTIF7
LL_DMA_ISR_HTIF8
LL_DMA_ISR_TCIF1
LL_DMA_ISR_TCIF2
LL_DMA_ISR_TCIF3
LL_DMA_ISR_TCIF4
LL_DMA_ISR_TCIF5
LL_DMA_ISR_TCIF6
LL_DMA_ISR_TCIF7
LL_DMA_ISR_TCIF8
LL_DMA_ISR_TEIF1
LL_DMA_ISR_TEIF2
LL_DMA_ISR_TEIF3
LL_DMA_ISR_TEIF4
LL_DMA_ISR_TEIF5
LL_DMA_ISR_TEIF6
LL_DMA_ISR_TEIF7
LL_DMA_ISR_TEIF8
IT Defines
LL_DMA_CCR_TCIE
LL_DMA_CCR_TEIE
CHANNEL
LL_DMA_CHANNEL_2
LL_DMA_CHANNEL_3
LL_DMA_CHANNEL_4
LL_DMA_CHANNEL_5
LL_DMA_CHANNEL_6
LL_DMA_CHANNEL_7
LL_DMA_CHANNEL_8
LL_DMA_CHANNEL_ALL
Transfer Direction
LL_DMA_DIRECTION_MEMORY_TO_PERIPH
LL_DMA_DIRECTION_PERIPH_TO_MEMORY
Transfer mode
LL_DMA_MODE_NORMAL
Peripheral increment mode
LL_DMA_PERIPH_NOINCREMENT
Memory increment mode
LL_DMA_MEMORY_NOINCREMENT
Peripheral data alignment
LL_DMA_PDATAALIGN_HALFWORD
LL_DMA_PDATAALIGN_WORD
Memory data alignment
LL_DMA_MDATAALIGN_HALFWORD
LL_DMA_MDATAALIGN_WORD
Transfer Priority level
LL_DMA_PRIORITY_LOW
LL_DMA_PRIORITY_MEDIUM
LL_DMA_PRIORITY_VERYHIGH
DMA Exported Macros
LL_DMA_WriteReg
Convert DMAxChannely
__LL_DMA_GET_CHANNEL_INSTANCE
__LL_DMA_GET_INSTANCE
DMA Exported Functions
LL_DMA_ConfigTransfer
LL_DMA_DisableChannel
LL_DMA_EnableChannel
LL_DMA_GetChannelPriorityLevel
LL_DMA_GetDataLength
LL_DMA_GetDataTransferDirection
LL_DMA_GetM2MDstAddress
LL_DMA_GetM2MSrcAddress
LL_DMA_GetMemoryAddress
LL_DMA_GetMemoryIncMode
LL_DMA_GetMemorySize
LL_DMA_GetMode
LL_DMA_GetPeriphAddress
LL_DMA_GetPeriphIncMode
LL_DMA_GetPeriphRequest
LL_DMA_GetPeriphSize
LL_DMA_IsEnabledChannel
LL_DMA_SetChannelPriorityLevel
LL_DMA_SetDataLength
LL_DMA_SetDataTransferDirection
LL_DMA_SetM2MDstAddress
LL_DMA_SetM2MSrcAddress
LL_DMA_SetMemoryAddress
LL_DMA_SetMemoryIncMode
LL_DMA_SetMemorySize
LL_DMA_SetMode
LL_DMA_SetPeriphAddress
LL_DMA_SetPeriphIncMode
LL_DMA_SetPeriphRequest
LL_DMA_SetPeriphSize
FLAG_Management
LL_DMA_ClearFlag_GI2
LL_DMA_ClearFlag_GI3
LL_DMA_ClearFlag_GI4
LL_DMA_ClearFlag_GI5
LL_DMA_ClearFlag_GI6
LL_DMA_ClearFlag_GI7
LL_DMA_ClearFlag_GI8
LL_DMA_ClearFlag_HT1
LL_DMA_ClearFlag_HT2
LL_DMA_ClearFlag_HT3
LL_DMA_ClearFlag_HT4
LL_DMA_ClearFlag_HT5
LL_DMA_ClearFlag_HT6
LL_DMA_ClearFlag_HT7
LL_DMA_ClearFlag_HT8
LL_DMA_ClearFlag_TC1
LL_DMA_ClearFlag_TC2
LL_DMA_ClearFlag_TC3
LL_DMA_ClearFlag_TC4
LL_DMA_ClearFlag_TC5
LL_DMA_ClearFlag_TC6
LL_DMA_ClearFlag_TC7
LL_DMA_ClearFlag_TC8
LL_DMA_ClearFlag_TE1
LL_DMA_ClearFlag_TE2
LL_DMA_ClearFlag_TE3
LL_DMA_ClearFlag_TE4
LL_DMA_ClearFlag_TE5
LL_DMA_ClearFlag_TE6
LL_DMA_ClearFlag_TE7
LL_DMA_ClearFlag_TE8
LL_DMA_IsActiveFlag_GI1
LL_DMA_IsActiveFlag_GI2
LL_DMA_IsActiveFlag_GI3
LL_DMA_IsActiveFlag_GI4
LL_DMA_IsActiveFlag_GI5
LL_DMA_IsActiveFlag_GI6
LL_DMA_IsActiveFlag_GI7
LL_DMA_IsActiveFlag_GI8
LL_DMA_IsActiveFlag_HT1
LL_DMA_IsActiveFlag_HT2
LL_DMA_IsActiveFlag_HT3
LL_DMA_IsActiveFlag_HT4
LL_DMA_IsActiveFlag_HT5
LL_DMA_IsActiveFlag_HT6
LL_DMA_IsActiveFlag_HT7
LL_DMA_IsActiveFlag_HT8
LL_DMA_IsActiveFlag_TC1
LL_DMA_IsActiveFlag_TC2
LL_DMA_IsActiveFlag_TC3
LL_DMA_IsActiveFlag_TC4
LL_DMA_IsActiveFlag_TC5
LL_DMA_IsActiveFlag_TC6
LL_DMA_IsActiveFlag_TC7
LL_DMA_IsActiveFlag_TC8
LL_DMA_IsActiveFlag_TE1
LL_DMA_IsActiveFlag_TE2
LL_DMA_IsActiveFlag_TE3
LL_DMA_IsActiveFlag_TE4
LL_DMA_IsActiveFlag_TE5
LL_DMA_IsActiveFlag_TE6
LL_DMA_IsActiveFlag_TE7
LL_DMA_IsActiveFlag_TE8
IT_Management
LL_DMA_DisableIT_TC
LL_DMA_DisableIT_TE
LL_DMA_EnableIT_HT
LL_DMA_EnableIT_TC
LL_DMA_EnableIT_TE
LL_DMA_IsEnabledIT_HT
LL_DMA_IsEnabledIT_TC
LL_DMA_IsEnabledIT_TE
Initialization and de-initialization functions
LL_DMA_Init
LL_DMA_StructInit
DMAMUX
DMAMUX_RGCR_SIZE
DMAMUX Private Macros
DMAMUX Exported Constants
LL_DMAMUX_CFR_CSOF1
LL_DMAMUX_CFR_CSOF10
LL_DMAMUX_CFR_CSOF11
LL_DMAMUX_CFR_CSOF12
LL_DMAMUX_CFR_CSOF13
LL_DMAMUX_CFR_CSOF14
LL_DMAMUX_CFR_CSOF15
LL_DMAMUX_CFR_CSOF2
LL_DMAMUX_CFR_CSOF3
LL_DMAMUX_CFR_CSOF4
LL_DMAMUX_CFR_CSOF5
LL_DMAMUX_CFR_CSOF6
LL_DMAMUX_CFR_CSOF7
LL_DMAMUX_CFR_CSOF8
LL_DMAMUX_CFR_CSOF9
LL_DMAMUX_RGCFR_RGCOF0
LL_DMAMUX_RGCFR_RGCOF1
LL_DMAMUX_RGCFR_RGCOF2
LL_DMAMUX_RGCFR_RGCOF3
Get Flags Defines
LL_DMAMUX_CSR_SOF1
LL_DMAMUX_CSR_SOF10
LL_DMAMUX_CSR_SOF11
LL_DMAMUX_CSR_SOF12
LL_DMAMUX_CSR_SOF13
LL_DMAMUX_CSR_SOF14
LL_DMAMUX_CSR_SOF15
LL_DMAMUX_CSR_SOF2
LL_DMAMUX_CSR_SOF3
LL_DMAMUX_CSR_SOF4
LL_DMAMUX_CSR_SOF5
LL_DMAMUX_CSR_SOF6
LL_DMAMUX_CSR_SOF7
LL_DMAMUX_CSR_SOF8
LL_DMAMUX_CSR_SOF9
LL_DMAMUX_RGSR_RGOF0
LL_DMAMUX_RGSR_RGOF1
LL_DMAMUX_RGSR_RGOF2
LL_DMAMUX_RGSR_RGOF3
IT Defines
LL_DMAMUX_RGCR_RGOIE
Transfer request
LL_DMAMUX_REQ_ADC2
LL_DMAMUX_REQ_ADC3
LL_DMAMUX_REQ_ADC4
LL_DMAMUX_REQ_ADC5
LL_DMAMUX_REQ_AES_IN
LL_DMAMUX_REQ_AES_OUT
LL_DMAMUX_REQ_CORDIC_READ
LL_DMAMUX_REQ_CORDIC_WRITE
LL_DMAMUX_REQ_DAC1_CH1
LL_DMAMUX_REQ_DAC1_CH2
LL_DMAMUX_REQ_DAC2_CH1
LL_DMAMUX_REQ_DAC3_CH1
LL_DMAMUX_REQ_DAC3_CH2
LL_DMAMUX_REQ_DAC4_CH1
LL_DMAMUX_REQ_DAC4_CH2
LL_DMAMUX_REQ_FMAC_READ
LL_DMAMUX_REQ_FMAC_WRITE
LL_DMAMUX_REQ_GENERATOR0
LL_DMAMUX_REQ_GENERATOR1
LL_DMAMUX_REQ_GENERATOR2
LL_DMAMUX_REQ_GENERATOR3
LL_DMAMUX_REQ_HRTIM1_A
LL_DMAMUX_REQ_HRTIM1_B
LL_DMAMUX_REQ_HRTIM1_C
LL_DMAMUX_REQ_HRTIM1_D
LL_DMAMUX_REQ_HRTIM1_E
LL_DMAMUX_REQ_HRTIM1_F
LL_DMAMUX_REQ_HRTIM1_M
LL_DMAMUX_REQ_I2C1_RX
LL_DMAMUX_REQ_I2C1_TX
LL_DMAMUX_REQ_I2C2_RX
LL_DMAMUX_REQ_I2C2_TX
LL_DMAMUX_REQ_I2C3_RX
LL_DMAMUX_REQ_I2C3_TX
LL_DMAMUX_REQ_I2C4_RX
LL_DMAMUX_REQ_I2C4_TX
LL_DMAMUX_REQ_LPUART1_RX
LL_DMAMUX_REQ_LPUART1_TX
LL_DMAMUX_REQ_MEM2MEM
LL_DMAMUX_REQ_QSPI
LL_DMAMUX_REQ_SAI1_A
LL_DMAMUX_REQ_SAI1_B
LL_DMAMUX_REQ_SPI1_RX
LL_DMAMUX_REQ_SPI1_TX
LL_DMAMUX_REQ_SPI2_RX
LL_DMAMUX_REQ_SPI2_TX
LL_DMAMUX_REQ_SPI3_RX
LL_DMAMUX_REQ_SPI3_TX
LL_DMAMUX_REQ_SPI4_RX
LL_DMAMUX_REQ_SPI4_TX
LL_DMAMUX_REQ_TIM15_CH1
LL_DMAMUX_REQ_TIM15_COM
LL_DMAMUX_REQ_TIM15_TRIG
LL_DMAMUX_REQ_TIM15_UP
LL_DMAMUX_REQ_TIM16_CH1
LL_DMAMUX_REQ_TIM16_UP
LL_DMAMUX_REQ_TIM17_CH1
LL_DMAMUX_REQ_TIM17_UP
LL_DMAMUX_REQ_TIM1_CH1
LL_DMAMUX_REQ_TIM1_CH2
LL_DMAMUX_REQ_TIM1_CH3
LL_DMAMUX_REQ_TIM1_CH4
LL_DMAMUX_REQ_TIM1_COM
LL_DMAMUX_REQ_TIM1_TRIG
LL_DMAMUX_REQ_TIM1_UP
LL_DMAMUX_REQ_TIM20_CH1
LL_DMAMUX_REQ_TIM20_CH2
LL_DMAMUX_REQ_TIM20_CH3
LL_DMAMUX_REQ_TIM20_CH4
LL_DMAMUX_REQ_TIM20_COM
LL_DMAMUX_REQ_TIM20_TRIG
LL_DMAMUX_REQ_TIM20_UP
LL_DMAMUX_REQ_TIM2_CH1
LL_DMAMUX_REQ_TIM2_CH2
LL_DMAMUX_REQ_TIM2_CH3
LL_DMAMUX_REQ_TIM2_CH4
LL_DMAMUX_REQ_TIM2_UP
LL_DMAMUX_REQ_TIM3_CH1
LL_DMAMUX_REQ_TIM3_CH2
LL_DMAMUX_REQ_TIM3_CH3
LL_DMAMUX_REQ_TIM3_CH4
LL_DMAMUX_REQ_TIM3_TRIG
LL_DMAMUX_REQ_TIM3_UP
LL_DMAMUX_REQ_TIM4_CH1
LL_DMAMUX_REQ_TIM4_CH2
LL_DMAMUX_REQ_TIM4_CH3
LL_DMAMUX_REQ_TIM4_CH4
LL_DMAMUX_REQ_TIM4_UP
LL_DMAMUX_REQ_TIM5_CH1
LL_DMAMUX_REQ_TIM5_CH2
LL_DMAMUX_REQ_TIM5_CH3
LL_DMAMUX_REQ_TIM5_CH4
LL_DMAMUX_REQ_TIM5_TRIG
LL_DMAMUX_REQ_TIM5_UP
LL_DMAMUX_REQ_TIM6_UP
LL_DMAMUX_REQ_TIM7_UP
LL_DMAMUX_REQ_TIM8_CH1
LL_DMAMUX_REQ_TIM8_CH2
LL_DMAMUX_REQ_TIM8_CH3
LL_DMAMUX_REQ_TIM8_CH4
LL_DMAMUX_REQ_TIM8_COM
LL_DMAMUX_REQ_TIM8_TRIG
LL_DMAMUX_REQ_TIM8_UP
LL_DMAMUX_REQ_UART4_RX
LL_DMAMUX_REQ_UART4_TX
LL_DMAMUX_REQ_UART5_RX
LL_DMAMUX_REQ_UART5_TX
LL_DMAMUX_REQ_UCPD1_RX
LL_DMAMUX_REQ_UCPD1_TX
LL_DMAMUX_REQ_USART1_RX
LL_DMAMUX_REQ_USART1_TX
LL_DMAMUX_REQ_USART2_RX
LL_DMAMUX_REQ_USART2_TX
LL_DMAMUX_REQ_USART3_RX
LL_DMAMUX_REQ_USART3_TX
DMAMUX Channel
LL_DMAMUX_CHANNEL_1
LL_DMAMUX_CHANNEL_10
LL_DMAMUX_CHANNEL_11
LL_DMAMUX_CHANNEL_12
LL_DMAMUX_CHANNEL_13
LL_DMAMUX_CHANNEL_14
LL_DMAMUX_CHANNEL_15
LL_DMAMUX_CHANNEL_2
LL_DMAMUX_CHANNEL_3
LL_DMAMUX_CHANNEL_4
LL_DMAMUX_CHANNEL_5
LL_DMAMUX_CHANNEL_6
LL_DMAMUX_CHANNEL_7
LL_DMAMUX_CHANNEL_8
LL_DMAMUX_CHANNEL_9
Synchronization Signal Polarity
LL_DMAMUX_SYNC_POL_FALLING
LL_DMAMUX_SYNC_POL_RISING
LL_DMAMUX_SYNC_POL_RISING_FALLING
Synchronization Signal Event
LL_DMAMUX_SYNC_DMAMUX_CH1
LL_DMAMUX_SYNC_DMAMUX_CH2
LL_DMAMUX_SYNC_DMAMUX_CH3
LL_DMAMUX_SYNC_EXTI_LINE0
LL_DMAMUX_SYNC_EXTI_LINE1
LL_DMAMUX_SYNC_EXTI_LINE10
LL_DMAMUX_SYNC_EXTI_LINE11
LL_DMAMUX_SYNC_EXTI_LINE12
LL_DMAMUX_SYNC_EXTI_LINE13
LL_DMAMUX_SYNC_EXTI_LINE14
LL_DMAMUX_SYNC_EXTI_LINE15
LL_DMAMUX_SYNC_EXTI_LINE2
LL_DMAMUX_SYNC_EXTI_LINE3
LL_DMAMUX_SYNC_EXTI_LINE4
LL_DMAMUX_SYNC_EXTI_LINE5
LL_DMAMUX_SYNC_EXTI_LINE6
LL_DMAMUX_SYNC_EXTI_LINE7
LL_DMAMUX_SYNC_EXTI_LINE8
LL_DMAMUX_SYNC_EXTI_LINE9
LL_DMAMUX_SYNC_LPTIM1_OUT
Request Generator Channel
LL_DMAMUX_REQ_GEN_1
LL_DMAMUX_REQ_GEN_2
LL_DMAMUX_REQ_GEN_3
External Request Signal Generation Polarity
LL_DMAMUX_REQ_GEN_POL_FALLING
LL_DMAMUX_REQ_GEN_POL_RISING
LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
External Request Signal Generation
LL_DMAMUX_REQ_GEN_DMAMUX_CH1
LL_DMAMUX_REQ_GEN_DMAMUX_CH2
LL_DMAMUX_REQ_GEN_DMAMUX_CH3
LL_DMAMUX_REQ_GEN_EXTI_LINE0
LL_DMAMUX_REQ_GEN_EXTI_LINE1
LL_DMAMUX_REQ_GEN_EXTI_LINE10
LL_DMAMUX_REQ_GEN_EXTI_LINE11
LL_DMAMUX_REQ_GEN_EXTI_LINE12
LL_DMAMUX_REQ_GEN_EXTI_LINE13
LL_DMAMUX_REQ_GEN_EXTI_LINE14
LL_DMAMUX_REQ_GEN_EXTI_LINE15
LL_DMAMUX_REQ_GEN_EXTI_LINE2
LL_DMAMUX_REQ_GEN_EXTI_LINE3
LL_DMAMUX_REQ_GEN_EXTI_LINE4
LL_DMAMUX_REQ_GEN_EXTI_LINE5
LL_DMAMUX_REQ_GEN_EXTI_LINE6
LL_DMAMUX_REQ_GEN_EXTI_LINE7
LL_DMAMUX_REQ_GEN_EXTI_LINE8
LL_DMAMUX_REQ_GEN_EXTI_LINE9
LL_DMAMUX_REQ_GEN_LPTIM1_OUT
DMAMUX Exported Macros
LL_DMAMUX_WriteReg
DMAMUX Exported Functions
LL_DMAMUX_DisableRequestGen
LL_DMAMUX_DisableSync
LL_DMAMUX_EnableEventGeneration
LL_DMAMUX_EnableRequestGen
LL_DMAMUX_EnableSync
LL_DMAMUX_GetGenRequestNb
LL_DMAMUX_GetRequestGenPolarity
LL_DMAMUX_GetRequestID
LL_DMAMUX_GetRequestSignalID
LL_DMAMUX_GetSyncID
LL_DMAMUX_GetSyncPolarity
LL_DMAMUX_GetSyncRequestNb
LL_DMAMUX_IsEnabledEventGeneration
LL_DMAMUX_IsEnabledRequestGen
LL_DMAMUX_IsEnabledSync
LL_DMAMUX_SetGenRequestNb
LL_DMAMUX_SetRequestGenPolarity
LL_DMAMUX_SetRequestID
LL_DMAMUX_SetRequestSignalID
LL_DMAMUX_SetSyncID
LL_DMAMUX_SetSyncPolarity
LL_DMAMUX_SetSyncRequestNb
FLAG_Management
LL_DMAMUX_ClearFlag_RGO1
LL_DMAMUX_ClearFlag_RGO2
LL_DMAMUX_ClearFlag_RGO3
LL_DMAMUX_ClearFlag_SO0
LL_DMAMUX_ClearFlag_SO1
LL_DMAMUX_ClearFlag_SO10
LL_DMAMUX_ClearFlag_SO11
LL_DMAMUX_ClearFlag_SO12
LL_DMAMUX_ClearFlag_SO13
LL_DMAMUX_ClearFlag_SO14
LL_DMAMUX_ClearFlag_SO15
LL_DMAMUX_ClearFlag_SO2
LL_DMAMUX_ClearFlag_SO3
LL_DMAMUX_ClearFlag_SO4
LL_DMAMUX_ClearFlag_SO5
LL_DMAMUX_ClearFlag_SO6
LL_DMAMUX_ClearFlag_SO7
LL_DMAMUX_ClearFlag_SO8
LL_DMAMUX_ClearFlag_SO9
LL_DMAMUX_IsActiveFlag_RGO0
LL_DMAMUX_IsActiveFlag_RGO1
LL_DMAMUX_IsActiveFlag_RGO2
LL_DMAMUX_IsActiveFlag_RGO3
LL_DMAMUX_IsActiveFlag_SO0
LL_DMAMUX_IsActiveFlag_SO1
LL_DMAMUX_IsActiveFlag_SO10
LL_DMAMUX_IsActiveFlag_SO11
LL_DMAMUX_IsActiveFlag_SO12
LL_DMAMUX_IsActiveFlag_SO13
LL_DMAMUX_IsActiveFlag_SO14
LL_DMAMUX_IsActiveFlag_SO15
LL_DMAMUX_IsActiveFlag_SO2
LL_DMAMUX_IsActiveFlag_SO3
LL_DMAMUX_IsActiveFlag_SO4
LL_DMAMUX_IsActiveFlag_SO5
LL_DMAMUX_IsActiveFlag_SO6
LL_DMAMUX_IsActiveFlag_SO7
LL_DMAMUX_IsActiveFlag_SO8
LL_DMAMUX_IsActiveFlag_SO9
IT_Management
LL_DMAMUX_DisableIT_SO
LL_DMAMUX_EnableIT_RGO
LL_DMAMUX_EnableIT_SO
LL_DMAMUX_IsEnabledIT_RGO
LL_DMAMUX_IsEnabledIT_SO
EXTI
IS_LL_EXTI_LINE_32_63
IS_LL_EXTI_MODE
IS_LL_EXTI_TRIGGER
EXTI Exported Init structure
EXTI Exported Constants
LL_EXTI_LINE_1
LL_EXTI_LINE_10
LL_EXTI_LINE_11
LL_EXTI_LINE_12
LL_EXTI_LINE_13
LL_EXTI_LINE_14
LL_EXTI_LINE_15
LL_EXTI_LINE_16
LL_EXTI_LINE_17
LL_EXTI_LINE_18
LL_EXTI_LINE_19
LL_EXTI_LINE_2
LL_EXTI_LINE_20
LL_EXTI_LINE_21
LL_EXTI_LINE_22
LL_EXTI_LINE_23
LL_EXTI_LINE_24
LL_EXTI_LINE_25
LL_EXTI_LINE_26
LL_EXTI_LINE_27
LL_EXTI_LINE_28
LL_EXTI_LINE_29
LL_EXTI_LINE_3
LL_EXTI_LINE_30
LL_EXTI_LINE_31
LL_EXTI_LINE_32
LL_EXTI_LINE_33
LL_EXTI_LINE_34
LL_EXTI_LINE_35
LL_EXTI_LINE_36
LL_EXTI_LINE_37
LL_EXTI_LINE_38
LL_EXTI_LINE_39
LL_EXTI_LINE_4
LL_EXTI_LINE_40
LL_EXTI_LINE_41
LL_EXTI_LINE_42
LL_EXTI_LINE_5
LL_EXTI_LINE_6
LL_EXTI_LINE_7
LL_EXTI_LINE_8
LL_EXTI_LINE_9
LL_EXTI_LINE_ALL
LL_EXTI_LINE_ALL_0_31
LL_EXTI_LINE_ALL_32_63
LL_EXTI_LINE_NONE
Mode
LL_EXTI_MODE_IT
LL_EXTI_MODE_IT_EVENT
Edge Trigger
LL_EXTI_TRIGGER_NONE
LL_EXTI_TRIGGER_RISING
LL_EXTI_TRIGGER_RISING_FALLING
EXTI Exported Macros
LL_EXTI_WriteReg
EXTI Exported Functions
LL_EXTI_DisableIT_32_63
LL_EXTI_EnableIT_0_31
LL_EXTI_EnableIT_32_63
LL_EXTI_IsEnabledIT_0_31
LL_EXTI_IsEnabledIT_32_63
Event_Management
LL_EXTI_DisableEvent_32_63
LL_EXTI_EnableEvent_0_31
LL_EXTI_EnableEvent_32_63
LL_EXTI_IsEnabledEvent_0_31
LL_EXTI_IsEnabledEvent_32_63
Rising_Trigger_Management
LL_EXTI_DisableRisingTrig_32_63
LL_EXTI_EnableRisingTrig_0_31
LL_EXTI_EnableRisingTrig_32_63
LL_EXTI_IsEnabledRisingTrig_0_31
LL_EXTI_IsEnabledRisingTrig_32_63
Falling_Trigger_Management
LL_EXTI_DisableFallingTrig_32_63
LL_EXTI_EnableFallingTrig_0_31
LL_EXTI_EnableFallingTrig_32_63
LL_EXTI_IsEnabledFallingTrig_0_31
LL_EXTI_IsEnabledFallingTrig_32_63
Software_Interrupt_Management
LL_EXTI_GenerateSWI_32_63
Flag_Management
LL_EXTI_ClearFlag_32_63
LL_EXTI_IsActiveFlag_0_31
LL_EXTI_IsActiveFlag_32_63
LL_EXTI_ReadFlag_0_31
LL_EXTI_ReadFlag_32_63
Initialization and de-initialization functions
LL_EXTI_Init
LL_EXTI_StructInit
FMAC
LL_FMAC_SR_SAT
LL_FMAC_SR_UNFL
LL_FMAC_SR_X1FULL
LL_FMAC_SR_YEMPTY
IT Defines
LL_FMAC_CR_RIEN
LL_FMAC_CR_SATIEN
LL_FMAC_CR_UNFLIEN
LL_FMAC_CR_WIEN
FMAC watermarks
LL_FMAC_WM_1_THRESHOLD_2
LL_FMAC_WM_2_THRESHOLD_4
LL_FMAC_WM_3_THRESHOLD_8
FMAC functions
LL_FMAC_FUNC_IIR_DIRECT_FORM_1
LL_FMAC_FUNC_LOAD_X1
LL_FMAC_FUNC_LOAD_X2
LL_FMAC_FUNC_LOAD_Y
FMAC processing
LL_FMAC_PROCESSING_STOP
FMAC Exported Macros
LL_FMAC_WriteReg
FMAC Exported Functions
LL_FMAC_ConfigX1
LL_FMAC_ConfigX2
LL_FMAC_ConfigY
LL_FMAC_DisableClipping
LL_FMAC_DisableStart
LL_FMAC_EnableClipping
LL_FMAC_EnableStart
LL_FMAC_GetFunction
LL_FMAC_GetParamP
LL_FMAC_GetParamQ
LL_FMAC_GetParamR
LL_FMAC_GetX1Base
LL_FMAC_GetX1BufferSize
LL_FMAC_GetX1FullWatermark
LL_FMAC_GetX2Base
LL_FMAC_GetX2BufferSize
LL_FMAC_GetYBase
LL_FMAC_GetYBufferSize
LL_FMAC_GetYEmptyWatermark
LL_FMAC_IsEnabledClipping
LL_FMAC_IsEnabledStart
LL_FMAC_SetFunction
LL_FMAC_SetParamP
LL_FMAC_SetParamQ
LL_FMAC_SetParamR
LL_FMAC_SetX1Base
LL_FMAC_SetX1BufferSize
LL_FMAC_SetX1FullWatermark
LL_FMAC_SetX2Base
LL_FMAC_SetX2BufferSize
LL_FMAC_SetYBase
LL_FMAC_SetYBufferSize
LL_FMAC_SetYEmptyWatermark
Reset_Management
LL_FMAC_IsEnabledReset
DMA_Management
LL_FMAC_DisableDMAReq_WRITE
LL_FMAC_EnableDMAReq_READ
LL_FMAC_EnableDMAReq_WRITE
LL_FMAC_IsEnabledDMAReq_READ
LL_FMAC_IsEnabledDMAReq_WRITE
IT_Management
LL_FMAC_DisableIT_RD
LL_FMAC_DisableIT_SAT
LL_FMAC_DisableIT_UNFL
LL_FMAC_DisableIT_WR
LL_FMAC_EnableIT_OVFL
LL_FMAC_EnableIT_RD
LL_FMAC_EnableIT_SAT
LL_FMAC_EnableIT_UNFL
LL_FMAC_EnableIT_WR
LL_FMAC_IsEnabledIT_OVFL
LL_FMAC_IsEnabledIT_RD
LL_FMAC_IsEnabledIT_SAT
LL_FMAC_IsEnabledIT_UNFL
LL_FMAC_IsEnabledIT_WR
FLAG_Management
LL_FMAC_IsActiveFlag_SAT
LL_FMAC_IsActiveFlag_UNFL
LL_FMAC_IsActiveFlag_X1FULL
LL_FMAC_IsActiveFlag_YEMPTY
Data_Management
LL_FMAC_WriteData
Initialization and de-initialization functions
LL_FMAC_Init
GPIO
IS_LL_GPIO_MODE
IS_LL_GPIO_OUTPUT_TYPE
IS_LL_GPIO_PIN
IS_LL_GPIO_PULL
IS_LL_GPIO_SPEED
GPIO Exported Init structures
GPIO Exported Constants
LL_GPIO_PIN_1
LL_GPIO_PIN_10
LL_GPIO_PIN_11
LL_GPIO_PIN_12
LL_GPIO_PIN_13
LL_GPIO_PIN_14
LL_GPIO_PIN_15
LL_GPIO_PIN_2
LL_GPIO_PIN_3
LL_GPIO_PIN_4
LL_GPIO_PIN_5
LL_GPIO_PIN_6
LL_GPIO_PIN_7
LL_GPIO_PIN_8
LL_GPIO_PIN_9
LL_GPIO_PIN_ALL
Mode
LL_GPIO_MODE_ANALOG
LL_GPIO_MODE_INPUT
LL_GPIO_MODE_OUTPUT
Output Type
LL_GPIO_OUTPUT_PUSHPULL
Output Speed
LL_GPIO_SPEED_FREQ_LOW
LL_GPIO_SPEED_FREQ_MEDIUM
LL_GPIO_SPEED_FREQ_VERY_HIGH
Pull Up Pull Down
LL_GPIO_PULL_NO
LL_GPIO_PULL_UP
Alternate Function
LL_GPIO_AF_1
LL_GPIO_AF_10
LL_GPIO_AF_11
LL_GPIO_AF_12
LL_GPIO_AF_13
LL_GPIO_AF_14
LL_GPIO_AF_15
LL_GPIO_AF_2
LL_GPIO_AF_3
LL_GPIO_AF_4
LL_GPIO_AF_5
LL_GPIO_AF_6
LL_GPIO_AF_7
LL_GPIO_AF_8
LL_GPIO_AF_9
Defines
LL_GPIO_SPEED_HIGH
LL_GPIO_SPEED_LOW
LL_GPIO_SPEED_MEDIUM
GPIO Exported Macros
LL_GPIO_WriteReg
GPIO Exported Functions
LL_GPIO_GetAFPin_8_15
LL_GPIO_GetPinMode
LL_GPIO_GetPinOutputType
LL_GPIO_GetPinPull
LL_GPIO_GetPinSpeed
LL_GPIO_IsAnyPinLocked
LL_GPIO_IsPinLocked
LL_GPIO_LockPin
LL_GPIO_SetAFPin_0_7
LL_GPIO_SetAFPin_8_15
LL_GPIO_SetPinMode
LL_GPIO_SetPinOutputType
LL_GPIO_SetPinPull
LL_GPIO_SetPinSpeed
Data Access
LL_GPIO_IsOutputPinSet
LL_GPIO_ReadInputPort
LL_GPIO_ReadOutputPort
LL_GPIO_ResetOutputPin
LL_GPIO_SetOutputPin
LL_GPIO_TogglePin
LL_GPIO_WriteOutputPort
Initialization and de-initialization functions
LL_GPIO_Init
LL_GPIO_StructInit
HRTIM
REG_MASK_TAB_ADCUR
REG_MASK_TAB_CPT
REG_MASK_TAB_INTLVD
REG_MASK_TAB_UPDATEGATING
REG_MASK_TAB_UPDATETRIG
REG_OFFSET_TAB_ADCER
REG_OFFSET_TAB_ADCPSx
REG_OFFSET_TAB_ADCUR
REG_OFFSET_TAB_EECR
REG_OFFSET_TAB_FLTINR
REG_OFFSET_TAB_OUTxR
REG_OFFSET_TAB_SETxR
REG_OFFSET_TAB_TIMER
REG_SHIFT_TAB_ADCER
REG_SHIFT_TAB_ADCUR
REG_SHIFT_TAB_CPT
REG_SHIFT_TAB_EExSRC
REG_SHIFT_TAB_FLTx
REG_SHIFT_TAB_FLTxCNT
REG_SHIFT_TAB_FLTxE
REG_SHIFT_TAB_FLTxF
REG_SHIFT_TAB_INTLVD
REG_SHIFT_TAB_OUTxR
REG_SHIFT_TAB_OxSTAT
REG_SHIFT_TAB_UPDATEGATING
REG_SHIFT_TAB_UPDATETRIG
HRTIM Private Constants
HRTIM_CR1_UDIS_MASK
HRTIM_CR2_SWAP_MASK
HRTIM_CR2_SWRST_MASK
HRTIM_CR2_SWUPD_MASK
HRTIM_EE_CONFIG_MASK
HRTIM_FLT_CONFIG_MASK
HRTIM_FLT_SRC_1_MASK
HRTIM_OENR_ODIS_MASK
HRTIM_OENR_OEN_MASK
HRTIM_OUT_CONFIG_MASK
HRTIM Exported Constants
LL_HRTIM_ISR_DLLRDY
LL_HRTIM_ISR_FLT1
LL_HRTIM_ISR_FLT2
LL_HRTIM_ISR_FLT3
LL_HRTIM_ISR_FLT4
LL_HRTIM_ISR_FLT5
LL_HRTIM_ISR_FLT6
LL_HRTIM_ISR_SYSFLT
LL_HRTIM_MISR_MCMP1
LL_HRTIM_MISR_MCMP2
LL_HRTIM_MISR_MCMP3
LL_HRTIM_MISR_MCMP4
LL_HRTIM_MISR_MREP
LL_HRTIM_MISR_MUPD
LL_HRTIM_MISR_SYNC
LL_HRTIM_TIMISR_CMP1
LL_HRTIM_TIMISR_CMP2
LL_HRTIM_TIMISR_CMP3
LL_HRTIM_TIMISR_CMP4
LL_HRTIM_TIMISR_CPT1
LL_HRTIM_TIMISR_CPT2
LL_HRTIM_TIMISR_DLYPRT
LL_HRTIM_TIMISR_REP
LL_HRTIM_TIMISR_RST
LL_HRTIM_TIMISR_RST1
LL_HRTIM_TIMISR_RST2
LL_HRTIM_TIMISR_SET1
LL_HRTIM_TIMISR_SET2
LL_HRTIM_TIMISR_UPD
IT Defines
LL_HRTIM_IER_DLLRDYIE
LL_HRTIM_IER_FLT1IE
LL_HRTIM_IER_FLT2IE
LL_HRTIM_IER_FLT3IE
LL_HRTIM_IER_FLT4IE
LL_HRTIM_IER_FLT5IE
LL_HRTIM_IER_FLT6IE
LL_HRTIM_IER_SYSFLTIE
LL_HRTIM_MDIER_MCMP1IE
LL_HRTIM_MDIER_MCMP2IE
LL_HRTIM_MDIER_MCMP3IE
LL_HRTIM_MDIER_MCMP4IE
LL_HRTIM_MDIER_MREPIE
LL_HRTIM_MDIER_MUPDIE
LL_HRTIM_MDIER_SYNCIE
LL_HRTIM_TIMDIER_CMP1IE
LL_HRTIM_TIMDIER_CMP2IE
LL_HRTIM_TIMDIER_CMP3IE
LL_HRTIM_TIMDIER_CMP4IE
LL_HRTIM_TIMDIER_CPT1IE
LL_HRTIM_TIMDIER_CPT2IE
LL_HRTIM_TIMDIER_DLYPRTIE
LL_HRTIM_TIMDIER_REPIE
LL_HRTIM_TIMDIER_RST1IE
LL_HRTIM_TIMDIER_RST2IE
LL_HRTIM_TIMDIER_RSTIE
LL_HRTIM_TIMDIER_SET1IE
LL_HRTIM_TIMDIER_SET2IE
LL_HRTIM_TIMDIER_UPDIE
SYNCHRONIZATION INPUT SOURCE
LL_HRTIM_SYNCIN_SRC_NONE
LL_HRTIM_SYNCIN_SRC_TIM_EVENT
SYNCHRONIZATION OUTPUT SOURCE
LL_HRTIM_SYNCOUT_SRC_MASTER_START
LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
LL_HRTIM_SYNCOUT_SRC_TIMA_START
SYNCHRONIZATION OUTPUT POLARITY
LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
LL_HRTIM_SYNCOUT_POSITIVE_PULSE
TIMER ID
LL_HRTIM_TIMER_ALL
LL_HRTIM_TIMER_B
LL_HRTIM_TIMER_C
LL_HRTIM_TIMER_D
LL_HRTIM_TIMER_E
LL_HRTIM_TIMER_F
LL_HRTIM_TIMER_MASTER
LL_HRTIM_TIMER_NONE
LL_HRTIM_TIMER_X
OUTPUT ID
LL_HRTIM_OUTPUT_TA2
LL_HRTIM_OUTPUT_TB1
LL_HRTIM_OUTPUT_TB2
LL_HRTIM_OUTPUT_TC1
LL_HRTIM_OUTPUT_TC2
LL_HRTIM_OUTPUT_TD1
LL_HRTIM_OUTPUT_TD2
LL_HRTIM_OUTPUT_TE1
LL_HRTIM_OUTPUT_TE2
LL_HRTIM_OUTPUT_TF1
LL_HRTIM_OUTPUT_TF2
COMPARE UNIT ID
LL_HRTIM_COMPAREUNIT_4
CAPTURE UNIT ID
LL_HRTIM_CAPTUREUNIT_2
FAULT ID
LL_HRTIM_FAULT_2
LL_HRTIM_FAULT_3
LL_HRTIM_FAULT_4
LL_HRTIM_FAULT_5
LL_HRTIM_FAULT_6
EXTERNAL EVENT ID
LL_HRTIM_EVENT_10
LL_HRTIM_EVENT_2
LL_HRTIM_EVENT_3
LL_HRTIM_EVENT_4
LL_HRTIM_EVENT_5
LL_HRTIM_EVENT_6
LL_HRTIM_EVENT_7
LL_HRTIM_EVENT_8
LL_HRTIM_EVENT_9
OUTPUT STATE
LL_HRTIM_OUTPUTSTATE_IDLE
LL_HRTIM_OUTPUTSTATE_RUN
ADC TRIGGER
LL_HRTIM_ADCTRIG_10
LL_HRTIM_ADCTRIG_2
LL_HRTIM_ADCTRIG_3
LL_HRTIM_ADCTRIG_4
LL_HRTIM_ADCTRIG_5
LL_HRTIM_ADCTRIG_6
LL_HRTIM_ADCTRIG_7
LL_HRTIM_ADCTRIG_8
LL_HRTIM_ADCTRIG_9
ADC TRIGGER UPDATE
LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
ADC TRIGGER 1/3 SOURCE
LL_HRTIM_ADCTRIG_SRC13_EEV2
LL_HRTIM_ADCTRIG_SRC13_EEV3
LL_HRTIM_ADCTRIG_SRC13_EEV4
LL_HRTIM_ADCTRIG_SRC13_EEV5
LL_HRTIM_ADCTRIG_SRC13_MCMP1
LL_HRTIM_ADCTRIG_SRC13_MCMP2
LL_HRTIM_ADCTRIG_SRC13_MCMP3
LL_HRTIM_ADCTRIG_SRC13_MCMP4
LL_HRTIM_ADCTRIG_SRC13_MPER
LL_HRTIM_ADCTRIG_SRC13_NONE
LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
LL_HRTIM_ADCTRIG_SRC13_TIMAPER
LL_HRTIM_ADCTRIG_SRC13_TIMARST
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMBPER
LL_HRTIM_ADCTRIG_SRC13_TIMBRST
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMCPER
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMDPER
LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
LL_HRTIM_ADCTRIG_SRC13_TIMEPER
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMFPER
LL_HRTIM_ADCTRIG_SRC13_TIMFRST
ADC TRIGGER 2/4 SOURCE
LL_HRTIM_ADCTRIG_SRC24_EEV6
LL_HRTIM_ADCTRIG_SRC24_EEV7
LL_HRTIM_ADCTRIG_SRC24_EEV8
LL_HRTIM_ADCTRIG_SRC24_EEV9
LL_HRTIM_ADCTRIG_SRC24_MCMP1
LL_HRTIM_ADCTRIG_SRC24_MCMP2
LL_HRTIM_ADCTRIG_SRC24_MCMP3
LL_HRTIM_ADCTRIG_SRC24_MCMP4
LL_HRTIM_ADCTRIG_SRC24_MPER
LL_HRTIM_ADCTRIG_SRC24_NONE
LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
LL_HRTIM_ADCTRIG_SRC24_TIMAPER
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMBPER
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMCPER
LL_HRTIM_ADCTRIG_SRC24_TIMCRST
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMDPER
LL_HRTIM_ADCTRIG_SRC24_TIMDRST
LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
LL_HRTIM_ADCTRIG_SRC24_TIMERST
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMFPER
HRTIM ADC TRIGGER SELECTION
LL_HRTIM_ADCTRIG_SRC579_EEV2
LL_HRTIM_ADCTRIG_SRC579_EEV3
LL_HRTIM_ADCTRIG_SRC579_EEV4
LL_HRTIM_ADCTRIG_SRC579_EEV5
LL_HRTIM_ADCTRIG_SRC579_MCMP1
LL_HRTIM_ADCTRIG_SRC579_MCMP2
LL_HRTIM_ADCTRIG_SRC579_MCMP3
LL_HRTIM_ADCTRIG_SRC579_MCMP4
LL_HRTIM_ADCTRIG_SRC579_MPER
LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIME_PER
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
LL_HRTIM_ADCTRIG_SRC6810_EEV10
LL_HRTIM_ADCTRIG_SRC6810_EEV6
LL_HRTIM_ADCTRIG_SRC6810_EEV7
LL_HRTIM_ADCTRIG_SRC6810_EEV8
LL_HRTIM_ADCTRIG_SRC6810_EEV9
LL_HRTIM_ADCTRIG_SRC6810_MCMP1
LL_HRTIM_ADCTRIG_SRC6810_MCMP2
LL_HRTIM_ADCTRIG_SRC6810_MCMP3
LL_HRTIM_ADCTRIG_SRC6810_MCMP4
LL_HRTIM_ADCTRIG_SRC6810_MPER
LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
DLL CALIBRATION MODE
LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
DLL CALIBRATION RATE
LL_HRTIM_DLLCALIBRATION_RATE_1
LL_HRTIM_DLLCALIBRATION_RATE_2
LL_HRTIM_DLLCALIBRATION_RATE_3
PRESCALER RATIO
LL_HRTIM_PRESCALERRATIO_DIV2
LL_HRTIM_PRESCALERRATIO_DIV4
LL_HRTIM_PRESCALERRATIO_MUL16
LL_HRTIM_PRESCALERRATIO_MUL2
LL_HRTIM_PRESCALERRATIO_MUL32
LL_HRTIM_PRESCALERRATIO_MUL4
LL_HRTIM_PRESCALERRATIO_MUL8
COUNTER MODE
LL_HRTIM_MODE_RETRIGGERABLE
LL_HRTIM_MODE_SINGLESHOT
DAC TRIGGER
LL_HRTIM_DACTRIG_DACTRIGOUT_2
LL_HRTIM_DACTRIG_DACTRIGOUT_3
LL_HRTIM_DACTRIG_NONE
UPDATE TRIGGER
LL_HRTIM_UPDATETRIG_NONE
LL_HRTIM_UPDATETRIG_REPETITION
LL_HRTIM_UPDATETRIG_RESET
LL_HRTIM_UPDATETRIG_TIMER_A
LL_HRTIM_UPDATETRIG_TIMER_B
LL_HRTIM_UPDATETRIG_TIMER_C
LL_HRTIM_UPDATETRIG_TIMER_D
LL_HRTIM_UPDATETRIG_TIMER_E
LL_HRTIM_UPDATETRIG_TIMER_F
UPDATE GATING
LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
LL_HRTIM_UPDATEGATING_INDEPENDENT
LL_HRTIM_UPDATEGATING_UPDEN1
LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
LL_HRTIM_UPDATEGATING_UPDEN2
LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
LL_HRTIM_UPDATEGATING_UPDEN3
LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
COMPARE MODE
LL_HRTIM_COMPAREMODE_DELAY_CMP3
LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
LL_HRTIM_COMPAREMODE_REGULAR
RESET TRIGGER
LL_HRTIM_RESETTRIG_CMP4
LL_HRTIM_RESETTRIG_EEV_1
LL_HRTIM_RESETTRIG_EEV_10
LL_HRTIM_RESETTRIG_EEV_2
LL_HRTIM_RESETTRIG_EEV_3
LL_HRTIM_RESETTRIG_EEV_4
LL_HRTIM_RESETTRIG_EEV_5
LL_HRTIM_RESETTRIG_EEV_6
LL_HRTIM_RESETTRIG_EEV_7
LL_HRTIM_RESETTRIG_EEV_8
LL_HRTIM_RESETTRIG_EEV_9
LL_HRTIM_RESETTRIG_MASTER_CMP1
LL_HRTIM_RESETTRIG_MASTER_CMP2
LL_HRTIM_RESETTRIG_MASTER_CMP3
LL_HRTIM_RESETTRIG_MASTER_CMP4
LL_HRTIM_RESETTRIG_MASTER_PER
LL_HRTIM_RESETTRIG_NONE
LL_HRTIM_RESETTRIG_OTHER1_CMP1
LL_HRTIM_RESETTRIG_OTHER1_CMP2
LL_HRTIM_RESETTRIG_OTHER1_CMP4
LL_HRTIM_RESETTRIG_OTHER2_CMP1
LL_HRTIM_RESETTRIG_OTHER2_CMP2
LL_HRTIM_RESETTRIG_OTHER2_CMP4
LL_HRTIM_RESETTRIG_OTHER3_CMP1
LL_HRTIM_RESETTRIG_OTHER3_CMP2
LL_HRTIM_RESETTRIG_OTHER3_CMP4
LL_HRTIM_RESETTRIG_OTHER4_CMP1
LL_HRTIM_RESETTRIG_OTHER4_CMP2
LL_HRTIM_RESETTRIG_OTHER4_CMP4
LL_HRTIM_RESETTRIG_OTHER5_CMP1
LL_HRTIM_RESETTRIG_OTHER5_CMP2
LL_HRTIM_RESETTRIG_UPDATE
CAPTURE TRIGGER
LL_HRTIM_CAPTURETRIG_EEV_10
LL_HRTIM_CAPTURETRIG_EEV_2
LL_HRTIM_CAPTURETRIG_EEV_3
LL_HRTIM_CAPTURETRIG_EEV_4
LL_HRTIM_CAPTURETRIG_EEV_5
LL_HRTIM_CAPTURETRIG_EEV_6
LL_HRTIM_CAPTURETRIG_EEV_7
LL_HRTIM_CAPTURETRIG_EEV_8
LL_HRTIM_CAPTURETRIG_EEV_9
LL_HRTIM_CAPTURETRIG_NONE
LL_HRTIM_CAPTURETRIG_SW
LL_HRTIM_CAPTURETRIG_TA1_RESET
LL_HRTIM_CAPTURETRIG_TA1_SET
LL_HRTIM_CAPTURETRIG_TB1_RESET
LL_HRTIM_CAPTURETRIG_TB1_SET
LL_HRTIM_CAPTURETRIG_TC1_RESET
LL_HRTIM_CAPTURETRIG_TC1_SET
LL_HRTIM_CAPTURETRIG_TD1_RESET
LL_HRTIM_CAPTURETRIG_TD1_SET
LL_HRTIM_CAPTURETRIG_TE1_RESET
LL_HRTIM_CAPTURETRIG_TE1_SET
LL_HRTIM_CAPTURETRIG_TF1_RESET
LL_HRTIM_CAPTURETRIG_TF1_SET
LL_HRTIM_CAPTURETRIG_TIMA_CMP1
LL_HRTIM_CAPTURETRIG_TIMA_CMP2
LL_HRTIM_CAPTURETRIG_TIMB_CMP1
LL_HRTIM_CAPTURETRIG_TIMB_CMP2
LL_HRTIM_CAPTURETRIG_TIMC_CMP1
LL_HRTIM_CAPTURETRIG_TIMC_CMP2
LL_HRTIM_CAPTURETRIG_TIMD_CMP1
LL_HRTIM_CAPTURETRIG_TIMD_CMP2
LL_HRTIM_CAPTURETRIG_TIME_CMP1
LL_HRTIM_CAPTURETRIG_TIME_CMP2
LL_HRTIM_CAPTURETRIG_TIMF_CMP1
LL_HRTIM_CAPTURETRIG_TIMF_CMP2
LL_HRTIM_CAPTURETRIG_UPDATE
DELAYED PROTECTION (DLYPRT) MODE
LL_HRTIM_DLYPRT_BALANCED_EEV7
LL_HRTIM_DLYPRT_BALANCED_EEV8
LL_HRTIM_DLYPRT_BALANCED_EEV9
LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
BURST MODE
LL_HRTIM_BURSTMODE_RESETCOUNTER
BURST DMA
LL_HRTIM_BURSTDMA_EEFR3
LL_HRTIM_BURSTDMA_MCMP1
LL_HRTIM_BURSTDMA_MCMP2
LL_HRTIM_BURSTDMA_MCMP3
LL_HRTIM_BURSTDMA_MCMP4
LL_HRTIM_BURSTDMA_MCNT
LL_HRTIM_BURSTDMA_MCR
LL_HRTIM_BURSTDMA_MDIER
LL_HRTIM_BURSTDMA_MICR
LL_HRTIM_BURSTDMA_MPER
LL_HRTIM_BURSTDMA_MREP
LL_HRTIM_BURSTDMA_NONE
LL_HRTIM_BURSTDMA_TIMCHPR
LL_HRTIM_BURSTDMA_TIMCMP1
LL_HRTIM_BURSTDMA_TIMCMP2
LL_HRTIM_BURSTDMA_TIMCMP3
LL_HRTIM_BURSTDMA_TIMCMP4
LL_HRTIM_BURSTDMA_TIMCNT
LL_HRTIM_BURSTDMA_TIMDIER
LL_HRTIM_BURSTDMA_TIMDTR
LL_HRTIM_BURSTDMA_TIMEEFR1
LL_HRTIM_BURSTDMA_TIMEEFR2
LL_HRTIM_BURSTDMA_TIMFLTR
LL_HRTIM_BURSTDMA_TIMICR
LL_HRTIM_BURSTDMA_TIMMCR
LL_HRTIM_BURSTDMA_TIMOUTR
LL_HRTIM_BURSTDMA_TIMPER
LL_HRTIM_BURSTDMA_TIMREP
LL_HRTIM_BURSTDMA_TIMRST1R
LL_HRTIM_BURSTDMA_TIMRST2R
LL_HRTIM_BURSTDMA_TIMRSTR
LL_HRTIM_BURSTDMA_TIMSET1R
LL_HRTIM_BURSTDMA_TIMSET2R
CURRENT PUSH-PULL STATUS
LL_HRTIM_CPPSTAT_OUTPUT2
IDLE PUSH-PULL STATUS
LL_HRTIM_IPPSTAT_OUTPUT2
TIMER EXTERNAL EVENT FILTER
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
LL_HRTIM_EEFLTR_BLANKINGCMP1
LL_HRTIM_EEFLTR_BLANKINGCMP2
LL_HRTIM_EEFLTR_BLANKINGCMP3
LL_HRTIM_EEFLTR_BLANKINGCMP4
LL_HRTIM_EEFLTR_NONE
LL_HRTIM_EEFLTR_WINDOWINGCMP2
LL_HRTIM_EEFLTR_WINDOWINGCMP3
LL_HRTIM_EEFLTR_WINDOWINGTIM
TIMER EXTERNAL EVENT LATCH STATUS
LL_HRTIM_EELATCH_ENABLED
DEADTIME PRESCALER
LL_HRTIM_DT_PRESCALER_DIV2
LL_HRTIM_DT_PRESCALER_DIV4
LL_HRTIM_DT_PRESCALER_DIV8
LL_HRTIM_DT_PRESCALER_MUL16
LL_HRTIM_DT_PRESCALER_MUL2
LL_HRTIM_DT_PRESCALER_MUL4
LL_HRTIM_DT_PRESCALER_MUL8
DEADTIME RISING SIGN
LL_HRTIM_DT_RISING_POSITIVE
DEADTIME FALLING SIGN
LL_HRTIM_DT_FALLING_POSITIVE
CHOPPER MODE PRESCALER
LL_HRTIM_CHP_PRESCALER_DIV128
LL_HRTIM_CHP_PRESCALER_DIV144
LL_HRTIM_CHP_PRESCALER_DIV16
LL_HRTIM_CHP_PRESCALER_DIV160
LL_HRTIM_CHP_PRESCALER_DIV176
LL_HRTIM_CHP_PRESCALER_DIV192
LL_HRTIM_CHP_PRESCALER_DIV208
LL_HRTIM_CHP_PRESCALER_DIV224
LL_HRTIM_CHP_PRESCALER_DIV240
LL_HRTIM_CHP_PRESCALER_DIV256
LL_HRTIM_CHP_PRESCALER_DIV32
LL_HRTIM_CHP_PRESCALER_DIV48
LL_HRTIM_CHP_PRESCALER_DIV64
LL_HRTIM_CHP_PRESCALER_DIV80
LL_HRTIM_CHP_PRESCALER_DIV96
CHOPPER MODE DUTY CYCLE
LL_HRTIM_CHP_DUTYCYCLE_125
LL_HRTIM_CHP_DUTYCYCLE_250
LL_HRTIM_CHP_DUTYCYCLE_375
LL_HRTIM_CHP_DUTYCYCLE_500
LL_HRTIM_CHP_DUTYCYCLE_625
LL_HRTIM_CHP_DUTYCYCLE_750
LL_HRTIM_CHP_DUTYCYCLE_875
CHOPPER MODE PULSE WIDTH
LL_HRTIM_CHP_PULSEWIDTH_128
LL_HRTIM_CHP_PULSEWIDTH_144
LL_HRTIM_CHP_PULSEWIDTH_16
LL_HRTIM_CHP_PULSEWIDTH_160
LL_HRTIM_CHP_PULSEWIDTH_176
LL_HRTIM_CHP_PULSEWIDTH_192
LL_HRTIM_CHP_PULSEWIDTH_208
LL_HRTIM_CHP_PULSEWIDTH_224
LL_HRTIM_CHP_PULSEWIDTH_240
LL_HRTIM_CHP_PULSEWIDTH_256
LL_HRTIM_CHP_PULSEWIDTH_32
LL_HRTIM_CHP_PULSEWIDTH_48
LL_HRTIM_CHP_PULSEWIDTH_64
LL_HRTIM_CHP_PULSEWIDTH_80
LL_HRTIM_CHP_PULSEWIDTH_96
OUTPUTSET INPUT
LL_HRTIM_OUTPUTSET_EEV_10
LL_HRTIM_OUTPUTSET_EEV_2
LL_HRTIM_OUTPUTSET_EEV_3
LL_HRTIM_OUTPUTSET_EEV_4
LL_HRTIM_OUTPUTSET_EEV_5
LL_HRTIM_OUTPUTSET_EEV_6
LL_HRTIM_OUTPUTSET_EEV_7
LL_HRTIM_OUTPUTSET_EEV_8
LL_HRTIM_OUTPUTSET_EEV_9
LL_HRTIM_OUTPUTSET_MASTERCMP1
LL_HRTIM_OUTPUTSET_MASTERCMP2
LL_HRTIM_OUTPUTSET_MASTERCMP3
LL_HRTIM_OUTPUTSET_MASTERCMP4
LL_HRTIM_OUTPUTSET_MASTERPER
LL_HRTIM_OUTPUTSET_NONE
LL_HRTIM_OUTPUTSET_RESYNC
LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
LL_HRTIM_OUTPUTSET_TIMCMP1
LL_HRTIM_OUTPUTSET_TIMCMP2
LL_HRTIM_OUTPUTSET_TIMCMP3
LL_HRTIM_OUTPUTSET_TIMCMP4
LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMPER
LL_HRTIM_OUTPUTSET_UPDATE
HRTIM Output Reset Source
HRTIM_OUTPUTRESET_EEV_10
HRTIM_OUTPUTRESET_EEV_2
HRTIM_OUTPUTRESET_EEV_3
HRTIM_OUTPUTRESET_EEV_4
HRTIM_OUTPUTRESET_EEV_5
HRTIM_OUTPUTRESET_EEV_6
HRTIM_OUTPUTRESET_EEV_7
HRTIM_OUTPUTRESET_EEV_8
HRTIM_OUTPUTRESET_EEV_9
HRTIM_OUTPUTRESET_MASTERCMP1
HRTIM_OUTPUTRESET_MASTERCMP2
HRTIM_OUTPUTRESET_MASTERCMP3
HRTIM_OUTPUTRESET_MASTERCMP4
HRTIM_OUTPUTRESET_MASTERPER
HRTIM_OUTPUTRESET_NONE
HRTIM_OUTPUTRESET_RESYNC
HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
HRTIM_OUTPUTRESET_TIMCMP1
HRTIM_OUTPUTRESET_TIMCMP2
HRTIM_OUTPUTRESET_TIMCMP3
HRTIM_OUTPUTRESET_TIMCMP4
HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
HRTIM_OUTPUTRESET_TIMPER
HRTIM_OUTPUTRESET_UPDATE
LL_HRTIM_OUTPUTRESET_EEV_1
LL_HRTIM_OUTPUTRESET_EEV_10
LL_HRTIM_OUTPUTRESET_EEV_2
LL_HRTIM_OUTPUTRESET_EEV_3
LL_HRTIM_OUTPUTRESET_EEV_4
LL_HRTIM_OUTPUTRESET_EEV_5
LL_HRTIM_OUTPUTRESET_EEV_6
LL_HRTIM_OUTPUTRESET_EEV_7
LL_HRTIM_OUTPUTRESET_EEV_8
LL_HRTIM_OUTPUTRESET_EEV_9
LL_HRTIM_OUTPUTRESET_MASTERCMP1
LL_HRTIM_OUTPUTRESET_MASTERCMP2
LL_HRTIM_OUTPUTRESET_MASTERCMP3
LL_HRTIM_OUTPUTRESET_MASTERCMP4
LL_HRTIM_OUTPUTRESET_MASTERPER
LL_HRTIM_OUTPUTRESET_NONE
LL_HRTIM_OUTPUTRESET_RESYNC
LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP1
LL_HRTIM_OUTPUTRESET_TIMCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP3
LL_HRTIM_OUTPUTRESET_TIMCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMPER
LL_HRTIM_OUTPUTRESET_UPDATE
OUPUT_POLARITY
LL_HRTIM_OUT_POSITIVE_POLARITY
OUTPUT IDLE MODE
LL_HRTIM_OUT_NO_IDLE
INTLVD MODE
LL_HRTIM_INTERLEAVED_MODE_DUAL
LL_HRTIM_INTERLEAVED_MODE_QUAD
LL_HRTIM_INTERLEAVED_MODE_TRIPLE
HALF MODE
LL_HRTIM_HALF_MODE_ENABLE
OUTPUT IDLE LEVEL
LL_HRTIM_OUT_IDLELEVEL_INACTIVE
OUTPUT FAULT STATE
LL_HRTIM_OUT_FAULTSTATE_HIGHZ
LL_HRTIM_OUT_FAULTSTATE_INACTIVE
LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
OUTPUT CHOPPER MODE
LL_HRTIM_OUT_CHOPPERMODE_ENABLED
OUTPUT BURST MODE ENTRY MODE
LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
OUTPUT LEVEL
LL_HRTIM_OUT_LEVEL_INACTIVE
EXTERNAL EVENT SOURCE
LL_HRTIM_EEV10SRC_COMP7_OUT
LL_HRTIM_EEV10SRC_GPIO
LL_HRTIM_EEV10SRC_TIM6_TRGO
LL_HRTIM_EEV1SRC_ADC1_AWD1
LL_HRTIM_EEV1SRC_COMP2_OUT
LL_HRTIM_EEV1SRC_GPIO
LL_HRTIM_EEV1SRC_TIM1_TRGO
LL_HRTIM_EEV2SRC_ADC1_AWD2
LL_HRTIM_EEV2SRC_COMP4_OUT
LL_HRTIM_EEV2SRC_GPIO
LL_HRTIM_EEV2SRC_TIM2_TRGO
LL_HRTIM_EEV3SRC_ADC1_AWD3
LL_HRTIM_EEV3SRC_COMP6_OUT
LL_HRTIM_EEV3SRC_GPIO
LL_HRTIM_EEV3SRC_TIM3_TRGO
LL_HRTIM_EEV4SRC_ADC2_AWD1
LL_HRTIM_EEV4SRC_COMP1_OUT
LL_HRTIM_EEV4SRC_COMP5_OUT
LL_HRTIM_EEV4SRC_GPIO
LL_HRTIM_EEV5SRC_ADC2_AWD2
LL_HRTIM_EEV5SRC_COMP3_OUT
LL_HRTIM_EEV5SRC_COMP7_OUT
LL_HRTIM_EEV5SRC_GPIO
LL_HRTIM_EEV6SRC_ADC2_AWD3
LL_HRTIM_EEV6SRC_COMP1_OUT
LL_HRTIM_EEV6SRC_COMP2_OUT
LL_HRTIM_EEV6SRC_GPIO
LL_HRTIM_EEV7SRC_ADC3_AWD1
LL_HRTIM_EEV7SRC_COMP4_OUT
LL_HRTIM_EEV7SRC_GPIO
LL_HRTIM_EEV7SRC_TIM7_TRGO
LL_HRTIM_EEV8SRC_ADC4_AWD1
LL_HRTIM_EEV8SRC_COMP3_OUT
LL_HRTIM_EEV8SRC_COMP6_OUT
LL_HRTIM_EEV8SRC_GPIO
LL_HRTIM_EEV9SRC_COMP4_OUT
LL_HRTIM_EEV9SRC_COMP5_OUT
LL_HRTIM_EEV9SRC_GPIO
LL_HRTIM_EEV9SRC_TIM15_TRGO
EXTERNAL EVENT POLARITY
LL_HRTIM_EE_POLARITY_LOW
EXTERNAL EVENT SENSITIVITY
LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
LL_HRTIM_EE_SENSITIVITY_LEVEL
LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
EXTERNAL EVENT FAST MODE
LL_HRTIM_EE_FASTMODE_ENABLE
EXTERNAL EVENT DIGITAL FILTER
LL_HRTIM_EE_FILTER_10
LL_HRTIM_EE_FILTER_11
LL_HRTIM_EE_FILTER_12
LL_HRTIM_EE_FILTER_13
LL_HRTIM_EE_FILTER_14
LL_HRTIM_EE_FILTER_15
LL_HRTIM_EE_FILTER_2
LL_HRTIM_EE_FILTER_3
LL_HRTIM_EE_FILTER_4
LL_HRTIM_EE_FILTER_5
LL_HRTIM_EE_FILTER_6
LL_HRTIM_EE_FILTER_7
LL_HRTIM_EE_FILTER_8
LL_HRTIM_EE_FILTER_9
LL_HRTIM_EE_FILTER_NONE
EXTERNAL EVENT PRESCALER
LL_HRTIM_EE_PRESCALER_DIV2
LL_HRTIM_EE_PRESCALER_DIV4
LL_HRTIM_EE_PRESCALER_DIV8
EXTERNAL EVENT A or B COUNTER
LL_HRTIM_EE_COUNTER_B
EXTERNAL EVENT A or B RESET MODE
LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
FAULT SOURCE
LL_HRTIM_FLT_SRC_EEVINPUT
LL_HRTIM_FLT_SRC_INTERNAL
FAULT POLARITY
LL_HRTIM_FLT_POLARITY_LOW
FAULT DIGITAL FILTER
LL_HRTIM_FLT_FILTER_10
LL_HRTIM_FLT_FILTER_11
LL_HRTIM_FLT_FILTER_12
LL_HRTIM_FLT_FILTER_13
LL_HRTIM_FLT_FILTER_14
LL_HRTIM_FLT_FILTER_15
LL_HRTIM_FLT_FILTER_2
LL_HRTIM_FLT_FILTER_3
LL_HRTIM_FLT_FILTER_4
LL_HRTIM_FLT_FILTER_5
LL_HRTIM_FLT_FILTER_6
LL_HRTIM_FLT_FILTER_7
LL_HRTIM_FLT_FILTER_8
LL_HRTIM_FLT_FILTER_9
LL_HRTIM_FLT_FILTER_NONE
BURST FAULT PRESCALER
LL_HRTIM_FLT_PRESCALER_DIV2
LL_HRTIM_FLT_PRESCALER_DIV4
LL_HRTIM_FLT_PRESCALER_DIV8
FAULT BLANKING Source
LL_HRTIM_FLT_BLANKING_RSTALIGNED
FAULT Counter RESET Mode
LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
BURST MODE OPERATING MODE
LL_HRTIM_BM_MODE_SINGLESHOT
BURST MODE CLOCK SOURCE
LL_HRTIM_BM_CLKSRC_MASTER
LL_HRTIM_BM_CLKSRC_TIM16_OC
LL_HRTIM_BM_CLKSRC_TIM17_OC
LL_HRTIM_BM_CLKSRC_TIM7_TRGO
LL_HRTIM_BM_CLKSRC_TIMER_A
LL_HRTIM_BM_CLKSRC_TIMER_B
LL_HRTIM_BM_CLKSRC_TIMER_C
LL_HRTIM_BM_CLKSRC_TIMER_D
LL_HRTIM_BM_CLKSRC_TIMER_E
LL_HRTIM_BM_CLKSRC_TIMER_F
BURST MODE PRESCALER
LL_HRTIM_BM_PRESCALER_DIV1024
LL_HRTIM_BM_PRESCALER_DIV128
LL_HRTIM_BM_PRESCALER_DIV16
LL_HRTIM_BM_PRESCALER_DIV16384
LL_HRTIM_BM_PRESCALER_DIV2
LL_HRTIM_BM_PRESCALER_DIV2048
LL_HRTIM_BM_PRESCALER_DIV256
LL_HRTIM_BM_PRESCALER_DIV32
LL_HRTIM_BM_PRESCALER_DIV32768
LL_HRTIM_BM_PRESCALER_DIV4
LL_HRTIM_BM_PRESCALER_DIV4096
LL_HRTIM_BM_PRESCALER_DIV512
LL_HRTIM_BM_PRESCALER_DIV64
LL_HRTIM_BM_PRESCALER_DIV8
LL_HRTIM_BM_PRESCALER_DIV8192
HRTIM BURST MODE TRIGGER
LL_HRTIM_BM_TRIG_EVENT_8
LL_HRTIM_BM_TRIG_EVENT_ONCHIP
LL_HRTIM_BM_TRIG_MASTER_CMP1
LL_HRTIM_BM_TRIG_MASTER_CMP2
LL_HRTIM_BM_TRIG_MASTER_CMP3
LL_HRTIM_BM_TRIG_MASTER_CMP4
LL_HRTIM_BM_TRIG_MASTER_REPETITION
LL_HRTIM_BM_TRIG_MASTER_RESET
LL_HRTIM_BM_TRIG_NONE
LL_HRTIM_BM_TRIG_TIMA_CMP1
LL_HRTIM_BM_TRIG_TIMA_CMP2
LL_HRTIM_BM_TRIG_TIMA_EVENT7
LL_HRTIM_BM_TRIG_TIMA_REPETITION
LL_HRTIM_BM_TRIG_TIMA_RESET
LL_HRTIM_BM_TRIG_TIMB_CMP1
LL_HRTIM_BM_TRIG_TIMB_CMP2
LL_HRTIM_BM_TRIG_TIMB_REPETITION
LL_HRTIM_BM_TRIG_TIMB_RESET
LL_HRTIM_BM_TRIG_TIMC_CMP1
LL_HRTIM_BM_TRIG_TIMC_REPETITION
LL_HRTIM_BM_TRIG_TIMC_RESET
LL_HRTIM_BM_TRIG_TIMD_CMP2
LL_HRTIM_BM_TRIG_TIMD_EVENT8
LL_HRTIM_BM_TRIG_TIMD_REPETITION
LL_HRTIM_BM_TRIG_TIMD_RESET
LL_HRTIM_BM_TRIG_TIME_CMP1
LL_HRTIM_BM_TRIG_TIME_CMP2
LL_HRTIM_BM_TRIG_TIME_REPETITION
LL_HRTIM_BM_TRIG_TIMF_CMP1
LL_HRTIM_BM_TRIG_TIMF_REPETITION
LL_HRTIM_BM_TRIG_TIMF_RESET
HRTIM BURST MODE STATUS
LL_HRTIM_BM_STATUS_NORMAL
Counter Mode
LL_HRTIM_COUNTING_MODE_UP_DOWN
counter Mode
LL_HRTIM_ROLLOVER_MODE_PER
LL_HRTIM_ROLLOVER_MODE_RST
HRTIM Timer Triggered-Half Mode
HRTIM_TIMERTRIGHALF_ENABLED
LL_HRTIM_TRIGHALF_DISABLED
LL_HRTIM_TRIGHALF_ENABLED
Greater than compare PWM Mode
LL_HRTIM_GTCMP1_GREATER
LL_HRTIM_GTCMP3_EQUAL
LL_HRTIM_GTCMP3_GREATER
Enabling the Dual Channel DAC Triggering
LL_HRTIM_DCDE_ENABLED
Dual Channel DAC Reset Trigger
LL_HRTIM_DCDR_OUT1SET
Dual Channel DAC Step trigger
LL_HRTIM_DCDS_OUT1RST
HRTIM Exported Macros
LL_HRTIM_WriteReg
Exported_Macros
HRTIM Exported Functions
LL_HRTIM_ConfigDLLCalibration
LL_HRTIM_ConfigSyncOut
LL_HRTIM_CounterReset
LL_HRTIM_DisableOutput
LL_HRTIM_DisableSwapOutputs
LL_HRTIM_EnableOutput
LL_HRTIM_EnableSwapOutputs
LL_HRTIM_ForceUpdate
LL_HRTIM_GetADCPostScaler
LL_HRTIM_GetADCTrigSrc
LL_HRTIM_GetADCTrigUpdate
LL_HRTIM_GetSyncInSrc
LL_HRTIM_GetSyncOutConfig
LL_HRTIM_GetSyncOutSrc
LL_HRTIM_IsDisabledOutput
LL_HRTIM_IsEnabledOutput
LL_HRTIM_IsEnabledSwapOutputs
LL_HRTIM_ResumeUpdate
LL_HRTIM_SetADCPostScaler
LL_HRTIM_SetADCTrigSrc
LL_HRTIM_SetADCTrigUpdate
LL_HRTIM_SetSyncInSrc
LL_HRTIM_SetSyncOutConfig
LL_HRTIM_SetSyncOutSrc
LL_HRTIM_StartDLLCalibration
LL_HRTIM_SuspendUpdate
HRTIM_Timer_Control
LL_HRTIM_TIM_CounterDisable
LL_HRTIM_TIM_CounterEnable
LL_HRTIM_TIM_DisableBIAR
LL_HRTIM_TIM_DisableDeadTime
LL_HRTIM_TIM_DisableDLYPRT
LL_HRTIM_TIM_DisableDualDacTrigger
LL_HRTIM_TIM_DisableEventCounter
LL_HRTIM_TIM_DisableFault
LL_HRTIM_TIM_DisableHalfMode
LL_HRTIM_TIM_DisablePreload
LL_HRTIM_TIM_DisablePushPullMode
LL_HRTIM_TIM_DisableResetOnSync
LL_HRTIM_TIM_DisableResyncUpdate
LL_HRTIM_TIM_DisableStartOnSync
LL_HRTIM_TIM_EnableBIAR
LL_HRTIM_TIM_EnableDeadTime
LL_HRTIM_TIM_EnableDLYPRT
LL_HRTIM_TIM_EnableDualDacTrigger
LL_HRTIM_TIM_EnableEventCounter
LL_HRTIM_TIM_EnableFault
LL_HRTIM_TIM_EnableHalfMode
LL_HRTIM_TIM_EnablePreload
LL_HRTIM_TIM_EnablePushPullMode
LL_HRTIM_TIM_EnableResetOnSync
LL_HRTIM_TIM_EnableResyncUpdate
LL_HRTIM_TIM_EnableStartOnSync
LL_HRTIM_TIM_GetADCRollOverMode
LL_HRTIM_TIM_GetBMRollOverMode
LL_HRTIM_TIM_GetBurstModeOption
LL_HRTIM_TIM_GetCapture1
LL_HRTIM_TIM_GetCapture1Direction
LL_HRTIM_TIM_GetCapture2
LL_HRTIM_TIM_GetCapture2Direction
LL_HRTIM_TIM_GetCaptureTrig
LL_HRTIM_TIM_GetComp1Mode
LL_HRTIM_TIM_GetComp3Mode
LL_HRTIM_TIM_GetCompare1
LL_HRTIM_TIM_GetCompare2
LL_HRTIM_TIM_GetCompare3
LL_HRTIM_TIM_GetCompare4
LL_HRTIM_TIM_GetCompareMode
LL_HRTIM_TIM_GetCounter
LL_HRTIM_TIM_GetCounterMode
LL_HRTIM_TIM_GetCountingMode
LL_HRTIM_TIM_GetCurrentPushPullStatus
LL_HRTIM_TIM_GetDACTrig
LL_HRTIM_TIM_GetDLYPRTMode
LL_HRTIM_TIM_GetDualDacResetTrigger
LL_HRTIM_TIM_GetDualDacStepTrigger
LL_HRTIM_TIM_GetEventCounterResetMode
LL_HRTIM_TIM_GetEventCounterSource
LL_HRTIM_TIM_GetEventCounterThreshold
LL_HRTIM_TIM_GetEventFilter
LL_HRTIM_TIM_GetEventLatchStatus
LL_HRTIM_TIM_GetFaultEventRollOverMode
LL_HRTIM_TIM_GetIdlePushPullStatus
LL_HRTIM_TIM_GetInterleavedMode
LL_HRTIM_TIM_GetOutputRollOverMode
LL_HRTIM_TIM_GetPeriod
LL_HRTIM_TIM_GetPrescaler
LL_HRTIM_TIM_GetRepetition
LL_HRTIM_TIM_GetResetTrig
LL_HRTIM_TIM_GetRollOverMode
LL_HRTIM_TIM_GetTriggeredHalfMode
LL_HRTIM_TIM_GetUpdateGating
LL_HRTIM_TIM_GetUpdateTrig
LL_HRTIM_TIM_IsCounterEnabled
LL_HRTIM_TIM_IsEnabledBIAR
LL_HRTIM_TIM_IsEnabledDeadTime
LL_HRTIM_TIM_IsEnabledDLYPRT
LL_HRTIM_TIM_IsEnabledDualDacTrigger
LL_HRTIM_TIM_IsEnabledEventCounter
LL_HRTIM_TIM_IsEnabledFault
LL_HRTIM_TIM_IsEnabledHalfMode
LL_HRTIM_TIM_IsEnabledPreload
LL_HRTIM_TIM_IsEnabledPushPullMode
LL_HRTIM_TIM_IsEnabledResetOnSync
LL_HRTIM_TIM_IsEnabledResyncUpdate
LL_HRTIM_TIM_IsEnabledStartOnSync
LL_HRTIM_TIM_LockFault
LL_HRTIM_TIM_ResetEventCounter
LL_HRTIM_TIM_SetADCRollOverMode
LL_HRTIM_TIM_SetBMRollOverMode
LL_HRTIM_TIM_SetBurstModeOption
LL_HRTIM_TIM_SetCaptureTrig
LL_HRTIM_TIM_SetComp1Mode
LL_HRTIM_TIM_SetComp3Mode
LL_HRTIM_TIM_SetCompare1
LL_HRTIM_TIM_SetCompare2
LL_HRTIM_TIM_SetCompare3
LL_HRTIM_TIM_SetCompare4
LL_HRTIM_TIM_SetCompareMode
LL_HRTIM_TIM_SetCounter
LL_HRTIM_TIM_SetCounterMode
LL_HRTIM_TIM_SetCountingMode
LL_HRTIM_TIM_SetDACTrig
LL_HRTIM_TIM_SetDLYPRTMode
LL_HRTIM_TIM_SetDualDacResetTrigger
LL_HRTIM_TIM_SetDualDacStepTrigger
LL_HRTIM_TIM_SetEventCounterResetMode
LL_HRTIM_TIM_SetEventCounterSource
LL_HRTIM_TIM_SetEventCounterThreshold
LL_HRTIM_TIM_SetEventFilter
LL_HRTIM_TIM_SetEventLatchStatus
LL_HRTIM_TIM_SetFaultEventRollOverMode
LL_HRTIM_TIM_SetInterleavedMode
LL_HRTIM_TIM_SetOutputRollOverMode
LL_HRTIM_TIM_SetPeriod
LL_HRTIM_TIM_SetPrescaler
LL_HRTIM_TIM_SetRepetition
LL_HRTIM_TIM_SetResetTrig
LL_HRTIM_TIM_SetRollOverMode
LL_HRTIM_TIM_SetTriggeredHalfMode
LL_HRTIM_TIM_SetUpdateGating
LL_HRTIM_TIM_SetUpdateTrig
Dead_Time_Configuration
LL_HRTIM_DT_GetFallingSign
LL_HRTIM_DT_GetFallingValue
LL_HRTIM_DT_GetPrescaler
LL_HRTIM_DT_GetRisingSign
LL_HRTIM_DT_GetRisingValue
LL_HRTIM_DT_LockFalling
LL_HRTIM_DT_LockFallingSign
LL_HRTIM_DT_LockRising
LL_HRTIM_DT_LockRisingSign
LL_HRTIM_DT_SetFallingSign
LL_HRTIM_DT_SetFallingValue
LL_HRTIM_DT_SetPrescaler
LL_HRTIM_DT_SetRisingSign
LL_HRTIM_DT_SetRisingValue
Chopper_Mode_Configuration
LL_HRTIM_CHP_GetDutyCycle
LL_HRTIM_CHP_GetPrescaler
LL_HRTIM_CHP_GetPulseWidth
LL_HRTIM_CHP_SetDutyCycle
LL_HRTIM_CHP_SetPrescaler
LL_HRTIM_CHP_SetPulseWidth
Output_Management
LL_HRTIM_OUT_ForceLevel
LL_HRTIM_OUT_GetBMEntryMode
LL_HRTIM_OUT_GetChopperMode
LL_HRTIM_OUT_GetDLYPRTOutStatus
LL_HRTIM_OUT_GetFaultState
LL_HRTIM_OUT_GetIdleLevel
LL_HRTIM_OUT_GetIdleMode
LL_HRTIM_OUT_GetLevel
LL_HRTIM_OUT_GetOutputResetSrc
LL_HRTIM_OUT_GetOutputSetSrc
LL_HRTIM_OUT_GetPolarity
LL_HRTIM_OUT_SetBMEntryMode
LL_HRTIM_OUT_SetChopperMode
LL_HRTIM_OUT_SetFaultState
LL_HRTIM_OUT_SetIdleLevel
LL_HRTIM_OUT_SetIdleMode
LL_HRTIM_OUT_SetOutputResetSrc
LL_HRTIM_OUT_SetOutputSetSrc
LL_HRTIM_OUT_SetPolarity
External_Event_management
LL_HRTIM_EE_GetFastMode
LL_HRTIM_EE_GetFilter
LL_HRTIM_EE_GetPolarity
LL_HRTIM_EE_GetPrescaler
LL_HRTIM_EE_GetSensitivity
LL_HRTIM_EE_GetSrc
LL_HRTIM_EE_SetFastMode
LL_HRTIM_EE_SetFilter
LL_HRTIM_EE_SetPolarity
LL_HRTIM_EE_SetPrescaler
LL_HRTIM_EE_SetSensitivity
LL_HRTIM_EE_SetSrc
Fault_management
LL_HRTIM_FLT_Disable
LL_HRTIM_FLT_DisableBlanking
LL_HRTIM_FLT_Enable
LL_HRTIM_FLT_EnableBlanking
LL_HRTIM_FLT_GetBlankingSrc
LL_HRTIM_FLT_GetCounterThreshold
LL_HRTIM_FLT_GetFilter
LL_HRTIM_FLT_GetPolarity
LL_HRTIM_FLT_GetPrescaler
LL_HRTIM_FLT_GetResetMode
LL_HRTIM_FLT_GetSrc
LL_HRTIM_FLT_IsEnabled
LL_HRTIM_FLT_IsEnabledBlanking
LL_HRTIM_FLT_Lock
LL_HRTIM_FLT_ResetCounter
LL_HRTIM_FLT_SetBlankingSrc
LL_HRTIM_FLT_SetCounterThreshold
LL_HRTIM_FLT_SetFilter
LL_HRTIM_FLT_SetPolarity
LL_HRTIM_FLT_SetPrescaler
LL_HRTIM_FLT_SetResetMode
LL_HRTIM_FLT_SetSrc
Burst_Mode_management
LL_HRTIM_BM_Disable
LL_HRTIM_BM_DisablePreload
LL_HRTIM_BM_Enable
LL_HRTIM_BM_EnablePreload
LL_HRTIM_BM_GetClockSrc
LL_HRTIM_BM_GetCompare
LL_HRTIM_BM_GetMode
LL_HRTIM_BM_GetPeriod
LL_HRTIM_BM_GetPrescaler
LL_HRTIM_BM_GetStatus
LL_HRTIM_BM_GetTrig
LL_HRTIM_BM_IsEnabled
LL_HRTIM_BM_IsEnabledPreload
LL_HRTIM_BM_SetClockSrc
LL_HRTIM_BM_SetCompare
LL_HRTIM_BM_SetMode
LL_HRTIM_BM_SetPeriod
LL_HRTIM_BM_SetPrescaler
LL_HRTIM_BM_SetTrig
LL_HRTIM_BM_Start
LL_HRTIM_BM_Stop
FLAG_Management
LL_HRTIM_ClearFlag_CMP1
LL_HRTIM_ClearFlag_CMP2
LL_HRTIM_ClearFlag_CMP3
LL_HRTIM_ClearFlag_CMP4
LL_HRTIM_ClearFlag_CPT1
LL_HRTIM_ClearFlag_CPT2
LL_HRTIM_ClearFlag_DLLRDY
LL_HRTIM_ClearFlag_DLYPRT
LL_HRTIM_ClearFlag_FLT1
LL_HRTIM_ClearFlag_FLT2
LL_HRTIM_ClearFlag_FLT3
LL_HRTIM_ClearFlag_FLT4
LL_HRTIM_ClearFlag_FLT5
LL_HRTIM_ClearFlag_FLT6
LL_HRTIM_ClearFlag_REP
LL_HRTIM_ClearFlag_RST
LL_HRTIM_ClearFlag_RST1
LL_HRTIM_ClearFlag_RST2
LL_HRTIM_ClearFlag_SET1
LL_HRTIM_ClearFlag_SET2
LL_HRTIM_ClearFlag_SYNC
LL_HRTIM_ClearFlag_SYSFLT
LL_HRTIM_ClearFlag_UPDATE
LL_HRTIM_IsActiveFlag_BMPER
LL_HRTIM_IsActiveFlag_CMP1
LL_HRTIM_IsActiveFlag_CMP2
LL_HRTIM_IsActiveFlag_CMP3
LL_HRTIM_IsActiveFlag_CMP4
LL_HRTIM_IsActiveFlag_CPT1
LL_HRTIM_IsActiveFlag_CPT2
LL_HRTIM_IsActiveFlag_DLLRDY
LL_HRTIM_IsActiveFlag_DLYPRT
LL_HRTIM_IsActiveFlag_FLT1
LL_HRTIM_IsActiveFlag_FLT2
LL_HRTIM_IsActiveFlag_FLT3
LL_HRTIM_IsActiveFlag_FLT4
LL_HRTIM_IsActiveFlag_FLT5
LL_HRTIM_IsActiveFlag_FLT6
LL_HRTIM_IsActiveFlag_REP
LL_HRTIM_IsActiveFlag_RST
LL_HRTIM_IsActiveFlag_RST1
LL_HRTIM_IsActiveFlag_RST2
LL_HRTIM_IsActiveFlag_SET1
LL_HRTIM_IsActiveFlag_SET2
LL_HRTIM_IsActiveFlag_SYNC
LL_HRTIM_IsActiveFlag_SYSFLT
LL_HRTIM_IsActiveFlag_UPDATE
IT_Management
LL_HRTIM_DisableIT_CMP1
LL_HRTIM_DisableIT_CMP2
LL_HRTIM_DisableIT_CMP3
LL_HRTIM_DisableIT_CMP4
LL_HRTIM_DisableIT_CPT1
LL_HRTIM_DisableIT_CPT2
LL_HRTIM_DisableIT_DLLRDY
LL_HRTIM_DisableIT_DLYPRT
LL_HRTIM_DisableIT_FLT1
LL_HRTIM_DisableIT_FLT2
LL_HRTIM_DisableIT_FLT3
LL_HRTIM_DisableIT_FLT4
LL_HRTIM_DisableIT_FLT5
LL_HRTIM_DisableIT_FLT6
LL_HRTIM_DisableIT_REP
LL_HRTIM_DisableIT_RST
LL_HRTIM_DisableIT_RST1
LL_HRTIM_DisableIT_RST2
LL_HRTIM_DisableIT_SET1
LL_HRTIM_DisableIT_SET2
LL_HRTIM_DisableIT_SYNC
LL_HRTIM_DisableIT_SYSFLT
LL_HRTIM_DisableIT_UPDATE
LL_HRTIM_EnableIT_BMPER
LL_HRTIM_EnableIT_CMP1
LL_HRTIM_EnableIT_CMP2
LL_HRTIM_EnableIT_CMP3
LL_HRTIM_EnableIT_CMP4
LL_HRTIM_EnableIT_CPT1
LL_HRTIM_EnableIT_CPT2
LL_HRTIM_EnableIT_DLLRDY
LL_HRTIM_EnableIT_DLYPRT
LL_HRTIM_EnableIT_FLT1
LL_HRTIM_EnableIT_FLT2
LL_HRTIM_EnableIT_FLT3
LL_HRTIM_EnableIT_FLT4
LL_HRTIM_EnableIT_FLT5
LL_HRTIM_EnableIT_FLT6
LL_HRTIM_EnableIT_REP
LL_HRTIM_EnableIT_RST
LL_HRTIM_EnableIT_RST1
LL_HRTIM_EnableIT_RST2
LL_HRTIM_EnableIT_SET1
LL_HRTIM_EnableIT_SET2
LL_HRTIM_EnableIT_SYNC
LL_HRTIM_EnableIT_SYSFLT
LL_HRTIM_EnableIT_UPDATE
LL_HRTIM_IsEnabledIT_BMPER
LL_HRTIM_IsEnabledIT_CMP1
LL_HRTIM_IsEnabledIT_CMP2
LL_HRTIM_IsEnabledIT_CMP3
LL_HRTIM_IsEnabledIT_CMP4
LL_HRTIM_IsEnabledIT_CPT1
LL_HRTIM_IsEnabledIT_CPT2
LL_HRTIM_IsEnabledIT_DLLRDY
LL_HRTIM_IsEnabledIT_DLYPRT
LL_HRTIM_IsEnabledIT_FLT1
LL_HRTIM_IsEnabledIT_FLT2
LL_HRTIM_IsEnabledIT_FLT3
LL_HRTIM_IsEnabledIT_FLT4
LL_HRTIM_IsEnabledIT_FLT5
LL_HRTIM_IsEnabledIT_FLT6
LL_HRTIM_IsEnabledIT_REP
LL_HRTIM_IsEnabledIT_RST
LL_HRTIM_IsEnabledIT_RST1
LL_HRTIM_IsEnabledIT_RST2
LL_HRTIM_IsEnabledIT_SET1
LL_HRTIM_IsEnabledIT_SET2
LL_HRTIM_IsEnabledIT_SYNC
LL_HRTIM_IsEnabledIT_SYSFLT
LL_HRTIM_IsEnabledIT_UPDATE
DMA_Management
LL_HRTIM_DisableDMAReq_CMP2
LL_HRTIM_DisableDMAReq_CMP3
LL_HRTIM_DisableDMAReq_CMP4
LL_HRTIM_DisableDMAReq_CPT1
LL_HRTIM_DisableDMAReq_CPT2
LL_HRTIM_DisableDMAReq_DLYPRT
LL_HRTIM_DisableDMAReq_REP
LL_HRTIM_DisableDMAReq_RST
LL_HRTIM_DisableDMAReq_RST1
LL_HRTIM_DisableDMAReq_RST2
LL_HRTIM_DisableDMAReq_SET1
LL_HRTIM_DisableDMAReq_SET2
LL_HRTIM_DisableDMAReq_SYNC
LL_HRTIM_DisableDMAReq_UPDATE
LL_HRTIM_EnableDMAReq_CMP1
LL_HRTIM_EnableDMAReq_CMP2
LL_HRTIM_EnableDMAReq_CMP3
LL_HRTIM_EnableDMAReq_CMP4
LL_HRTIM_EnableDMAReq_CPT1
LL_HRTIM_EnableDMAReq_CPT2
LL_HRTIM_EnableDMAReq_DLYPRT
LL_HRTIM_EnableDMAReq_REP
LL_HRTIM_EnableDMAReq_RST
LL_HRTIM_EnableDMAReq_RST1
LL_HRTIM_EnableDMAReq_RST2
LL_HRTIM_EnableDMAReq_SET1
LL_HRTIM_EnableDMAReq_SET2
LL_HRTIM_EnableDMAReq_SYNC
LL_HRTIM_EnableDMAReq_UPDATE
LL_HRTIM_IsEnabledDMAReq_CMP1
LL_HRTIM_IsEnabledDMAReq_CMP2
LL_HRTIM_IsEnabledDMAReq_CMP3
LL_HRTIM_IsEnabledDMAReq_CMP4
LL_HRTIM_IsEnabledDMAReq_CPT1
LL_HRTIM_IsEnabledDMAReq_CPT2
LL_HRTIM_IsEnabledDMAReq_DLYPRT
LL_HRTIM_IsEnabledDMAReq_REP
LL_HRTIM_IsEnabledDMAReq_RST
LL_HRTIM_IsEnabledDMAReq_RST1
LL_HRTIM_IsEnabledDMAReq_RST2
LL_HRTIM_IsEnabledDMAReq_SET1
LL_HRTIM_IsEnabledDMAReq_SET2
LL_HRTIM_IsEnabledDMAReq_SYNC
LL_HRTIM_IsEnabledDMAReq_UPDATE
In-initialization and de-initialization functions
Functions
I2C
I2C Private Macros
IS_LL_I2C_DIGITAL_FILTER
IS_LL_I2C_OWN_ADDRESS1
IS_LL_I2C_OWN_ADDRSIZE
IS_LL_I2C_PERIPHERAL_MODE
IS_LL_I2C_TYPE_ACKNOWLEDGE
I2C Exported Init structure
I2C Exported Constants
LL_I2C_ICR_ALERTCF
LL_I2C_ICR_ARLOCF
LL_I2C_ICR_BERRCF
LL_I2C_ICR_NACKCF
LL_I2C_ICR_OVRCF
LL_I2C_ICR_PECCF
LL_I2C_ICR_STOPCF
LL_I2C_ICR_TIMOUTCF
Get Flags Defines
LL_I2C_ISR_ALERT
LL_I2C_ISR_ARLO
LL_I2C_ISR_BERR
LL_I2C_ISR_BUSY
LL_I2C_ISR_NACKF
LL_I2C_ISR_OVR
LL_I2C_ISR_PECERR
LL_I2C_ISR_RXNE
LL_I2C_ISR_STOPF
LL_I2C_ISR_TC
LL_I2C_ISR_TCR
LL_I2C_ISR_TIMEOUT
LL_I2C_ISR_TXE
LL_I2C_ISR_TXIS
IT Defines
LL_I2C_CR1_ERRIE
LL_I2C_CR1_NACKIE
LL_I2C_CR1_RXIE
LL_I2C_CR1_STOPIE
LL_I2C_CR1_TCIE
LL_I2C_CR1_TXIE
Peripheral Mode
LL_I2C_MODE_SMBUS_DEVICE
LL_I2C_MODE_SMBUS_DEVICE_ARP
LL_I2C_MODE_SMBUS_HOST
Analog Filter Selection
LL_I2C_ANALOGFILTER_ENABLE
Master Addressing Mode
LL_I2C_ADDRESSING_MODE_7BIT
Own Address 1 Length
LL_I2C_OWNADDRESS1_7BIT
Own Address 2 Masks
LL_I2C_OWNADDRESS2_MASK02
LL_I2C_OWNADDRESS2_MASK03
LL_I2C_OWNADDRESS2_MASK04
LL_I2C_OWNADDRESS2_MASK05
LL_I2C_OWNADDRESS2_MASK06
LL_I2C_OWNADDRESS2_MASK07
LL_I2C_OWNADDRESS2_NOMASK
Acknowledge Generation
LL_I2C_NACK
Slave Address Length
LL_I2C_ADDRSLAVE_7BIT
Transfer Request Direction
LL_I2C_REQUEST_WRITE
Transfer End Mode
LL_I2C_MODE_RELOAD
LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
LL_I2C_MODE_SMBUS_RELOAD
LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
LL_I2C_MODE_SOFTEND
Start And Stop Generation
LL_I2C_GENERATE_RESTART_10BIT_READ
LL_I2C_GENERATE_RESTART_10BIT_WRITE
LL_I2C_GENERATE_RESTART_7BIT_READ
LL_I2C_GENERATE_RESTART_7BIT_WRITE
LL_I2C_GENERATE_START_READ
LL_I2C_GENERATE_START_WRITE
LL_I2C_GENERATE_STOP
Read Write Direction
LL_I2C_DIRECTION_WRITE
DMA Register Data
LL_I2C_DMA_REG_DATA_TRANSMIT
SMBus TimeoutA Mode SCL SDA Timeout
LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
SMBus Timeout Selection
LL_I2C_SMBUS_TIMEOUTA
LL_I2C_SMBUS_TIMEOUTB
I2C Exported Macros
LL_I2C_WriteReg
Convert SDA SCL timings
I2C Exported Functions
LL_I2C_ConfigSMBusTimeout
LL_I2C_Disable
LL_I2C_DisableAnalogFilter
LL_I2C_DisableClockStretching
LL_I2C_DisableDMAReq_RX
LL_I2C_DisableDMAReq_TX
LL_I2C_DisableGeneralCall
LL_I2C_DisableOwnAddress1
LL_I2C_DisableOwnAddress2
LL_I2C_DisableSlaveByteControl
LL_I2C_DisableSMBusAlert
LL_I2C_DisableSMBusPEC
LL_I2C_DisableSMBusTimeout
LL_I2C_DisableWakeUpFromStop
LL_I2C_DMA_GetRegAddr
LL_I2C_Enable
LL_I2C_EnableAnalogFilter
LL_I2C_EnableClockStretching
LL_I2C_EnableDMAReq_RX
LL_I2C_EnableDMAReq_TX
LL_I2C_EnableGeneralCall
LL_I2C_EnableOwnAddress1
LL_I2C_EnableOwnAddress2
LL_I2C_EnableSlaveByteControl
LL_I2C_EnableSMBusAlert
LL_I2C_EnableSMBusPEC
LL_I2C_EnableSMBusTimeout
LL_I2C_EnableWakeUpFromStop
LL_I2C_GetClockHighPeriod
LL_I2C_GetClockLowPeriod
LL_I2C_GetDataHoldTime
LL_I2C_GetDataSetupTime
LL_I2C_GetDigitalFilter
LL_I2C_GetMasterAddressingMode
LL_I2C_GetMode
LL_I2C_GetSMBusTimeoutA
LL_I2C_GetSMBusTimeoutAMode
LL_I2C_GetSMBusTimeoutB
LL_I2C_GetTimingPrescaler
LL_I2C_IsEnabled
LL_I2C_IsEnabledAnalogFilter
LL_I2C_IsEnabledClockStretching
LL_I2C_IsEnabledDMAReq_RX
LL_I2C_IsEnabledDMAReq_TX
LL_I2C_IsEnabledGeneralCall
LL_I2C_IsEnabledOwnAddress1
LL_I2C_IsEnabledOwnAddress2
LL_I2C_IsEnabledSlaveByteControl
LL_I2C_IsEnabledSMBusAlert
LL_I2C_IsEnabledSMBusPEC
LL_I2C_IsEnabledSMBusTimeout
LL_I2C_IsEnabledWakeUpFromStop
LL_I2C_SetDigitalFilter
LL_I2C_SetMasterAddressingMode
LL_I2C_SetMode
LL_I2C_SetOwnAddress1
LL_I2C_SetOwnAddress2
LL_I2C_SetSMBusTimeoutA
LL_I2C_SetSMBusTimeoutAMode
LL_I2C_SetSMBusTimeoutB
LL_I2C_SetTiming
IT_Management
LL_I2C_DisableIT_ERR
LL_I2C_DisableIT_NACK
LL_I2C_DisableIT_RX
LL_I2C_DisableIT_STOP
LL_I2C_DisableIT_TC
LL_I2C_DisableIT_TX
LL_I2C_EnableIT_ADDR
LL_I2C_EnableIT_ERR
LL_I2C_EnableIT_NACK
LL_I2C_EnableIT_RX
LL_I2C_EnableIT_STOP
LL_I2C_EnableIT_TC
LL_I2C_EnableIT_TX
LL_I2C_IsEnabledIT_ADDR
LL_I2C_IsEnabledIT_ERR
LL_I2C_IsEnabledIT_NACK
LL_I2C_IsEnabledIT_RX
LL_I2C_IsEnabledIT_STOP
LL_I2C_IsEnabledIT_TC
LL_I2C_IsEnabledIT_TX
FLAG_management
LL_I2C_ClearFlag_ARLO
LL_I2C_ClearFlag_BERR
LL_I2C_ClearFlag_NACK
LL_I2C_ClearFlag_OVR
LL_I2C_ClearFlag_STOP
LL_I2C_ClearFlag_TXE
LL_I2C_ClearSMBusFlag_ALERT
LL_I2C_ClearSMBusFlag_PECERR
LL_I2C_ClearSMBusFlag_TIMEOUT
LL_I2C_IsActiveFlag_ADDR
LL_I2C_IsActiveFlag_ARLO
LL_I2C_IsActiveFlag_BERR
LL_I2C_IsActiveFlag_BUSY
LL_I2C_IsActiveFlag_NACK
LL_I2C_IsActiveFlag_OVR
LL_I2C_IsActiveFlag_RXNE
LL_I2C_IsActiveFlag_STOP
LL_I2C_IsActiveFlag_TC
LL_I2C_IsActiveFlag_TCR
LL_I2C_IsActiveFlag_TXE
LL_I2C_IsActiveFlag_TXIS
LL_I2C_IsActiveSMBusFlag_ALERT
LL_I2C_IsActiveSMBusFlag_PECERR
LL_I2C_IsActiveSMBusFlag_TIMEOUT
Data_Management
LL_I2C_DisableAuto10BitRead
LL_I2C_DisableAutoEndMode
LL_I2C_DisableReloadMode
LL_I2C_EnableAuto10BitRead
LL_I2C_EnableAutoEndMode
LL_I2C_EnableReloadMode
LL_I2C_EnableSMBusPECCompare
LL_I2C_GenerateStartCondition
LL_I2C_GenerateStopCondition
LL_I2C_GetAddressMatchCode
LL_I2C_GetSlaveAddr
LL_I2C_GetSMBusPEC
LL_I2C_GetTransferDirection
LL_I2C_GetTransferRequest
LL_I2C_GetTransferSize
LL_I2C_HandleTransfer
LL_I2C_IsEnabledAuto10BitRead
LL_I2C_IsEnabledAutoEndMode
LL_I2C_IsEnabledReloadMode
LL_I2C_IsEnabledSMBusPECCompare
LL_I2C_ReceiveData8
LL_I2C_SetSlaveAddr
LL_I2C_SetTransferRequest
LL_I2C_SetTransferSize
LL_I2C_TransmitData8
Initialization and de-initialization functions
LL_I2C_Init
LL_I2C_StructInit
IWDG
LL_IWDG_KEY_RELOAD
LL_IWDG_KEY_WR_ACCESS_DISABLE
LL_IWDG_KEY_WR_ACCESS_ENABLE
IWDG Exported Constants
LL_IWDG_SR_RVU
LL_IWDG_SR_WVU
Prescaler Divider
LL_IWDG_PRESCALER_16
LL_IWDG_PRESCALER_256
LL_IWDG_PRESCALER_32
LL_IWDG_PRESCALER_4
LL_IWDG_PRESCALER_64
LL_IWDG_PRESCALER_8
IWDG Exported Macros
LL_IWDG_WriteReg
IWDG Exported Functions
LL_IWDG_Enable
LL_IWDG_EnableWriteAccess
LL_IWDG_GetPrescaler
LL_IWDG_GetReloadCounter
LL_IWDG_GetWindow
LL_IWDG_ReloadCounter
LL_IWDG_SetPrescaler
LL_IWDG_SetReloadCounter
LL_IWDG_SetWindow
FLAG_Management
LL_IWDG_IsActiveFlag_RVU
LL_IWDG_IsActiveFlag_WVU
LL_IWDG_IsReady
LPTIM
LPTIM_ResetCallback
LPTIM_WaitForFlag
LPTIM Private Macros
IS_LL_LPTIM_CLOCK_SOURCE
IS_LL_LPTIM_OUTPUT_POLARITY
IS_LL_LPTIM_WAVEFORM
LPTIM Exported Init structure
LPTIM Exported Constants
LL_LPTIM_ISR_ARROK
LL_LPTIM_ISR_CMPM
LL_LPTIM_ISR_CMPOK
LL_LPTIM_ISR_DOWN
LL_LPTIM_ISR_EXTTRIG
LL_LPTIM_ISR_UP
IT Defines
LL_LPTIM_IER_ARROKIE
LL_LPTIM_IER_CMPMIE
LL_LPTIM_IER_CMPOKIE
LL_LPTIM_IER_DOWNIE
LL_LPTIM_IER_EXTTRIGIE
LL_LPTIM_IER_UPIE
Operating Mode
LL_LPTIM_OPERATING_MODE_ONESHOT
Update Mode
LL_LPTIM_UPDATE_MODE_IMMEDIATE
Counter Mode
LL_LPTIM_COUNTER_MODE_INTERNAL
Output Waveform Type
LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
Output Polarity
LL_LPTIM_OUTPUT_POLARITY_REGULAR
Prescaler Value
LL_LPTIM_PRESCALER_DIV128
LL_LPTIM_PRESCALER_DIV16
LL_LPTIM_PRESCALER_DIV2
LL_LPTIM_PRESCALER_DIV32
LL_LPTIM_PRESCALER_DIV4
LL_LPTIM_PRESCALER_DIV64
LL_LPTIM_PRESCALER_DIV8
Trigger Source
LL_LPTIM_TRIG_SOURCE_COMP2
LL_LPTIM_TRIG_SOURCE_COMP3
LL_LPTIM_TRIG_SOURCE_COMP4
LL_LPTIM_TRIG_SOURCE_COMP5
LL_LPTIM_TRIG_SOURCE_COMP6
LL_LPTIM_TRIG_SOURCE_COMP7
LL_LPTIM_TRIG_SOURCE_GPIO
LL_LPTIM_TRIG_SOURCE_RTCALARMA
LL_LPTIM_TRIG_SOURCE_RTCALARMB
LL_LPTIM_TRIG_SOURCE_RTCTAMP1
LL_LPTIM_TRIG_SOURCE_RTCTAMP2
LL_LPTIM_TRIG_SOURCE_RTCTAMP3
Trigger Filter
LL_LPTIM_TRIG_FILTER_4
LL_LPTIM_TRIG_FILTER_8
LL_LPTIM_TRIG_FILTER_NONE
Trigger Polarity
LL_LPTIM_TRIG_POLARITY_RISING
LL_LPTIM_TRIG_POLARITY_RISING_FALLING
Clock Source
LL_LPTIM_CLK_SOURCE_INTERNAL
Clock Filter
LL_LPTIM_CLK_FILTER_4
LL_LPTIM_CLK_FILTER_8
LL_LPTIM_CLK_FILTER_NONE
Clock Polarity
LL_LPTIM_CLK_POLARITY_RISING
LL_LPTIM_CLK_POLARITY_RISING_FALLING
Encoder Mode
LL_LPTIM_ENCODER_MODE_RISING
LL_LPTIM_ENCODER_MODE_RISING_FALLING
Input1 Source
LL_LPTIM_INPUT1_SRC_COMP3
LL_LPTIM_INPUT1_SRC_COMP5
LL_LPTIM_INPUT1_SRC_COMP7
LL_LPTIM_INPUT1_SRC_GPIO
Input2 Source
LL_LPTIM_INPUT2_SRC_COMP4
LL_LPTIM_INPUT2_SRC_COMP6
LL_LPTIM_INPUT2_SRC_GPIO
LPTIM Exported Macros
LL_LPTIM_WriteReg
LPTIM Exported Functions
LL_LPTIM_Disable
LL_LPTIM_Init
LL_LPTIM_StructInit
LPTIM Configuration
LL_LPTIM_DisableResetAfterRead
LL_LPTIM_Enable
LL_LPTIM_EnableResetAfterRead
LL_LPTIM_GetAutoReload
LL_LPTIM_GetCompare
LL_LPTIM_GetCounter
LL_LPTIM_GetCounterMode
LL_LPTIM_GetPolarity
LL_LPTIM_GetPrescaler
LL_LPTIM_GetUpdateMode
LL_LPTIM_GetWaveform
LL_LPTIM_IsEnabled
LL_LPTIM_IsEnabledResetAfterRead
LL_LPTIM_ResetCounter
LL_LPTIM_SetAutoReload
LL_LPTIM_SetCompare
LL_LPTIM_SetCounterMode
LL_LPTIM_SetInput1Src
LL_LPTIM_SetInput2Src
LL_LPTIM_SetPolarity
LL_LPTIM_SetPrescaler
LL_LPTIM_SetUpdateMode
LL_LPTIM_SetWaveform
LL_LPTIM_StartCounter
Trigger Configuration
LL_LPTIM_DisableTimeout
LL_LPTIM_EnableTimeout
LL_LPTIM_GetTriggerFilter
LL_LPTIM_GetTriggerPolarity
LL_LPTIM_GetTriggerSource
LL_LPTIM_IsEnabledTimeout
LL_LPTIM_TrigSw
Clock Configuration
LL_LPTIM_GetClockFilter
LL_LPTIM_GetClockPolarity
LL_LPTIM_GetClockSource
LL_LPTIM_SetClockSource
Encoder Mode
LL_LPTIM_EnableEncoderMode
LL_LPTIM_GetEncoderMode
LL_LPTIM_IsEnabledEncoderMode
LL_LPTIM_SetEncoderMode
FLAG Management
LL_LPTIM_ClearFlag_ARROK
LL_LPTIM_ClearFlag_CMPM
LL_LPTIM_ClearFlag_CMPOK
LL_LPTIM_ClearFlag_DOWN
LL_LPTIM_ClearFlag_EXTTRIG
LL_LPTIM_ClearFlag_UP
LL_LPTIM_IsActiveFlag_ARRM
LL_LPTIM_IsActiveFlag_ARROK
LL_LPTIM_IsActiveFlag_CMPM
LL_LPTIM_IsActiveFlag_CMPOK
LL_LPTIM_IsActiveFlag_DOWN
LL_LPTIM_IsActiveFlag_EXTTRIG
LL_LPTIM_IsActiveFlag_UP
Interrupt Management
LL_LPTIM_DisableIT_ARROK
LL_LPTIM_DisableIT_CMPM
LL_LPTIM_DisableIT_CMPOK
LL_LPTIM_DisableIT_DOWN
LL_LPTIM_DisableIT_EXTTRIG
LL_LPTIM_DisableIT_UP
LL_LPTIM_EnableIT_ARRM
LL_LPTIM_EnableIT_ARROK
LL_LPTIM_EnableIT_CMPM
LL_LPTIM_EnableIT_CMPOK
LL_LPTIM_EnableIT_DOWN
LL_LPTIM_EnableIT_EXTTRIG
LL_LPTIM_EnableIT_UP
LL_LPTIM_IsEnabledIT_ARRM
LL_LPTIM_IsEnabledIT_ARROK
LL_LPTIM_IsEnabledIT_CMPM
LL_LPTIM_IsEnabledIT_CMPOK
LL_LPTIM_IsEnabledIT_DOWN
LL_LPTIM_IsEnabledIT_EXTTRIG
LL_LPTIM_IsEnabledIT_UP
LPUART
LPUART Private Constants
LPUART_BRR_MIN_VALUE
LPUART_DEFAULT_BAUDRATE
LPUART_LPUARTDIV_FREQ_MUL
LPUART Private Macros
IS_LL_LPUART_BRR_MAX
IS_LL_LPUART_BRR_MIN
IS_LL_LPUART_DATAWIDTH
IS_LL_LPUART_DIRECTION
IS_LL_LPUART_HWCONTROL
IS_LL_LPUART_PARITY
IS_LL_LPUART_PRESCALER
IS_LL_LPUART_STOPBITS
LPUART Exported Init structures
LPUART Exported Constants
LL_LPUART_ICR_CTSCF
LL_LPUART_ICR_FECF
LL_LPUART_ICR_IDLECF
LL_LPUART_ICR_NCF
LL_LPUART_ICR_ORECF
LL_LPUART_ICR_PECF
LL_LPUART_ICR_TCCF
LL_LPUART_ICR_WUCF
Get Flags Defines
LL_LPUART_ISR_CMF
LL_LPUART_ISR_CTS
LL_LPUART_ISR_CTSIF
LL_LPUART_ISR_FE
LL_LPUART_ISR_IDLE
LL_LPUART_ISR_NE
LL_LPUART_ISR_ORE
LL_LPUART_ISR_PE
LL_LPUART_ISR_REACK
LL_LPUART_ISR_RWU
LL_LPUART_ISR_RXFF
LL_LPUART_ISR_RXFT
LL_LPUART_ISR_RXNE_RXFNE
LL_LPUART_ISR_SBKF
LL_LPUART_ISR_TC
LL_LPUART_ISR_TEACK
LL_LPUART_ISR_TXE_TXFNF
LL_LPUART_ISR_TXFE
LL_LPUART_ISR_TXFT
LL_LPUART_ISR_WUF
IT Defines
LL_LPUART_CR1_IDLEIE
LL_LPUART_CR1_PEIE
LL_LPUART_CR1_RXFFIE
LL_LPUART_CR1_RXNEIE_RXFNEIE
LL_LPUART_CR1_TCIE
LL_LPUART_CR1_TXEIE_TXFNFIE
LL_LPUART_CR1_TXFEIE
LL_LPUART_CR3_CTSIE
LL_LPUART_CR3_EIE
LL_LPUART_CR3_RXFTIE
LL_LPUART_CR3_TXFTIE
LL_LPUART_CR3_WUFIE
FIFO Threshold
LL_LPUART_FIFOTHRESHOLD_1_4
LL_LPUART_FIFOTHRESHOLD_1_8
LL_LPUART_FIFOTHRESHOLD_3_4
LL_LPUART_FIFOTHRESHOLD_7_8
LL_LPUART_FIFOTHRESHOLD_8_8
Direction
LL_LPUART_DIRECTION_RX
LL_LPUART_DIRECTION_TX
LL_LPUART_DIRECTION_TX_RX
Parity Control
LL_LPUART_PARITY_NONE
LL_LPUART_PARITY_ODD
Wakeup
LL_LPUART_WAKEUP_IDLELINE
Datawidth
LL_LPUART_DATAWIDTH_8B
LL_LPUART_DATAWIDTH_9B
Clock Source Prescaler
LL_LPUART_PRESCALER_DIV10
LL_LPUART_PRESCALER_DIV12
LL_LPUART_PRESCALER_DIV128
LL_LPUART_PRESCALER_DIV16
LL_LPUART_PRESCALER_DIV2
LL_LPUART_PRESCALER_DIV256
LL_LPUART_PRESCALER_DIV32
LL_LPUART_PRESCALER_DIV4
LL_LPUART_PRESCALER_DIV6
LL_LPUART_PRESCALER_DIV64
LL_LPUART_PRESCALER_DIV8
Stop Bits
LL_LPUART_STOPBITS_2
TX RX Pins Swap
LL_LPUART_TXRX_SWAPPED
RX Pin Active Level Inversion
LL_LPUART_RXPIN_LEVEL_STANDARD
TX Pin Active Level Inversion
LL_LPUART_TXPIN_LEVEL_STANDARD
Binary Data Inversion
LL_LPUART_BINARY_LOGIC_POSITIVE
Bit Order
LL_LPUART_BITORDER_MSBFIRST
Address Length Detection
LL_LPUART_ADDRESS_DETECT_7B
Hardware Control
LL_LPUART_HWCONTROL_NONE
LL_LPUART_HWCONTROL_RTS
LL_LPUART_HWCONTROL_RTS_CTS
Wakeup Activation
LL_LPUART_WAKEUP_ON_RXNE
LL_LPUART_WAKEUP_ON_STARTBIT
Driver Enable Polarity
LL_LPUART_DE_POLARITY_LOW
DMA Register Data
LL_LPUART_DMA_REG_DATA_TRANSMIT
LPUART Exported Macros
LL_LPUART_WriteReg
Helper Macros
LPUART Exported Functions
LL_LPUART_ConfigFIFOsThreshold
LL_LPUART_ConfigNodeAddress
LL_LPUART_Disable
LL_LPUART_DisableCTSHWFlowCtrl
LL_LPUART_DisableDirectionRx
LL_LPUART_DisableDirectionTx
LL_LPUART_DisableFIFO
LL_LPUART_DisableInStopMode
LL_LPUART_DisableMuteMode
LL_LPUART_DisableOverrunDetect
LL_LPUART_DisableRTSHWFlowCtrl
LL_LPUART_Enable
LL_LPUART_EnableCTSHWFlowCtrl
LL_LPUART_EnableDirectionRx
LL_LPUART_EnableDirectionTx
LL_LPUART_EnableFIFO
LL_LPUART_EnableInStopMode
LL_LPUART_EnableMuteMode
LL_LPUART_EnableOverrunDetect
LL_LPUART_EnableRTSHWFlowCtrl
LL_LPUART_GetBaudRate
LL_LPUART_GetBinaryDataLogic
LL_LPUART_GetDataWidth
LL_LPUART_GetHWFlowCtrl
LL_LPUART_GetNodeAddress
LL_LPUART_GetNodeAddressLen
LL_LPUART_GetParity
LL_LPUART_GetPrescaler
LL_LPUART_GetRXFIFOThreshold
LL_LPUART_GetRXPinLevel
LL_LPUART_GetStopBitsLength
LL_LPUART_GetTransferBitOrder
LL_LPUART_GetTransferDirection
LL_LPUART_GetTXFIFOThreshold
LL_LPUART_GetTXPinLevel
LL_LPUART_GetTXRXSwap
LL_LPUART_GetWakeUpMethod
LL_LPUART_GetWKUPType
LL_LPUART_IsEnabled
LL_LPUART_IsEnabledFIFO
LL_LPUART_IsEnabledInStopMode
LL_LPUART_IsEnabledMuteMode
LL_LPUART_IsEnabledOverrunDetect
LL_LPUART_SetBaudRate
LL_LPUART_SetBinaryDataLogic
LL_LPUART_SetDataWidth
LL_LPUART_SetHWFlowCtrl
LL_LPUART_SetParity
LL_LPUART_SetPrescaler
LL_LPUART_SetRXFIFOThreshold
LL_LPUART_SetRXPinLevel
LL_LPUART_SetStopBitsLength
LL_LPUART_SetTransferBitOrder
LL_LPUART_SetTransferDirection
LL_LPUART_SetTXFIFOThreshold
LL_LPUART_SetTXPinLevel
LL_LPUART_SetTXRXSwap
LL_LPUART_SetWakeUpMethod
LL_LPUART_SetWKUPType
Configuration functions related to Half Duplex feature
LL_LPUART_EnableHalfDuplex
LL_LPUART_IsEnabledHalfDuplex
Configuration functions related to Driver Enable feature
LL_LPUART_EnableDEMode
LL_LPUART_GetDEAssertionTime
LL_LPUART_GetDEDeassertionTime
LL_LPUART_GetDESignalPolarity
LL_LPUART_IsEnabledDEMode
LL_LPUART_SetDEAssertionTime
LL_LPUART_SetDEDeassertionTime
LL_LPUART_SetDESignalPolarity
FLAG_Management
LL_LPUART_IsActiveFlag_TXE
Functions
LL_LPUART_ClearFlag_FE
LL_LPUART_ClearFlag_IDLE
LL_LPUART_ClearFlag_nCTS
LL_LPUART_ClearFlag_NE
LL_LPUART_ClearFlag_ORE
LL_LPUART_ClearFlag_PE
LL_LPUART_ClearFlag_TC
LL_LPUART_ClearFlag_WKUP
LL_LPUART_IsActiveFlag_BUSY
LL_LPUART_IsActiveFlag_CM
LL_LPUART_IsActiveFlag_CTS
LL_LPUART_IsActiveFlag_FE
LL_LPUART_IsActiveFlag_IDLE
LL_LPUART_IsActiveFlag_nCTS
LL_LPUART_IsActiveFlag_NE
LL_LPUART_IsActiveFlag_ORE
LL_LPUART_IsActiveFlag_PE
LL_LPUART_IsActiveFlag_REACK
LL_LPUART_IsActiveFlag_RWU
LL_LPUART_IsActiveFlag_RXFF
LL_LPUART_IsActiveFlag_RXFT
LL_LPUART_IsActiveFlag_RXNE_RXFNE
LL_LPUART_IsActiveFlag_SBK
LL_LPUART_IsActiveFlag_TC
LL_LPUART_IsActiveFlag_TEACK
LL_LPUART_IsActiveFlag_TXE_TXFNF
LL_LPUART_IsActiveFlag_TXFE
LL_LPUART_IsActiveFlag_TXFT
LL_LPUART_IsActiveFlag_WKUP
IT_Management
LL_LPUART_DisableIT_TXE
LL_LPUART_EnableIT_RXNE
LL_LPUART_EnableIT_TXE
LL_LPUART_IsEnabledIT_RXNE
LL_LPUART_IsEnabledIT_TXE
Functions
LL_LPUART_DisableIT_CTS
LL_LPUART_DisableIT_ERROR
LL_LPUART_DisableIT_IDLE
LL_LPUART_DisableIT_PE
LL_LPUART_DisableIT_RXFF
LL_LPUART_DisableIT_RXFT
LL_LPUART_DisableIT_RXNE_RXFNE
LL_LPUART_DisableIT_TC
LL_LPUART_DisableIT_TXE_TXFNF
LL_LPUART_DisableIT_TXFE
LL_LPUART_DisableIT_TXFT
LL_LPUART_DisableIT_WKUP
LL_LPUART_EnableIT_CM
LL_LPUART_EnableIT_CTS
LL_LPUART_EnableIT_ERROR
LL_LPUART_EnableIT_IDLE
LL_LPUART_EnableIT_PE
LL_LPUART_EnableIT_RXFF
LL_LPUART_EnableIT_RXFT
LL_LPUART_EnableIT_RXNE_RXFNE
LL_LPUART_EnableIT_TC
LL_LPUART_EnableIT_TXE_TXFNF
LL_LPUART_EnableIT_TXFE
LL_LPUART_EnableIT_TXFT
LL_LPUART_EnableIT_WKUP
LL_LPUART_IsEnabledIT_CM
LL_LPUART_IsEnabledIT_CTS
LL_LPUART_IsEnabledIT_ERROR
LL_LPUART_IsEnabledIT_IDLE
LL_LPUART_IsEnabledIT_PE
LL_LPUART_IsEnabledIT_RXFF
LL_LPUART_IsEnabledIT_RXFT
LL_LPUART_IsEnabledIT_RXNE_RXFNE
LL_LPUART_IsEnabledIT_TC
LL_LPUART_IsEnabledIT_TXE_TXFNF
LL_LPUART_IsEnabledIT_TXFE
LL_LPUART_IsEnabledIT_TXFT
LL_LPUART_IsEnabledIT_WKUP
DMA_Management
LL_LPUART_DisableDMAReq_RX
LL_LPUART_DisableDMAReq_TX
LL_LPUART_DMA_GetRegAddr
LL_LPUART_EnableDMADeactOnRxErr
LL_LPUART_EnableDMAReq_RX
LL_LPUART_EnableDMAReq_TX
LL_LPUART_IsEnabledDMADeactOnRxErr
LL_LPUART_IsEnabledDMAReq_RX
LL_LPUART_IsEnabledDMAReq_TX
Data_Management
LL_LPUART_ReceiveData9
LL_LPUART_TransmitData8
LL_LPUART_TransmitData9
Execution
LL_LPUART_RequestEnterMuteMode
LL_LPUART_RequestRxDataFlush
LL_LPUART_RequestTxDataFlush
Initialization and de-initialization functions
LL_LPUART_Init
LL_LPUART_StructInit
OPAMP
OPAMP_TRIMMING_VALUE_MASK
OPAMP Private Macros
IS_LL_OPAMP_FUNCTIONAL_MODE
IS_LL_OPAMP_INPUT_INVERTING
IS_LL_OPAMP_INPUT_NONINVERTING
IS_LL_OPAMP_POWER_MODE
OPAMP Exported Init structure
OPAMP Exported Constants
LL_OPAMP_MODE_FUNCTIONAL
OPAMP functional mode
LL_OPAMP_MODE_PGA
LL_OPAMP_MODE_PGA_IO0
LL_OPAMP_MODE_PGA_IO0_BIAS
LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
LL_OPAMP_MODE_STANDALONE
OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
OPAMP input non-inverting
LL_OPAMP_INPUT_NONINVERT_IO0
LL_OPAMP_INPUT_NONINVERT_IO1
LL_OPAMP_INPUT_NONINVERT_IO2
LL_OPAMP_INPUT_NONINVERT_IO3
OPAMP input inverting
LL_OPAMP_INPUT_INVERT_IO0
LL_OPAMP_INPUT_INVERT_IO1
OPAMP input non-inverting secondary
LL_OPAMP_INPUT_NONINVERT_IO0_SEC
LL_OPAMP_INPUT_NONINVERT_IO1_SEC
LL_OPAMP_INPUT_NONINVERT_IO2_SEC
LL_OPAMP_INPUT_NONINVERT_IO3_SEC
OPAMP input inverting secondary
LL_OPAMP_INPUT_INVERT_IO0_SEC
LL_OPAMP_INPUT_INVERT_IO1_SEC
LL_OPAMP_INPUT_INVERT_PGA_SEC
OPAMP internal output mode
LL_OPAMP_INTERNAL_OUPUT_ENABLED
LL_OPAMP_INTERNAL_OUTPUT_DISABLED
LL_OPAMP_INTERNAL_OUTPUT_ENABLED
OPAMP inputs multiplexer mode
LL_OPAMP_INPUT_MUX_TIM1_CH6
LL_OPAMP_INPUT_MUX_TIM20_CH6
LL_OPAMP_INPUT_MUX_TIM8_CH6
OPAMP PowerMode
LL_OPAMP_POWERMODE_NORMAL
LL_OPAMP_POWERMODE_NORMALSPEED
OPAMP trimming mode
LL_OPAMP_TRIMMING_USER
OPAMP trimming of transistors differential pair NMOS or PMOS
LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA
LL_OPAMP_TRIMMING_PMOS
LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA
LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
Definitions of OPAMP hardware constraints delays
OPAMP Exported Macros
LL_OPAMP_WriteReg
OPAMP Exported Functions
LL_OPAMP_GetMode
LL_OPAMP_GetPGAGain
LL_OPAMP_GetPowerMode
LL_OPAMP_SetFunctionalMode
LL_OPAMP_SetMode
LL_OPAMP_SetPGAGain
LL_OPAMP_SetPowerMode
Configuration of OPAMP inputs
LL_OPAMP_GetInputInvertingSecondary
LL_OPAMP_GetInputNonInverting
LL_OPAMP_GetInputNonInvertingSecondary
LL_OPAMP_GetInputsMuxMode
LL_OPAMP_GetInternalOutput
LL_OPAMP_SetInputInverting
LL_OPAMP_SetInputInvertingSecondary
LL_OPAMP_SetInputNonInverting
LL_OPAMP_SetInputNonInvertingSecondary
LL_OPAMP_SetInputsMuxMode
LL_OPAMP_SetInternalOutput
Configuration and operation of OPAMP trimming
LL_OPAMP_GetTrimmingMode
LL_OPAMP_GetTrimmingValue
LL_OPAMP_IsCalibrationOutputSet
LL_OPAMP_SetCalibrationSelection
LL_OPAMP_SetTrimmingMode
LL_OPAMP_SetTrimmingValue
Operation on OPAMP instance
LL_OPAMP_Enable
LL_OPAMP_IsEnabled
LL_OPAMP_IsLocked
LL_OPAMP_IsTimerMuxLocked
LL_OPAMP_Lock
LL_OPAMP_LockTimerMux
Initialization and de-initialization functions
LL_OPAMP_Init
LL_OPAMP_StructInit
PWR
LL_PWR_SCR_CWUF
LL_PWR_SCR_CWUF1
LL_PWR_SCR_CWUF2
LL_PWR_SCR_CWUF3
LL_PWR_SCR_CWUF4
LL_PWR_SCR_CWUF5
Get Flags Defines
LL_PWR_SR1_WUF1
LL_PWR_SR1_WUF2
LL_PWR_SR1_WUF3
LL_PWR_SR1_WUF4
LL_PWR_SR1_WUF5
LL_PWR_SR1_WUFI
LL_PWR_SR2_PVDO
LL_PWR_SR2_PVMO1
LL_PWR_SR2_PVMO2
LL_PWR_SR2_PVMO3
LL_PWR_SR2_PVMO4
LL_PWR_SR2_REGLPF
LL_PWR_SR2_REGLPS
LL_PWR_SR2_VOSF
REGU VOLTAGE
LL_PWR_REGU_VOLTAGE_SCALE2
MODE PWR
LL_PWR_MODE_STANDBY
LL_PWR_MODE_STOP0
LL_PWR_MODE_STOP1
Peripheral voltage monitoring
LL_PWR_PVM_VDDA_COMP
LL_PWR_PVM_VDDA_FASTDAC
LL_PWR_PVM_VDDA_OPAMP_DAC
PVDLEVEL
LL_PWR_PVDLEVEL_1
LL_PWR_PVDLEVEL_2
LL_PWR_PVDLEVEL_3
LL_PWR_PVDLEVEL_4
LL_PWR_PVDLEVEL_5
LL_PWR_PVDLEVEL_6
LL_PWR_PVDLEVEL_7
WAKEUP
LL_PWR_WAKEUP_PIN2
LL_PWR_WAKEUP_PIN3
LL_PWR_WAKEUP_PIN4
LL_PWR_WAKEUP_PIN5
BATT CHARG RESISTOR
LL_PWR_BATT_CHARGRESISTOR_1_5K
GPIO
LL_PWR_GPIO_B
LL_PWR_GPIO_C
LL_PWR_GPIO_D
LL_PWR_GPIO_E
LL_PWR_GPIO_F
LL_PWR_GPIO_G
GPIO BIT
LL_PWR_GPIO_BIT_1
LL_PWR_GPIO_BIT_10
LL_PWR_GPIO_BIT_11
LL_PWR_GPIO_BIT_12
LL_PWR_GPIO_BIT_13
LL_PWR_GPIO_BIT_14
LL_PWR_GPIO_BIT_15
LL_PWR_GPIO_BIT_2
LL_PWR_GPIO_BIT_3
LL_PWR_GPIO_BIT_4
LL_PWR_GPIO_BIT_5
LL_PWR_GPIO_BIT_6
LL_PWR_GPIO_BIT_7
LL_PWR_GPIO_BIT_8
LL_PWR_GPIO_BIT_9
PWR Exported Macros
LL_PWR_WriteReg
PWR Exported Functions
LL_PWR_DisableBkUpAccess
LL_PWR_DisableGPIOPullDown
LL_PWR_DisableGPIOPullUp
LL_PWR_DisableInternWU
LL_PWR_DisableLowPowerRunMode
LL_PWR_DisablePUPDCfg
LL_PWR_DisablePVD
LL_PWR_DisablePVM
LL_PWR_DisableRange1BoostMode
LL_PWR_DisableSRAM2Retention
LL_PWR_DisableUCPDDeadBattery
LL_PWR_DisableUCPDStandbyMode
LL_PWR_DisableWakeUpPin
LL_PWR_EnableBatteryCharging
LL_PWR_EnableBkUpAccess
LL_PWR_EnableGPIOPullDown
LL_PWR_EnableGPIOPullUp
LL_PWR_EnableInternWU
LL_PWR_EnableLowPowerRunMode
LL_PWR_EnablePUPDCfg
LL_PWR_EnablePVD
LL_PWR_EnablePVM
LL_PWR_EnableRange1BoostMode
LL_PWR_EnableSRAM2Retention
LL_PWR_EnableUCPDDeadBattery
LL_PWR_EnableUCPDStandbyMode
LL_PWR_EnableWakeUpPin
LL_PWR_EnterLowPowerRunMode
LL_PWR_ExitLowPowerRunMode
LL_PWR_GetBattChargResistor
LL_PWR_GetPowerMode
LL_PWR_GetPVDLevel
LL_PWR_GetRegulVoltageScaling
LL_PWR_IsEnabledBatteryCharging
LL_PWR_IsEnabledBkUpAccess
LL_PWR_IsEnabledGPIOPullDown
LL_PWR_IsEnabledGPIOPullUp
LL_PWR_IsEnabledInternWU
LL_PWR_IsEnabledLowPowerRunMode
LL_PWR_IsEnabledPUPDCfg
LL_PWR_IsEnabledPVD
LL_PWR_IsEnabledPVM
LL_PWR_IsEnabledRange1BoostMode
LL_PWR_IsEnabledSRAM2Retention
LL_PWR_IsEnabledUCPDDeadBattery
LL_PWR_IsEnabledUCPDStandbyMode
LL_PWR_IsEnabledWakeUpPin
LL_PWR_IsWakeUpPinPolarityLow
LL_PWR_SetBattChargResistor
LL_PWR_SetPowerMode
LL_PWR_SetPVDLevel
LL_PWR_SetRegulVoltageScaling
LL_PWR_SetWakeUpPinPolarityHigh
LL_PWR_SetWakeUpPinPolarityLow
FLAG_Management
LL_PWR_ClearFlag_WU
LL_PWR_ClearFlag_WU1
LL_PWR_ClearFlag_WU2
LL_PWR_ClearFlag_WU3
LL_PWR_ClearFlag_WU4
LL_PWR_ClearFlag_WU5
LL_PWR_IsActiveFlag_InternWU
LL_PWR_IsActiveFlag_PVDO
LL_PWR_IsActiveFlag_PVMO1
LL_PWR_IsActiveFlag_PVMO2
LL_PWR_IsActiveFlag_PVMO3
LL_PWR_IsActiveFlag_PVMO4
LL_PWR_IsActiveFlag_REGLPF
LL_PWR_IsActiveFlag_REGLPS
LL_PWR_IsActiveFlag_SB
LL_PWR_IsActiveFlag_VOS
LL_PWR_IsActiveFlag_WU1
LL_PWR_IsActiveFlag_WU2
LL_PWR_IsActiveFlag_WU3
LL_PWR_IsActiveFlag_WU4
LL_PWR_IsActiveFlag_WU5
De-initialization function
Legacy functions name
LL_PWR_DisableStandByModePD
LL_PWR_DisableUSBDeadBattery
LL_PWR_DisableUSBStandByModePD
LL_PWR_EnableDeadBatteryPD
LL_PWR_EnableStandByModePD
LL_PWR_EnableUSBDeadBattery
LL_PWR_EnableUSBStandByModePD
LL_PWR_IsActiveFlag_VOSF
LL_PWR_IsEnabledUSBDeadBattery
LL_PWR_IsEnabledUSBStandByModePD
RCC
RCC_GetPCLK1ClockFreq
RCC_GetPCLK2ClockFreq
RCC_GetSystemClockFreq
RCC_PLL_GetFreqDomain_48M
RCC_PLL_GetFreqDomain_ADC
RCC_PLL_GetFreqDomain_SYS
RCC Private Variables
RCC Private Constants
RCC_OFFSET_CCIPR2
RCC Private Macros
IS_LL_RCC_FDCAN_CLKSOURCE
IS_LL_RCC_I2C_CLKSOURCE
IS_LL_RCC_I2S_CLKSOURCE
IS_LL_RCC_LPTIM_CLKSOURCE
IS_LL_RCC_LPUART_CLKSOURCE
IS_LL_RCC_QUADSPI_CLKSOURCE
IS_LL_RCC_RNG_CLKSOURCE
IS_LL_RCC_SAI_CLKSOURCE
IS_LL_RCC_UART_CLKSOURCE
IS_LL_RCC_USART_CLKSOURCE
IS_LL_RCC_USB_CLKSOURCE
RCC Exported Types
RCC Exported Constants
Clear Flags Defines
LL_RCC_CICR_HSERDYC
LL_RCC_CICR_HSI48RDYC
LL_RCC_CICR_HSIRDYC
LL_RCC_CICR_LSECSSC
LL_RCC_CICR_LSERDYC
LL_RCC_CICR_LSIRDYC
LL_RCC_CICR_PLLRDYC
Get Flags Defines
LL_RCC_CIFR_HSERDYF
LL_RCC_CIFR_HSI48RDYF
LL_RCC_CIFR_HSIRDYF
LL_RCC_CIFR_LSECSSF
LL_RCC_CIFR_LSERDYF
LL_RCC_CIFR_LSIRDYF
LL_RCC_CIFR_PLLRDYF
LL_RCC_CSR_BORRSTF
LL_RCC_CSR_IWDGRSTF
LL_RCC_CSR_LPWRRSTF
LL_RCC_CSR_OBLRSTF
LL_RCC_CSR_PINRSTF
LL_RCC_CSR_SFTRSTF
LL_RCC_CSR_WWDGRSTF
IT Defines
LL_RCC_CIER_HSI48RDYIE
LL_RCC_CIER_HSIRDYIE
LL_RCC_CIER_LSECSSIE
LL_RCC_CIER_LSERDYIE
LL_RCC_CIER_LSIRDYIE
LL_RCC_CIER_PLLRDYIE
LSE oscillator drive capability
LL_RCC_LSEDRIVE_LOW
LL_RCC_LSEDRIVE_MEDIUMHIGH
LL_RCC_LSEDRIVE_MEDIUMLOW
LSCO Selection
LL_RCC_LSCO_CLKSOURCE_LSI
System clock switch
LL_RCC_SYS_CLKSOURCE_HSI
LL_RCC_SYS_CLKSOURCE_PLL
System clock switch status
LL_RCC_SYS_CLKSOURCE_STATUS_HSI
LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AHB prescaler
LL_RCC_SYSCLK_DIV_128
LL_RCC_SYSCLK_DIV_16
LL_RCC_SYSCLK_DIV_2
LL_RCC_SYSCLK_DIV_256
LL_RCC_SYSCLK_DIV_4
LL_RCC_SYSCLK_DIV_512
LL_RCC_SYSCLK_DIV_64
LL_RCC_SYSCLK_DIV_8
APB low-speed prescaler (APB1)
LL_RCC_APB1_DIV_16
LL_RCC_APB1_DIV_2
LL_RCC_APB1_DIV_4
LL_RCC_APB1_DIV_8
APB high-speed prescaler (APB2)
LL_RCC_APB2_DIV_16
LL_RCC_APB2_DIV_2
LL_RCC_APB2_DIV_4
LL_RCC_APB2_DIV_8
MCO1 SOURCE selection
LL_RCC_MCO1SOURCE_HSI
LL_RCC_MCO1SOURCE_HSI48
LL_RCC_MCO1SOURCE_LSE
LL_RCC_MCO1SOURCE_LSI
LL_RCC_MCO1SOURCE_NOCLOCK
LL_RCC_MCO1SOURCE_PLLCLK
LL_RCC_MCO1SOURCE_SYSCLK
MCO1 prescaler
LL_RCC_MCO1_DIV_16
LL_RCC_MCO1_DIV_2
LL_RCC_MCO1_DIV_4
LL_RCC_MCO1_DIV_8
Peripheral clock frequency
LL_RCC_PERIPH_FREQUENCY_NO
Peripheral USART clock source selection
LL_RCC_USART1_CLKSOURCE_LSE
LL_RCC_USART1_CLKSOURCE_PCLK2
LL_RCC_USART1_CLKSOURCE_SYSCLK
LL_RCC_USART2_CLKSOURCE_HSI
LL_RCC_USART2_CLKSOURCE_LSE
LL_RCC_USART2_CLKSOURCE_PCLK1
LL_RCC_USART2_CLKSOURCE_SYSCLK
LL_RCC_USART3_CLKSOURCE_HSI
LL_RCC_USART3_CLKSOURCE_LSE
LL_RCC_USART3_CLKSOURCE_PCLK1
LL_RCC_USART3_CLKSOURCE_SYSCLK
Peripheral UART clock source selection
LL_RCC_UART4_CLKSOURCE_LSE
LL_RCC_UART4_CLKSOURCE_PCLK1
LL_RCC_UART4_CLKSOURCE_SYSCLK
LL_RCC_UART5_CLKSOURCE_HSI
LL_RCC_UART5_CLKSOURCE_LSE
LL_RCC_UART5_CLKSOURCE_PCLK1
LL_RCC_UART5_CLKSOURCE_SYSCLK
Peripheral LPUART clock source selection
LL_RCC_LPUART1_CLKSOURCE_LSE
LL_RCC_LPUART1_CLKSOURCE_PCLK1
LL_RCC_LPUART1_CLKSOURCE_SYSCLK
Peripheral I2C clock source selection
LL_RCC_I2C1_CLKSOURCE_PCLK1
LL_RCC_I2C1_CLKSOURCE_SYSCLK
LL_RCC_I2C2_CLKSOURCE_HSI
LL_RCC_I2C2_CLKSOURCE_PCLK1
LL_RCC_I2C2_CLKSOURCE_SYSCLK
LL_RCC_I2C3_CLKSOURCE_HSI
LL_RCC_I2C3_CLKSOURCE_PCLK1
LL_RCC_I2C3_CLKSOURCE_SYSCLK
LL_RCC_I2C4_CLKSOURCE_HSI
LL_RCC_I2C4_CLKSOURCE_PCLK1
LL_RCC_I2C4_CLKSOURCE_SYSCLK
Peripheral LPTIM clock source selection
LL_RCC_LPTIM1_CLKSOURCE_LSE
LL_RCC_LPTIM1_CLKSOURCE_LSI
LL_RCC_LPTIM1_CLKSOURCE_PCLK1
Peripheral SAI clock source selection
LL_RCC_SAI1_CLKSOURCE_PIN
LL_RCC_SAI1_CLKSOURCE_PLL
LL_RCC_SAI1_CLKSOURCE_SYSCLK
Peripheral I2S clock source selection
LL_RCC_I2S_CLKSOURCE_PIN
LL_RCC_I2S_CLKSOURCE_PLL
LL_RCC_I2S_CLKSOURCE_SYSCLK
Peripheral FDCAN clock source selection
LL_RCC_FDCAN_CLKSOURCE_PCLK1
LL_RCC_FDCAN_CLKSOURCE_PLL
Peripheral RNG clock source selection
LL_RCC_RNG_CLKSOURCE_PLL
Peripheral USB clock source selection
LL_RCC_USB_CLKSOURCE_PLL
Peripheral ADC clock source selection
LL_RCC_ADC12_CLKSOURCE_PLL
LL_RCC_ADC12_CLKSOURCE_SYSCLK
LL_RCC_ADC345_CLKSOURCE_NONE
LL_RCC_ADC345_CLKSOURCE_PLL
LL_RCC_ADC345_CLKSOURCE_SYSCLK
Peripheral QUADSPI get clock source
LL_RCC_QUADSPI_CLKSOURCE_HSI
LL_RCC_QUADSPI_CLKSOURCE_PLL
LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
Peripheral USART get clock source
LL_RCC_USART2_CLKSOURCE
LL_RCC_USART3_CLKSOURCE
Peripheral UART get clock source
LL_RCC_UART5_CLKSOURCE
Peripheral LPUART get clock source
Peripheral I2C get clock source
LL_RCC_I2C2_CLKSOURCE
LL_RCC_I2C3_CLKSOURCE
LL_RCC_I2C4_CLKSOURCE
Peripheral LPTIM get clock source
Peripheral SAI get clock source
Peripheral I2S get clock source
Peripheral FDCAN get clock source
Peripheral RNG get clock source
Peripheral USB get clock source
Peripheral ADC get clock source
LL_RCC_ADC345_CLKSOURCE
RTC clock source selection
LL_RCC_RTC_CLKSOURCE_LSE
LL_RCC_RTC_CLKSOURCE_LSI
LL_RCC_RTC_CLKSOURCE_NONE
PLL entry clock source
LL_RCC_PLLSOURCE_HSI
LL_RCC_PLLSOURCE_NONE
PLL division factor
LL_RCC_PLLM_DIV_10
LL_RCC_PLLM_DIV_11
LL_RCC_PLLM_DIV_12
LL_RCC_PLLM_DIV_13
LL_RCC_PLLM_DIV_14
LL_RCC_PLLM_DIV_15
LL_RCC_PLLM_DIV_16
LL_RCC_PLLM_DIV_2
LL_RCC_PLLM_DIV_3
LL_RCC_PLLM_DIV_4
LL_RCC_PLLM_DIV_5
LL_RCC_PLLM_DIV_6
LL_RCC_PLLM_DIV_7
LL_RCC_PLLM_DIV_8
LL_RCC_PLLM_DIV_9
PLL division factor (PLLR)
LL_RCC_PLLR_DIV_4
LL_RCC_PLLR_DIV_6
LL_RCC_PLLR_DIV_8
PLL division factor (PLLP)
LL_RCC_PLLP_DIV_11
LL_RCC_PLLP_DIV_12
LL_RCC_PLLP_DIV_13
LL_RCC_PLLP_DIV_14
LL_RCC_PLLP_DIV_15
LL_RCC_PLLP_DIV_16
LL_RCC_PLLP_DIV_17
LL_RCC_PLLP_DIV_18
LL_RCC_PLLP_DIV_19
LL_RCC_PLLP_DIV_2
LL_RCC_PLLP_DIV_20
LL_RCC_PLLP_DIV_21
LL_RCC_PLLP_DIV_22
LL_RCC_PLLP_DIV_23
LL_RCC_PLLP_DIV_24
LL_RCC_PLLP_DIV_25
LL_RCC_PLLP_DIV_26
LL_RCC_PLLP_DIV_27
LL_RCC_PLLP_DIV_28
LL_RCC_PLLP_DIV_29
LL_RCC_PLLP_DIV_3
LL_RCC_PLLP_DIV_30
LL_RCC_PLLP_DIV_31
LL_RCC_PLLP_DIV_4
LL_RCC_PLLP_DIV_5
LL_RCC_PLLP_DIV_6
LL_RCC_PLLP_DIV_7
LL_RCC_PLLP_DIV_8
LL_RCC_PLLP_DIV_9
PLL division factor (PLLQ)
LL_RCC_PLLQ_DIV_4
LL_RCC_PLLQ_DIV_6
LL_RCC_PLLQ_DIV_8
RCC Exported Macros
LL_RCC_WriteReg
Calculate frequencies
__LL_RCC_CALC_PCLK1_FREQ
__LL_RCC_CALC_PCLK2_FREQ
__LL_RCC_CALC_PLLCLK_48M_FREQ
__LL_RCC_CALC_PLLCLK_ADC_FREQ
__LL_RCC_CALC_PLLCLK_FREQ
RCC Exported Functions
LL_RCC_HSE_DisableBypass
LL_RCC_HSE_Enable
LL_RCC_HSE_EnableBypass
LL_RCC_HSE_EnableCSS
LL_RCC_HSE_IsReady
HSI
LL_RCC_HSI_DisableInStopMode
LL_RCC_HSI_Enable
LL_RCC_HSI_EnableInStopMode
LL_RCC_HSI_GetCalibration
LL_RCC_HSI_GetCalibTrimming
LL_RCC_HSI_IsReady
LL_RCC_HSI_SetCalibTrimming
HSI48
LL_RCC_HSI48_Enable
LL_RCC_HSI48_GetCalibration
LL_RCC_HSI48_IsReady
LSE
LL_RCC_LSE_DisableBypass
LL_RCC_LSE_DisableCSS
LL_RCC_LSE_Enable
LL_RCC_LSE_EnableBypass
LL_RCC_LSE_EnableCSS
LL_RCC_LSE_GetDriveCapability
LL_RCC_LSE_IsCSSDetected
LL_RCC_LSE_IsReady
LL_RCC_LSE_SetDriveCapability
LSI
LL_RCC_LSI_Enable
LL_RCC_LSI_IsReady
LSCO
LL_RCC_LSCO_Enable
LL_RCC_LSCO_GetSource
LL_RCC_LSCO_SetSource
System
LL_RCC_GetAPB1Prescaler
LL_RCC_GetAPB2Prescaler
LL_RCC_GetSysClkSource
LL_RCC_SetAHBPrescaler
LL_RCC_SetAPB1Prescaler
LL_RCC_SetAPB2Prescaler
LL_RCC_SetSysClkSource
MCO
Peripheral Clock Source
LL_RCC_GetFDCANClockSource
LL_RCC_GetI2CClockSource
LL_RCC_GetI2SClockSource
LL_RCC_GetLPTIMClockSource
LL_RCC_GetLPUARTClockSource
LL_RCC_GetQUADSPIClockSource
LL_RCC_GetRNGClockSource
LL_RCC_GetSAIClockSource
LL_RCC_GetUARTClockSource
LL_RCC_GetUSARTClockSource
LL_RCC_GetUSBClockSource
LL_RCC_SetADCClockSource
LL_RCC_SetFDCANClockSource
LL_RCC_SetI2CClockSource
LL_RCC_SetI2SClockSource
LL_RCC_SetLPTIMClockSource
LL_RCC_SetLPUARTClockSource
LL_RCC_SetQUADSPIClockSource
LL_RCC_SetRNGClockSource
LL_RCC_SetSAIClockSource
LL_RCC_SetUARTClockSource
LL_RCC_SetUSARTClockSource
LL_RCC_SetUSBClockSource
RTC
LL_RCC_EnableRTC
LL_RCC_ForceBackupDomainReset
LL_RCC_GetRTCClockSource
LL_RCC_IsEnabledRTC
LL_RCC_ReleaseBackupDomainReset
LL_RCC_SetRTCClockSource
PLL
LL_RCC_PLL_ConfigDomain_ADC
LL_RCC_PLL_ConfigDomain_SYS
LL_RCC_PLL_Disable
LL_RCC_PLL_DisableDomain_48M
LL_RCC_PLL_DisableDomain_ADC
LL_RCC_PLL_DisableDomain_SYS
LL_RCC_PLL_Enable
LL_RCC_PLL_EnableDomain_48M
LL_RCC_PLL_EnableDomain_ADC
LL_RCC_PLL_EnableDomain_SYS
LL_RCC_PLL_GetDivider
LL_RCC_PLL_GetMainSource
LL_RCC_PLL_GetN
LL_RCC_PLL_GetP
LL_RCC_PLL_GetQ
LL_RCC_PLL_GetR
LL_RCC_PLL_IsEnabledDomain_48M
LL_RCC_PLL_IsEnabledDomain_ADC
LL_RCC_PLL_IsEnabledDomain_SYS
LL_RCC_PLL_IsReady
LL_RCC_PLL_SetMainSource
FLAG Management
LL_RCC_ClearFlag_HSERDY
LL_RCC_ClearFlag_HSI48RDY
LL_RCC_ClearFlag_HSIRDY
LL_RCC_ClearFlag_LSECSS
LL_RCC_ClearFlag_LSERDY
LL_RCC_ClearFlag_LSIRDY
LL_RCC_ClearFlag_PLLRDY
LL_RCC_ClearResetFlags
LL_RCC_IsActiveFlag_BORRST
LL_RCC_IsActiveFlag_HSECSS
LL_RCC_IsActiveFlag_HSERDY
LL_RCC_IsActiveFlag_HSI48RDY
LL_RCC_IsActiveFlag_HSIRDY
LL_RCC_IsActiveFlag_IWDGRST
LL_RCC_IsActiveFlag_LPWRRST
LL_RCC_IsActiveFlag_LSECSS
LL_RCC_IsActiveFlag_LSERDY
LL_RCC_IsActiveFlag_LSIRDY
LL_RCC_IsActiveFlag_OBLRST
LL_RCC_IsActiveFlag_PINRST
LL_RCC_IsActiveFlag_PLLRDY
LL_RCC_IsActiveFlag_SFTRST
LL_RCC_IsActiveFlag_WWDGRST
IT Management
LL_RCC_DisableIT_HSI48RDY
LL_RCC_DisableIT_HSIRDY
LL_RCC_DisableIT_LSECSS
LL_RCC_DisableIT_LSERDY
LL_RCC_DisableIT_LSIRDY
LL_RCC_DisableIT_PLLRDY
LL_RCC_EnableIT_HSERDY
LL_RCC_EnableIT_HSI48RDY
LL_RCC_EnableIT_HSIRDY
LL_RCC_EnableIT_LSECSS
LL_RCC_EnableIT_LSERDY
LL_RCC_EnableIT_LSIRDY
LL_RCC_EnableIT_PLLRDY
LL_RCC_IsEnabledIT_HSERDY
LL_RCC_IsEnabledIT_HSI48RDY
LL_RCC_IsEnabledIT_HSIRDY
LL_RCC_IsEnabledIT_LSECSS
LL_RCC_IsEnabledIT_LSERDY
LL_RCC_IsEnabledIT_LSIRDY
LL_RCC_IsEnabledIT_PLLRDY
De-initialization function
Get system and peripherals clocks frequency functions
LL_RCC_GetFDCANClockFreq
LL_RCC_GetI2CClockFreq
LL_RCC_GetI2SClockFreq
LL_RCC_GetLPTIMClockFreq
LL_RCC_GetLPUARTClockFreq
LL_RCC_GetQUADSPIClockFreq
LL_RCC_GetRNGClockFreq
LL_RCC_GetSAIClockFreq
LL_RCC_GetSystemClocksFreq
LL_RCC_GetUARTClockFreq
LL_RCC_GetUSARTClockFreq
LL_RCC_GetUSBClockFreq
RNG
RNG Exported Init structures
RNG Exported Constants
LL_RNG_CED_ENABLE
Get Flags Defines
LL_RNG_SR_CEIS
LL_RNG_SR_DRDY
LL_RNG_SR_SECS
LL_RNG_SR_SEIS
IT Defines
RNG Exported Macros
LL_RNG_WriteReg
RNG Exported Functions
LL_RNG_DisableClkErrorDetect
LL_RNG_Enable
LL_RNG_EnableClkErrorDetect
LL_RNG_IsEnabled
LL_RNG_IsEnabledClkErrorDetect
FLAG Management
LL_RNG_ClearFlag_SEIS
LL_RNG_IsActiveFlag_CECS
LL_RNG_IsActiveFlag_CEIS
LL_RNG_IsActiveFlag_DRDY
LL_RNG_IsActiveFlag_SECS
LL_RNG_IsActiveFlag_SEIS
IT Management
LL_RNG_EnableIT
LL_RNG_IsEnabledIT
Data Management
Initialization and de-initialization functions
LL_RNG_Init
LL_RNG_StructInit
RTC
RTC_INITMODE_TIMEOUT
RTC_LL_INIT_MASK
RTC_LL_RSF_MASK
RTC_OFFSET_DAY
RTC_OFFSET_HOUR
RTC_OFFSET_MINUTE
RTC_OFFSET_MONTH
RTC_OFFSET_WEEKDAY
RTC_SYNCH_PRESC_DEFAULT
RTC_SYNCHRO_TIMEOUT
RTC_WRITE_PROTECTION_DISABLE
RTC_WRITE_PROTECTION_ENABLE_1
RTC_WRITE_PROTECTION_ENABLE_2
RTC Private Macros
IS_LL_RTC_ALMA_MASK
IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL
IS_LL_RTC_ALMB_MASK
IS_LL_RTC_ASYNCH_PREDIV
IS_LL_RTC_DAY
IS_LL_RTC_FORMAT
IS_LL_RTC_HOUR12
IS_LL_RTC_HOUR24
IS_LL_RTC_HOURFORMAT
IS_LL_RTC_MINUTES
IS_LL_RTC_MONTH
IS_LL_RTC_SECONDS
IS_LL_RTC_SYNCH_PREDIV
IS_LL_RTC_TIME_FORMAT
IS_LL_RTC_WEEKDAY
IS_LL_RTC_YEAR
RTC Exported Init structure
LL_RTC_TimeTypeDef
LL_RTC_DateTypeDef
LL_RTC_AlarmTypeDef
RTC Exported Constants
LL_RTC_FORMAT_BIN
RTC Alarm A Date WeekDay
LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY
RTC Alarm B Date WeekDay
LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY
Get Flags Defines
LL_RTC_ICSR_ALRAWF
LL_RTC_ICSR_ALRBWF
LL_RTC_ICSR_INITF
LL_RTC_ICSR_INITS
LL_RTC_ICSR_RECALPF
LL_RTC_ICSR_RSF
LL_RTC_ICSR_SHPF
LL_RTC_ICSR_WUTWF
LL_RTC_SCR_ALRBF
LL_RTC_SCR_ITSF
LL_RTC_SCR_TSF
LL_RTC_SCR_TSOVF
LL_RTC_SCR_WUTF
IT Defines
LL_RTC_CR_ALRBIE
LL_RTC_CR_TSIE
LL_RTC_CR_WUTIE
WEEK DAY
LL_RTC_WEEKDAY_MONDAY
LL_RTC_WEEKDAY_SATURDAY
LL_RTC_WEEKDAY_SUNDAY
LL_RTC_WEEKDAY_THURSDAY
LL_RTC_WEEKDAY_TUESDAY
LL_RTC_WEEKDAY_WEDNESDAY
MONTH
LL_RTC_MONTH_AUGUST
LL_RTC_MONTH_DECEMBER
LL_RTC_MONTH_FEBRUARY
LL_RTC_MONTH_JANUARY
LL_RTC_MONTH_JULY
LL_RTC_MONTH_JUNE
LL_RTC_MONTH_MARCH
LL_RTC_MONTH_MAY
LL_RTC_MONTH_NOVEMBER
LL_RTC_MONTH_OCTOBER
LL_RTC_MONTH_SEPTEMBER
HOUR FORMAT
LL_RTC_HOURFORMAT_AMPM
ALARM OUTPUT
LL_RTC_ALARMOUT_ALMB
LL_RTC_ALARMOUT_DISABLE
LL_RTC_ALARMOUT_WAKEUP
ALARM OUTPUT TYPE
LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
OUTPUT POLARITY PIN
LL_RTC_OUTPUTPOLARITY_PIN_LOW
TIME FORMAT
LL_RTC_TIME_FORMAT_PM
SHIFT SECOND
LL_RTC_SHIFT_SECOND_DELAY
ALARMA MASK
LL_RTC_ALMA_MASK_DATEWEEKDAY
LL_RTC_ALMA_MASK_HOURS
LL_RTC_ALMA_MASK_MINUTES
LL_RTC_ALMA_MASK_NONE
LL_RTC_ALMA_MASK_SECONDS
ALARMA TIME FORMAT
LL_RTC_ALMA_TIME_FORMAT_PM
ALARMB MASK
LL_RTC_ALMB_MASK_DATEWEEKDAY
LL_RTC_ALMB_MASK_HOURS
LL_RTC_ALMB_MASK_MINUTES
LL_RTC_ALMB_MASK_NONE
LL_RTC_ALMB_MASK_SECONDS
ALARMB TIME FORMAT
LL_RTC_ALMB_TIME_FORMAT_PM
TIMESTAMP EDGE
LL_RTC_TIMESTAMP_EDGE_RISING
TIMESTAMP TIME FORMAT
LL_RTC_TS_TIME_FORMAT_PM
TAMPER
LL_RTC_TAMPER_2
LL_RTC_TAMPER_3
TAMPER MASK
LL_RTC_TAMPER_MASK_TAMPER2
LL_RTC_TAMPER_MASK_TAMPER3
TAMPER NO ERASE
LL_RTC_TAMPER_NOERASE_TAMPER2
LL_RTC_TAMPER_NOERASE_TAMPER3
TAMPER DURATION
LL_RTC_TAMPER_DURATION_2RTCCLK
LL_RTC_TAMPER_DURATION_4RTCCLK
LL_RTC_TAMPER_DURATION_8RTCCLK
TAMPER FILTER
LL_RTC_TAMPER_FILTER_4SAMPLE
LL_RTC_TAMPER_FILTER_8SAMPLE
LL_RTC_TAMPER_FILTER_DISABLE
TAMPER SAMPLING FREQUENCY DIVIDER
LL_RTC_TAMPER_SAMPLFREQDIV_16384
LL_RTC_TAMPER_SAMPLFREQDIV_2048
LL_RTC_TAMPER_SAMPLFREQDIV_256
LL_RTC_TAMPER_SAMPLFREQDIV_32768
LL_RTC_TAMPER_SAMPLFREQDIV_4096
LL_RTC_TAMPER_SAMPLFREQDIV_512
LL_RTC_TAMPER_SAMPLFREQDIV_8192
TAMPER ACTIVE LEVEL
LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
INTERNAL TAMPER
LL_RTC_TAMPER_ITAMP3
LL_RTC_TAMPER_ITAMP4
LL_RTC_TAMPER_ITAMP5
LL_RTC_TAMPER_ITAMP6
BACKUP
LL_RTC_BKP_DR1
LL_RTC_BKP_DR10
LL_RTC_BKP_DR11
LL_RTC_BKP_DR12
LL_RTC_BKP_DR13
LL_RTC_BKP_DR14
LL_RTC_BKP_DR15
LL_RTC_BKP_DR16
LL_RTC_BKP_DR17
LL_RTC_BKP_DR18
LL_RTC_BKP_DR19
LL_RTC_BKP_DR2
LL_RTC_BKP_DR20
LL_RTC_BKP_DR21
LL_RTC_BKP_DR22
LL_RTC_BKP_DR23
LL_RTC_BKP_DR24
LL_RTC_BKP_DR25
LL_RTC_BKP_DR26
LL_RTC_BKP_DR27
LL_RTC_BKP_DR28
LL_RTC_BKP_DR29
LL_RTC_BKP_DR3
LL_RTC_BKP_DR30
LL_RTC_BKP_DR31
LL_RTC_BKP_DR4
LL_RTC_BKP_DR5
LL_RTC_BKP_DR6
LL_RTC_BKP_DR7
LL_RTC_BKP_DR8
LL_RTC_BKP_DR9
LL_RTC_BKP_NUMBER
WAKEUP CLOCK DIV
LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
LL_RTC_WAKEUPCLOCK_DIV_16
LL_RTC_WAKEUPCLOCK_DIV_2
LL_RTC_WAKEUPCLOCK_DIV_4
LL_RTC_WAKEUPCLOCK_DIV_8
Calibration output
LL_RTC_CALIB_OUTPUT_512HZ
LL_RTC_CALIB_OUTPUT_NONE
Calibration pulse insertion
LL_RTC_CALIB_INSERTPULSE_SET
Calibration period
LL_RTC_CALIB_PERIOD_32SEC
LL_RTC_CALIB_PERIOD_8SEC
Convert helper Macros
__LL_RTC_CONVERT_BIN2BCD
Date helper Macros
__LL_RTC_GET_MONTH
__LL_RTC_GET_WEEKDAY
__LL_RTC_GET_YEAR
Time helper Macros
__LL_RTC_GET_MINUTE
__LL_RTC_GET_SECOND
RTC Exported Functions
LL_RTC_DisableInitMode
LL_RTC_DisableOutput2
LL_RTC_DisableRefClock
LL_RTC_DisableShadowRegBypass
LL_RTC_DisableTamperOutput
LL_RTC_DisableWriteProtection
LL_RTC_EnableAlarmPullUp
LL_RTC_EnableInitMode
LL_RTC_EnableOutput2
LL_RTC_EnableRefClock
LL_RTC_EnableShadowRegBypass
LL_RTC_EnableTamperOutput
LL_RTC_EnableWriteProtection
LL_RTC_GetAlarmOutEvent
LL_RTC_GetAlarmOutputType
LL_RTC_GetAsynchPrescaler
LL_RTC_GetHourFormat
LL_RTC_GetOutputPolarity
LL_RTC_GetSynchPrescaler
LL_RTC_IsAlarmPullUpEnabled
LL_RTC_IsOutput2Enabled
LL_RTC_IsShadowRegBypassEnabled
LL_RTC_IsTamperOutputEnabled
LL_RTC_SetAlarmOutEvent
LL_RTC_SetAlarmOutputType
LL_RTC_SetAsynchPrescaler
LL_RTC_SetHourFormat
LL_RTC_SetOutputPolarity
LL_RTC_SetSynchPrescaler
Time
LL_RTC_TIME_DecHour
LL_RTC_TIME_DisableDayLightStore
LL_RTC_TIME_EnableDayLightStore
LL_RTC_TIME_Get
LL_RTC_TIME_GetFormat
LL_RTC_TIME_GetHour
LL_RTC_TIME_GetMinute
LL_RTC_TIME_GetSecond
LL_RTC_TIME_GetSubSecond
LL_RTC_TIME_IncHour
LL_RTC_TIME_IsDayLightStoreEnabled
LL_RTC_TIME_SetFormat
LL_RTC_TIME_SetHour
LL_RTC_TIME_SetMinute
LL_RTC_TIME_SetSecond
LL_RTC_TIME_Synchronize
Date
LL_RTC_DATE_Get
LL_RTC_DATE_GetDay
LL_RTC_DATE_GetMonth
LL_RTC_DATE_GetWeekDay
LL_RTC_DATE_GetYear
LL_RTC_DATE_SetDay
LL_RTC_DATE_SetMonth
LL_RTC_DATE_SetWeekDay
LL_RTC_DATE_SetYear
ALARMA
LL_RTC_ALMA_Disable
LL_RTC_ALMA_DisableWeekday
LL_RTC_ALMA_Enable
LL_RTC_ALMA_EnableWeekday
LL_RTC_ALMA_GetDay
LL_RTC_ALMA_GetHour
LL_RTC_ALMA_GetMask
LL_RTC_ALMA_GetMinute
LL_RTC_ALMA_GetSecond
LL_RTC_ALMA_GetSubSecond
LL_RTC_ALMA_GetSubSecondMask
LL_RTC_ALMA_GetTime
LL_RTC_ALMA_GetTimeFormat
LL_RTC_ALMA_GetWeekDay
LL_RTC_ALMA_SetDay
LL_RTC_ALMA_SetHour
LL_RTC_ALMA_SetMask
LL_RTC_ALMA_SetMinute
LL_RTC_ALMA_SetSecond
LL_RTC_ALMA_SetSubSecond
LL_RTC_ALMA_SetSubSecondMask
LL_RTC_ALMA_SetTimeFormat
LL_RTC_ALMA_SetWeekDay
ALARMB
LL_RTC_ALMB_Disable
LL_RTC_ALMB_DisableWeekday
LL_RTC_ALMB_Enable
LL_RTC_ALMB_EnableWeekday
LL_RTC_ALMB_GetDay
LL_RTC_ALMB_GetHour
LL_RTC_ALMB_GetMask
LL_RTC_ALMB_GetMinute
LL_RTC_ALMB_GetSecond
LL_RTC_ALMB_GetSubSecond
LL_RTC_ALMB_GetSubSecondMask
LL_RTC_ALMB_GetTime
LL_RTC_ALMB_GetTimeFormat
LL_RTC_ALMB_GetWeekDay
LL_RTC_ALMB_SetDay
LL_RTC_ALMB_SetHour
LL_RTC_ALMB_SetMask
LL_RTC_ALMB_SetMinute
LL_RTC_ALMB_SetSecond
LL_RTC_ALMB_SetSubSecond
LL_RTC_ALMB_SetSubSecondMask
LL_RTC_ALMB_SetTimeFormat
LL_RTC_ALMB_SetWeekDay
Timestamp
LL_RTC_TS_DisableInternalEvent
LL_RTC_TS_DisableOnTamper
LL_RTC_TS_Enable
LL_RTC_TS_EnableInternalEvent
LL_RTC_TS_EnableOnTamper
LL_RTC_TS_GetActiveEdge
LL_RTC_TS_GetDate
LL_RTC_TS_GetDay
LL_RTC_TS_GetHour
LL_RTC_TS_GetMinute
LL_RTC_TS_GetMonth
LL_RTC_TS_GetSecond
LL_RTC_TS_GetSubSecond
LL_RTC_TS_GetTime
LL_RTC_TS_GetTimeFormat
LL_RTC_TS_GetWeekDay
LL_RTC_TS_SetActiveEdge
Tamper
LL_RTC_TAMPER_DisableActiveLevel
LL_RTC_TAMPER_DisableEraseBKP
LL_RTC_TAMPER_DisableMask
LL_RTC_TAMPER_DisablePullUp
LL_RTC_TAMPER_Enable
LL_RTC_TAMPER_EnableActiveLevel
LL_RTC_TAMPER_EnableEraseBKP
LL_RTC_TAMPER_EnableMask
LL_RTC_TAMPER_EnablePullUp
LL_RTC_TAMPER_GetFilterCount
LL_RTC_TAMPER_GetPrecharge
LL_RTC_TAMPER_GetSamplingFreq
LL_RTC_TAMPER_SetFilterCount
LL_RTC_TAMPER_SetPrecharge
LL_RTC_TAMPER_SetSamplingFreq
Internal Tamper
LL_RTC_TAMPER_ITAMP_Enable
Wakeup
LL_RTC_WAKEUP_Enable
LL_RTC_WAKEUP_GetAutoReload
LL_RTC_WAKEUP_GetClock
LL_RTC_WAKEUP_IsEnabled
LL_RTC_WAKEUP_SetAutoReload
LL_RTC_WAKEUP_SetClock
Backup_Registers
LL_RTC_BKP_SetRegister
Calibration
LL_RTC_CAL_GetOutputFreq
LL_RTC_CAL_GetPeriod
LL_RTC_CAL_IsPulseInserted
LL_RTC_CAL_SetMinus
LL_RTC_CAL_SetOutputFreq
LL_RTC_CAL_SetPeriod
LL_RTC_CAL_SetPulse
FLAG_Management
LL_RTC_ClearFlag_ALRB
LL_RTC_ClearFlag_ITAMP3
LL_RTC_ClearFlag_ITAMP4
LL_RTC_ClearFlag_ITAMP5
LL_RTC_ClearFlag_ITAMP6
LL_RTC_ClearFlag_ITS
LL_RTC_ClearFlag_RS
LL_RTC_ClearFlag_TAMP1
LL_RTC_ClearFlag_TAMP2
LL_RTC_ClearFlag_TAMP3
LL_RTC_ClearFlag_TS
LL_RTC_ClearFlag_TSOV
LL_RTC_ClearFlag_WUT
LL_RTC_IsActiveFlag_ALRA
LL_RTC_IsActiveFlag_ALRAM
LL_RTC_IsActiveFlag_ALRAW
LL_RTC_IsActiveFlag_ALRB
LL_RTC_IsActiveFlag_ALRBM
LL_RTC_IsActiveFlag_ALRBW
LL_RTC_IsActiveFlag_INIT
LL_RTC_IsActiveFlag_INITS
LL_RTC_IsActiveFlag_ITAMP3
LL_RTC_IsActiveFlag_ITAMP3M
LL_RTC_IsActiveFlag_ITAMP4
LL_RTC_IsActiveFlag_ITAMP4M
LL_RTC_IsActiveFlag_ITAMP5
LL_RTC_IsActiveFlag_ITAMP5M
LL_RTC_IsActiveFlag_ITAMP6
LL_RTC_IsActiveFlag_ITAMP6M
LL_RTC_IsActiveFlag_ITS
LL_RTC_IsActiveFlag_ITSM
LL_RTC_IsActiveFlag_RECALP
LL_RTC_IsActiveFlag_RS
LL_RTC_IsActiveFlag_SHP
LL_RTC_IsActiveFlag_TAMP1
LL_RTC_IsActiveFlag_TAMP1M
LL_RTC_IsActiveFlag_TAMP2
LL_RTC_IsActiveFlag_TAMP2M
LL_RTC_IsActiveFlag_TAMP3
LL_RTC_IsActiveFlag_TAMP3M
LL_RTC_IsActiveFlag_TS
LL_RTC_IsActiveFlag_TSM
LL_RTC_IsActiveFlag_TSOV
LL_RTC_IsActiveFlag_TSOVM
LL_RTC_IsActiveFlag_WUT
LL_RTC_IsActiveFlag_WUTM
LL_RTC_IsActiveFlag_WUTW
IT_Management
LL_RTC_DisableIT_ALRB
LL_RTC_DisableIT_ITAMP3
LL_RTC_DisableIT_ITAMP4
LL_RTC_DisableIT_ITAMP5
LL_RTC_DisableIT_ITAMP6
LL_RTC_DisableIT_TAMP1
LL_RTC_DisableIT_TAMP2
LL_RTC_DisableIT_TAMP3
LL_RTC_DisableIT_TS
LL_RTC_DisableIT_WUT
LL_RTC_EnableIT_ALRA
LL_RTC_EnableIT_ALRB
LL_RTC_EnableIT_ITAMP3
LL_RTC_EnableIT_ITAMP4
LL_RTC_EnableIT_ITAMP5
LL_RTC_EnableIT_ITAMP6
LL_RTC_EnableIT_TAMP1
LL_RTC_EnableIT_TAMP2
LL_RTC_EnableIT_TAMP3
LL_RTC_EnableIT_TS
LL_RTC_EnableIT_WUT
LL_RTC_IsEnabledIT_ALRA
LL_RTC_IsEnabledIT_ALRB
LL_RTC_IsEnabledIT_ITAMP3
LL_RTC_IsEnabledIT_ITAMP4
LL_RTC_IsEnabledIT_ITAMP5
LL_RTC_IsEnabledIT_ITAMP6
LL_RTC_IsEnabledIT_TAMP1
LL_RTC_IsEnabledIT_TAMP2
LL_RTC_IsEnabledIT_TAMP3
LL_RTC_IsEnabledIT_TS
LL_RTC_IsEnabledIT_WUT
Initialization and de-initialization functions
LL_RTC_ALMA_StructInit
LL_RTC_ALMB_Init
LL_RTC_ALMB_StructInit
LL_RTC_DATE_Init
LL_RTC_DATE_StructInit
LL_RTC_DeInit
LL_RTC_EnterInitMode
LL_RTC_ExitInitMode
LL_RTC_Init
LL_RTC_StructInit
LL_RTC_TIME_Init
LL_RTC_TIME_StructInit
LL_RTC_WaitForSynchro
RTC Exported Functions
LL_RTC_DisableInitMode
LL_RTC_DisableOutput2
LL_RTC_DisableRefClock
LL_RTC_DisableShadowRegBypass
LL_RTC_DisableTamperOutput
LL_RTC_DisableWriteProtection
LL_RTC_EnableAlarmPullUp
LL_RTC_EnableInitMode
LL_RTC_EnableOutput2
LL_RTC_EnableRefClock
LL_RTC_EnableShadowRegBypass
LL_RTC_EnableTamperOutput
LL_RTC_EnableWriteProtection
LL_RTC_GetAlarmOutEvent
LL_RTC_GetAlarmOutputType
LL_RTC_GetAsynchPrescaler
LL_RTC_GetHourFormat
LL_RTC_GetOutputPolarity
LL_RTC_GetSynchPrescaler
LL_RTC_IsAlarmPullUpEnabled
LL_RTC_IsOutput2Enabled
LL_RTC_IsShadowRegBypassEnabled
LL_RTC_IsTamperOutputEnabled
LL_RTC_SetAlarmOutEvent
LL_RTC_SetAlarmOutputType
LL_RTC_SetAsynchPrescaler
LL_RTC_SetHourFormat
LL_RTC_SetOutputPolarity
LL_RTC_SetSynchPrescaler
Time
LL_RTC_TIME_DecHour
LL_RTC_TIME_DisableDayLightStore
LL_RTC_TIME_EnableDayLightStore
LL_RTC_TIME_Get
LL_RTC_TIME_GetFormat
LL_RTC_TIME_GetHour
LL_RTC_TIME_GetMinute
LL_RTC_TIME_GetSecond
LL_RTC_TIME_GetSubSecond
LL_RTC_TIME_IncHour
LL_RTC_TIME_IsDayLightStoreEnabled
LL_RTC_TIME_SetFormat
LL_RTC_TIME_SetHour
LL_RTC_TIME_SetMinute
LL_RTC_TIME_SetSecond
LL_RTC_TIME_Synchronize
Date
LL_RTC_DATE_Get
LL_RTC_DATE_GetDay
LL_RTC_DATE_GetMonth
LL_RTC_DATE_GetWeekDay
LL_RTC_DATE_GetYear
LL_RTC_DATE_SetDay
LL_RTC_DATE_SetMonth
LL_RTC_DATE_SetWeekDay
LL_RTC_DATE_SetYear
ALARMA
LL_RTC_ALMA_Disable
LL_RTC_ALMA_DisableWeekday
LL_RTC_ALMA_Enable
LL_RTC_ALMA_EnableWeekday
LL_RTC_ALMA_GetDay
LL_RTC_ALMA_GetHour
LL_RTC_ALMA_GetMask
LL_RTC_ALMA_GetMinute
LL_RTC_ALMA_GetSecond
LL_RTC_ALMA_GetSubSecond
LL_RTC_ALMA_GetSubSecondMask
LL_RTC_ALMA_GetTime
LL_RTC_ALMA_GetTimeFormat
LL_RTC_ALMA_GetWeekDay
LL_RTC_ALMA_SetDay
LL_RTC_ALMA_SetHour
LL_RTC_ALMA_SetMask
LL_RTC_ALMA_SetMinute
LL_RTC_ALMA_SetSecond
LL_RTC_ALMA_SetSubSecond
LL_RTC_ALMA_SetSubSecondMask
LL_RTC_ALMA_SetTimeFormat
LL_RTC_ALMA_SetWeekDay
ALARMB
LL_RTC_ALMB_Disable
LL_RTC_ALMB_DisableWeekday
LL_RTC_ALMB_Enable
LL_RTC_ALMB_EnableWeekday
LL_RTC_ALMB_GetDay
LL_RTC_ALMB_GetHour
LL_RTC_ALMB_GetMask
LL_RTC_ALMB_GetMinute
LL_RTC_ALMB_GetSecond
LL_RTC_ALMB_GetSubSecond
LL_RTC_ALMB_GetSubSecondMask
LL_RTC_ALMB_GetTime
LL_RTC_ALMB_GetTimeFormat
LL_RTC_ALMB_GetWeekDay
LL_RTC_ALMB_SetDay
LL_RTC_ALMB_SetHour
LL_RTC_ALMB_SetMask
LL_RTC_ALMB_SetMinute
LL_RTC_ALMB_SetSecond
LL_RTC_ALMB_SetSubSecond
LL_RTC_ALMB_SetSubSecondMask
LL_RTC_ALMB_SetTimeFormat
LL_RTC_ALMB_SetWeekDay
Timestamp
LL_RTC_TS_DisableInternalEvent
LL_RTC_TS_DisableOnTamper
LL_RTC_TS_Enable
LL_RTC_TS_EnableInternalEvent
LL_RTC_TS_EnableOnTamper
LL_RTC_TS_GetActiveEdge
LL_RTC_TS_GetDate
LL_RTC_TS_GetDay
LL_RTC_TS_GetHour
LL_RTC_TS_GetMinute
LL_RTC_TS_GetMonth
LL_RTC_TS_GetSecond
LL_RTC_TS_GetSubSecond
LL_RTC_TS_GetTime
LL_RTC_TS_GetTimeFormat
LL_RTC_TS_GetWeekDay
LL_RTC_TS_SetActiveEdge
Tamper
LL_RTC_TAMPER_DisableActiveLevel
LL_RTC_TAMPER_DisableEraseBKP
LL_RTC_TAMPER_DisableMask
LL_RTC_TAMPER_DisablePullUp
LL_RTC_TAMPER_Enable
LL_RTC_TAMPER_EnableActiveLevel
LL_RTC_TAMPER_EnableEraseBKP
LL_RTC_TAMPER_EnableMask
LL_RTC_TAMPER_EnablePullUp
LL_RTC_TAMPER_GetFilterCount
LL_RTC_TAMPER_GetPrecharge
LL_RTC_TAMPER_GetSamplingFreq
LL_RTC_TAMPER_SetFilterCount
LL_RTC_TAMPER_SetPrecharge
LL_RTC_TAMPER_SetSamplingFreq
Internal Tamper
LL_RTC_TAMPER_ITAMP_Enable
Wakeup
LL_RTC_WAKEUP_Enable
LL_RTC_WAKEUP_GetAutoReload
LL_RTC_WAKEUP_GetClock
LL_RTC_WAKEUP_IsEnabled
LL_RTC_WAKEUP_SetAutoReload
LL_RTC_WAKEUP_SetClock
Backup_Registers
LL_RTC_BKP_SetRegister
Calibration
LL_RTC_CAL_GetOutputFreq
LL_RTC_CAL_GetPeriod
LL_RTC_CAL_IsPulseInserted
LL_RTC_CAL_SetMinus
LL_RTC_CAL_SetOutputFreq
LL_RTC_CAL_SetPeriod
LL_RTC_CAL_SetPulse
FLAG_Management
LL_RTC_ClearFlag_ALRB
LL_RTC_ClearFlag_ITAMP3
LL_RTC_ClearFlag_ITAMP4
LL_RTC_ClearFlag_ITAMP5
LL_RTC_ClearFlag_ITAMP6
LL_RTC_ClearFlag_ITS
LL_RTC_ClearFlag_RS
LL_RTC_ClearFlag_TAMP1
LL_RTC_ClearFlag_TAMP2
LL_RTC_ClearFlag_TAMP3
LL_RTC_ClearFlag_TS
LL_RTC_ClearFlag_TSOV
LL_RTC_ClearFlag_WUT
LL_RTC_IsActiveFlag_ALRA
LL_RTC_IsActiveFlag_ALRAM
LL_RTC_IsActiveFlag_ALRAW
LL_RTC_IsActiveFlag_ALRB
LL_RTC_IsActiveFlag_ALRBM
LL_RTC_IsActiveFlag_ALRBW
LL_RTC_IsActiveFlag_INIT
LL_RTC_IsActiveFlag_INITS
LL_RTC_IsActiveFlag_ITAMP3
LL_RTC_IsActiveFlag_ITAMP3M
LL_RTC_IsActiveFlag_ITAMP4
LL_RTC_IsActiveFlag_ITAMP4M
LL_RTC_IsActiveFlag_ITAMP5
LL_RTC_IsActiveFlag_ITAMP5M
LL_RTC_IsActiveFlag_ITAMP6
LL_RTC_IsActiveFlag_ITAMP6M
LL_RTC_IsActiveFlag_ITS
LL_RTC_IsActiveFlag_ITSM
LL_RTC_IsActiveFlag_RECALP
LL_RTC_IsActiveFlag_RS
LL_RTC_IsActiveFlag_SHP
LL_RTC_IsActiveFlag_TAMP1
LL_RTC_IsActiveFlag_TAMP1M
LL_RTC_IsActiveFlag_TAMP2
LL_RTC_IsActiveFlag_TAMP2M
LL_RTC_IsActiveFlag_TAMP3
LL_RTC_IsActiveFlag_TAMP3M
LL_RTC_IsActiveFlag_TS
LL_RTC_IsActiveFlag_TSM
LL_RTC_IsActiveFlag_TSOV
LL_RTC_IsActiveFlag_TSOVM
LL_RTC_IsActiveFlag_WUT
LL_RTC_IsActiveFlag_WUTM
LL_RTC_IsActiveFlag_WUTW
IT_Management
LL_RTC_DisableIT_ALRB
LL_RTC_DisableIT_ITAMP3
LL_RTC_DisableIT_ITAMP4
LL_RTC_DisableIT_ITAMP5
LL_RTC_DisableIT_ITAMP6
LL_RTC_DisableIT_TAMP1
LL_RTC_DisableIT_TAMP2
LL_RTC_DisableIT_TAMP3
LL_RTC_DisableIT_TS
LL_RTC_DisableIT_WUT
LL_RTC_EnableIT_ALRA
LL_RTC_EnableIT_ALRB
LL_RTC_EnableIT_ITAMP3
LL_RTC_EnableIT_ITAMP4
LL_RTC_EnableIT_ITAMP5
LL_RTC_EnableIT_ITAMP6
LL_RTC_EnableIT_TAMP1
LL_RTC_EnableIT_TAMP2
LL_RTC_EnableIT_TAMP3
LL_RTC_EnableIT_TS
LL_RTC_EnableIT_WUT
LL_RTC_IsEnabledIT_ALRA
LL_RTC_IsEnabledIT_ALRB
LL_RTC_IsEnabledIT_ITAMP3
LL_RTC_IsEnabledIT_ITAMP4
LL_RTC_IsEnabledIT_ITAMP5
LL_RTC_IsEnabledIT_ITAMP6
LL_RTC_IsEnabledIT_TAMP1
LL_RTC_IsEnabledIT_TAMP2
LL_RTC_IsEnabledIT_TAMP3
LL_RTC_IsEnabledIT_TS
LL_RTC_IsEnabledIT_WUT
Initialization and de-initialization functions
LL_RTC_ALMA_StructInit
LL_RTC_ALMB_Init
LL_RTC_ALMB_StructInit
LL_RTC_DATE_Init
LL_RTC_DATE_StructInit
LL_RTC_DeInit
LL_RTC_EnterInitMode
LL_RTC_ExitInitMode
LL_RTC_Init
LL_RTC_StructInit
LL_RTC_TIME_Init
LL_RTC_TIME_StructInit
LL_RTC_WaitForSynchro
SPI
SPI Private Macros
IS_LL_SPI_BITORDER
IS_LL_SPI_CRC_POLYNOMIAL
IS_LL_SPI_CRCCALCULATION
IS_LL_SPI_DATAWIDTH
IS_LL_SPI_MODE
IS_LL_SPI_NSS
IS_LL_SPI_PHASE
IS_LL_SPI_POLARITY
IS_LL_SPI_TRANSFER_DIRECTION
SPI Exported Init structure
SPI Exported Constants
LL_SPI_SR_CRCERR
LL_SPI_SR_FRE
LL_SPI_SR_MODF
LL_SPI_SR_OVR
LL_SPI_SR_RXNE
LL_SPI_SR_TXE
IT Defines
LL_I2S_CR2_RXNEIE
LL_I2S_CR2_TXEIE
LL_SPI_CR2_ERRIE
LL_SPI_CR2_RXNEIE
LL_SPI_CR2_TXEIE
Operation Mode
LL_SPI_MODE_SLAVE
Serial Protocol
LL_SPI_PROTOCOL_TI
Clock Phase
LL_SPI_PHASE_2EDGE
Clock Polarity
LL_SPI_POLARITY_LOW
Baud Rate Prescaler
LL_SPI_BAUDRATEPRESCALER_DIV16
LL_SPI_BAUDRATEPRESCALER_DIV2
LL_SPI_BAUDRATEPRESCALER_DIV256
LL_SPI_BAUDRATEPRESCALER_DIV32
LL_SPI_BAUDRATEPRESCALER_DIV4
LL_SPI_BAUDRATEPRESCALER_DIV64
LL_SPI_BAUDRATEPRESCALER_DIV8
Transmission Bit Order
LL_SPI_MSB_FIRST
Transfer Mode
LL_SPI_HALF_DUPLEX_RX
LL_SPI_HALF_DUPLEX_TX
LL_SPI_SIMPLEX_RX
Slave Select Pin Mode
LL_SPI_NSS_HARD_OUTPUT
LL_SPI_NSS_SOFT
Datawidth
LL_SPI_DATAWIDTH_11BIT
LL_SPI_DATAWIDTH_12BIT
LL_SPI_DATAWIDTH_13BIT
LL_SPI_DATAWIDTH_14BIT
LL_SPI_DATAWIDTH_15BIT
LL_SPI_DATAWIDTH_16BIT
LL_SPI_DATAWIDTH_4BIT
LL_SPI_DATAWIDTH_5BIT
LL_SPI_DATAWIDTH_6BIT
LL_SPI_DATAWIDTH_7BIT
LL_SPI_DATAWIDTH_8BIT
LL_SPI_DATAWIDTH_9BIT
CRC Calculation
LL_SPI_CRCCALCULATION_ENABLE
CRC Length
LL_SPI_CRC_8BIT
RX FIFO Threshold
LL_SPI_RX_FIFO_TH_QUARTER
RX FIFO Level
LL_SPI_RX_FIFO_FULL
LL_SPI_RX_FIFO_HALF_FULL
LL_SPI_RX_FIFO_QUARTER_FULL
TX FIFO Level
LL_SPI_TX_FIFO_FULL
LL_SPI_TX_FIFO_HALF_FULL
LL_SPI_TX_FIFO_QUARTER_FULL
DMA Parity
LL_SPI_DMA_PARITY_ODD
SPI Exported Macros
LL_SPI_WriteReg
SPI Exported Functions
LL_SPI_Enable
LL_SPI_GetBaudRatePrescaler
LL_SPI_GetClockPhase
LL_SPI_GetClockPolarity
LL_SPI_GetDataWidth
LL_SPI_GetMode
LL_SPI_GetRxFIFOThreshold
LL_SPI_GetStandard
LL_SPI_GetTransferBitOrder
LL_SPI_GetTransferDirection
LL_SPI_IsEnabled
LL_SPI_SetBaudRatePrescaler
LL_SPI_SetClockPhase
LL_SPI_SetClockPolarity
LL_SPI_SetDataWidth
LL_SPI_SetMode
LL_SPI_SetRxFIFOThreshold
LL_SPI_SetStandard
LL_SPI_SetTransferBitOrder
LL_SPI_SetTransferDirection
CRC Management
LL_SPI_EnableCRC
LL_SPI_GetCRCPolynomial
LL_SPI_GetCRCWidth
LL_SPI_GetRxCRC
LL_SPI_GetTxCRC
LL_SPI_IsEnabledCRC
LL_SPI_SetCRCNext
LL_SPI_SetCRCPolynomial
LL_SPI_SetCRCWidth
Slave Select Pin Management
LL_SPI_EnableNSSPulseMgt
LL_SPI_GetNSSMode
LL_SPI_IsEnabledNSSPulse
LL_SPI_SetNSSMode
FLAG Management
LL_SPI_ClearFlag_FRE
LL_SPI_ClearFlag_MODF
LL_SPI_ClearFlag_OVR
LL_SPI_GetRxFIFOLevel
LL_SPI_GetTxFIFOLevel
LL_SPI_IsActiveFlag_BSY
LL_SPI_IsActiveFlag_CRCERR
LL_SPI_IsActiveFlag_FRE
LL_SPI_IsActiveFlag_MODF
LL_SPI_IsActiveFlag_OVR
LL_SPI_IsActiveFlag_RXNE
LL_SPI_IsActiveFlag_TXE
Interrupt Management
LL_SPI_DisableIT_RXNE
LL_SPI_DisableIT_TXE
LL_SPI_EnableIT_ERR
LL_SPI_EnableIT_RXNE
LL_SPI_EnableIT_TXE
LL_SPI_IsEnabledIT_ERR
LL_SPI_IsEnabledIT_RXNE
LL_SPI_IsEnabledIT_TXE
DMA Management
LL_SPI_DisableDMAReq_TX
LL_SPI_DMA_GetRegAddr
LL_SPI_EnableDMAReq_RX
LL_SPI_EnableDMAReq_TX
LL_SPI_GetDMAParity_RX
LL_SPI_GetDMAParity_TX
LL_SPI_IsEnabledDMAReq_RX
LL_SPI_IsEnabledDMAReq_TX
LL_SPI_SetDMAParity_RX
LL_SPI_SetDMAParity_TX
DATA Management
LL_SPI_ReceiveData8
LL_SPI_TransmitData16
LL_SPI_TransmitData8
Initialization and de-initialization functions
LL_SPI_Init
LL_SPI_StructInit
I2S
I2S_I2SPR_CLEAR_MASK
I2S Private Macros
IS_LL_I2S_CPOL
IS_LL_I2S_DATAFORMAT
IS_LL_I2S_MCLK_OUTPUT
IS_LL_I2S_MODE
IS_LL_I2S_PRESCALER_LINEAR
IS_LL_I2S_PRESCALER_PARITY
IS_LL_I2S_STANDARD
I2S Exported Init structure
I2S Exported Constants
LL_I2S_SR_FRE
LL_I2S_SR_OVR
LL_I2S_SR_RXNE
LL_I2S_SR_TXE
LL_I2S_SR_UDR
IT Defines
LL_I2S_CR2_RXNEIE
LL_I2S_CR2_TXEIE
LL_SPI_CR2_ERRIE
LL_SPI_CR2_RXNEIE
LL_SPI_CR2_TXEIE
Data format
LL_I2S_DATAFORMAT_16B_EXTENDED
LL_I2S_DATAFORMAT_24B
LL_I2S_DATAFORMAT_32B
Clock Polarity
LL_I2S_POLARITY_LOW
I2s Standard
LL_I2S_STANDARD_MSB
LL_I2S_STANDARD_PCM_LONG
LL_I2S_STANDARD_PCM_SHORT
LL_I2S_STANDARD_PHILIPS
Operation Mode
LL_I2S_MODE_MASTER_TX
LL_I2S_MODE_SLAVE_RX
LL_I2S_MODE_SLAVE_TX
Prescaler Factor
LL_I2S_PRESCALER_PARITY_ODD
MCLK Output
LL_I2S_MCLK_OUTPUT_ENABLE
Audio Frequency
LL_I2S_AUDIOFREQ_16K
LL_I2S_AUDIOFREQ_192K
LL_I2S_AUDIOFREQ_22K
LL_I2S_AUDIOFREQ_32K
LL_I2S_AUDIOFREQ_44K
LL_I2S_AUDIOFREQ_48K
LL_I2S_AUDIOFREQ_8K
LL_I2S_AUDIOFREQ_96K
LL_I2S_AUDIOFREQ_DEFAULT
I2S Exported Macros
LL_I2S_WriteReg
I2S Exported Functions
LL_I2S_DisableAsyncStart
LL_I2S_DisableMasterClock
LL_I2S_Enable
LL_I2S_EnableAsyncStart
LL_I2S_EnableMasterClock
LL_I2S_GetClockPolarity
LL_I2S_GetDataFormat
LL_I2S_GetPrescalerLinear
LL_I2S_GetPrescalerParity
LL_I2S_GetStandard
LL_I2S_GetTransferMode
LL_I2S_IsEnabled
LL_I2S_IsEnabledAsyncStart
LL_I2S_IsEnabledMasterClock
LL_I2S_SetClockPolarity
LL_I2S_SetDataFormat
LL_I2S_SetPrescalerLinear
LL_I2S_SetPrescalerParity
LL_I2S_SetStandard
LL_I2S_SetTransferMode
FLAG Management
LL_I2S_ClearFlag_OVR
LL_I2S_ClearFlag_UDR
LL_I2S_IsActiveFlag_BSY
LL_I2S_IsActiveFlag_CHSIDE
LL_I2S_IsActiveFlag_FRE
LL_I2S_IsActiveFlag_OVR
LL_I2S_IsActiveFlag_RXNE
LL_I2S_IsActiveFlag_TXE
LL_I2S_IsActiveFlag_UDR
Interrupt Management
LL_I2S_DisableIT_RXNE
LL_I2S_DisableIT_TXE
LL_I2S_EnableIT_ERR
LL_I2S_EnableIT_RXNE
LL_I2S_EnableIT_TXE
LL_I2S_IsEnabledIT_ERR
LL_I2S_IsEnabledIT_RXNE
LL_I2S_IsEnabledIT_TXE
DMA Management
LL_I2S_DisableDMAReq_TX
LL_I2S_EnableDMAReq_RX
LL_I2S_EnableDMAReq_TX
LL_I2S_IsEnabledDMAReq_RX
LL_I2S_IsEnabledDMAReq_TX
DATA Management
LL_I2S_TransmitData16
Initialization and de-initialization functions
LL_I2S_DeInit
LL_I2S_Init
LL_I2S_StructInit
SYSTEM
FLASH_PDKEY1
FLASH_PDKEY2
SYSTEM Exported Constants
LL_SYSCFG_REMAP_FMC
LL_SYSCFG_REMAP_QUADSPI
LL_SYSCFG_REMAP_SRAM
LL_SYSCFG_REMAP_SYSTEMFLASH
SYSCFG BANK MODE
LL_SYSCFG_BANKMODE_BANK2
SYSCFG I2C FASTMODEPLUS
LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
LL_SYSCFG_I2C_FASTMODEPLUS_PB6
LL_SYSCFG_I2C_FASTMODEPLUS_PB7
LL_SYSCFG_I2C_FASTMODEPLUS_PB8
LL_SYSCFG_I2C_FASTMODEPLUS_PB9
SYSCFG EXTI PORT
LL_SYSCFG_EXTI_PORTB
LL_SYSCFG_EXTI_PORTC
LL_SYSCFG_EXTI_PORTD
LL_SYSCFG_EXTI_PORTE
LL_SYSCFG_EXTI_PORTF
LL_SYSCFG_EXTI_PORTG
SYSCFG EXTI LINE
LL_SYSCFG_EXTI_LINE1
LL_SYSCFG_EXTI_LINE10
LL_SYSCFG_EXTI_LINE11
LL_SYSCFG_EXTI_LINE12
LL_SYSCFG_EXTI_LINE13
LL_SYSCFG_EXTI_LINE14
LL_SYSCFG_EXTI_LINE15
LL_SYSCFG_EXTI_LINE2
LL_SYSCFG_EXTI_LINE3
LL_SYSCFG_EXTI_LINE4
LL_SYSCFG_EXTI_LINE5
LL_SYSCFG_EXTI_LINE6
LL_SYSCFG_EXTI_LINE7
LL_SYSCFG_EXTI_LINE8
LL_SYSCFG_EXTI_LINE9
SYSCFG TIMER BREAK
LL_SYSCFG_TIMBREAK_LOCKUP
LL_SYSCFG_TIMBREAK_PVD
LL_SYSCFG_TIMBREAK_SRAM_PARITY
SYSCFG CCMSRAM WRP
LL_SYSCFG_CCMSRAMWRP_PAGE1
LL_SYSCFG_CCMSRAMWRP_PAGE10
LL_SYSCFG_CCMSRAMWRP_PAGE11
LL_SYSCFG_CCMSRAMWRP_PAGE12
LL_SYSCFG_CCMSRAMWRP_PAGE13
LL_SYSCFG_CCMSRAMWRP_PAGE14
LL_SYSCFG_CCMSRAMWRP_PAGE15
LL_SYSCFG_CCMSRAMWRP_PAGE16
LL_SYSCFG_CCMSRAMWRP_PAGE17
LL_SYSCFG_CCMSRAMWRP_PAGE18
LL_SYSCFG_CCMSRAMWRP_PAGE19
LL_SYSCFG_CCMSRAMWRP_PAGE2
LL_SYSCFG_CCMSRAMWRP_PAGE20
LL_SYSCFG_CCMSRAMWRP_PAGE21
LL_SYSCFG_CCMSRAMWRP_PAGE22
LL_SYSCFG_CCMSRAMWRP_PAGE23
LL_SYSCFG_CCMSRAMWRP_PAGE24
LL_SYSCFG_CCMSRAMWRP_PAGE25
LL_SYSCFG_CCMSRAMWRP_PAGE26
LL_SYSCFG_CCMSRAMWRP_PAGE27
LL_SYSCFG_CCMSRAMWRP_PAGE28
LL_SYSCFG_CCMSRAMWRP_PAGE29
LL_SYSCFG_CCMSRAMWRP_PAGE3
LL_SYSCFG_CCMSRAMWRP_PAGE30
LL_SYSCFG_CCMSRAMWRP_PAGE31
LL_SYSCFG_CCMSRAMWRP_PAGE4
LL_SYSCFG_CCMSRAMWRP_PAGE5
LL_SYSCFG_CCMSRAMWRP_PAGE6
LL_SYSCFG_CCMSRAMWRP_PAGE7
LL_SYSCFG_CCMSRAMWRP_PAGE8
LL_SYSCFG_CCMSRAMWRP_PAGE9
DBGMCU TRACE Pin Assignment
LL_DBGMCU_TRACE_NONE
LL_DBGMCU_TRACE_SYNCH_SIZE1
LL_DBGMCU_TRACE_SYNCH_SIZE2
LL_DBGMCU_TRACE_SYNCH_SIZE4
DBGMCU APB1 GRP1 STOP IP
LL_DBGMCU_APB1_GRP1_I2C2_STOP
LL_DBGMCU_APB1_GRP1_I2C3_STOP
LL_DBGMCU_APB1_GRP1_IWDG_STOP
LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
LL_DBGMCU_APB1_GRP1_RTC_STOP
LL_DBGMCU_APB1_GRP1_TIM2_STOP
LL_DBGMCU_APB1_GRP1_TIM3_STOP
LL_DBGMCU_APB1_GRP1_TIM4_STOP
LL_DBGMCU_APB1_GRP1_TIM5_STOP
LL_DBGMCU_APB1_GRP1_TIM6_STOP
LL_DBGMCU_APB1_GRP1_TIM7_STOP
LL_DBGMCU_APB1_GRP1_WWDG_STOP
DBGMCU APB1 GRP2 STOP IP
DBGMCU APB2 GRP1 STOP IP
LL_DBGMCU_APB2_GRP1_TIM15_STOP
LL_DBGMCU_APB2_GRP1_TIM16_STOP
LL_DBGMCU_APB2_GRP1_TIM17_STOP
LL_DBGMCU_APB2_GRP1_TIM1_STOP
LL_DBGMCU_APB2_GRP1_TIM20_STOP
LL_DBGMCU_APB2_GRP1_TIM8_STOP
VREFBUF VOLTAGE
LL_VREFBUF_VOLTAGE_SCALE1
LL_VREFBUF_VOLTAGE_SCALE2
FLASH LATENCY
LL_FLASH_LATENCY_1
LL_FLASH_LATENCY_10
LL_FLASH_LATENCY_11
LL_FLASH_LATENCY_12
LL_FLASH_LATENCY_13
LL_FLASH_LATENCY_14
LL_FLASH_LATENCY_15
LL_FLASH_LATENCY_2
LL_FLASH_LATENCY_3
LL_FLASH_LATENCY_4
LL_FLASH_LATENCY_5
LL_FLASH_LATENCY_6
LL_FLASH_LATENCY_7
LL_FLASH_LATENCY_8
LL_FLASH_LATENCY_9
SYSTEM Exported Functions
LL_SYSCFG_DisableAnalogBooster
LL_SYSCFG_DisableFastModePlus
LL_SYSCFG_DisableIT_FPU_DZC
LL_SYSCFG_DisableIT_FPU_IDC
LL_SYSCFG_DisableIT_FPU_IOC
LL_SYSCFG_DisableIT_FPU_IXC
LL_SYSCFG_DisableIT_FPU_OFC
LL_SYSCFG_DisableIT_FPU_UFC
LL_SYSCFG_EnableAnalogBooster
LL_SYSCFG_EnableCCMSRAMErase
LL_SYSCFG_EnableCCMSRAMPageWRP
LL_SYSCFG_EnableFastModePlus
LL_SYSCFG_EnableIT_FPU_DZC
LL_SYSCFG_EnableIT_FPU_IDC
LL_SYSCFG_EnableIT_FPU_IOC
LL_SYSCFG_EnableIT_FPU_IXC
LL_SYSCFG_EnableIT_FPU_OFC
LL_SYSCFG_EnableIT_FPU_UFC
LL_SYSCFG_GetEXTISource
LL_SYSCFG_GetFlashBankMode
LL_SYSCFG_GetRemapMemory
LL_SYSCFG_GetTIMBreakInputs
LL_SYSCFG_IsActiveFlag_SP
LL_SYSCFG_IsCCMSRAMEraseOngoing
LL_SYSCFG_IsEnabledIT_FPU_DZC
LL_SYSCFG_IsEnabledIT_FPU_IDC
LL_SYSCFG_IsEnabledIT_FPU_IOC
LL_SYSCFG_IsEnabledIT_FPU_IXC
LL_SYSCFG_IsEnabledIT_FPU_OFC
LL_SYSCFG_IsEnabledIT_FPU_UFC
LL_SYSCFG_LockCCMSRAMWRP
LL_SYSCFG_SetEXTISource
LL_SYSCFG_SetFlashBankMode
LL_SYSCFG_SetRemapMemory
LL_SYSCFG_SetTIMBreakInputs
LL_SYSCFG_UnlockCCMSRAMWRP
DBGMCU
LL_DBGMCU_APB1_GRP1_UnFreezePeriph
LL_DBGMCU_APB1_GRP2_FreezePeriph
LL_DBGMCU_APB1_GRP2_UnFreezePeriph
LL_DBGMCU_APB2_GRP1_FreezePeriph
LL_DBGMCU_APB2_GRP1_UnFreezePeriph
LL_DBGMCU_DisableDBGSleepMode
LL_DBGMCU_DisableDBGStandbyMode
LL_DBGMCU_DisableDBGStopMode
LL_DBGMCU_EnableDBGSleepMode
LL_DBGMCU_EnableDBGStandbyMode
LL_DBGMCU_EnableDBGStopMode
LL_DBGMCU_GetDeviceID
LL_DBGMCU_GetRevisionID
LL_DBGMCU_GetTracePinAssignment
LL_DBGMCU_SetTracePinAssignment
VREFBUF
LL_VREFBUF_DisableHIZ
LL_VREFBUF_Enable
LL_VREFBUF_EnableHIZ
LL_VREFBUF_GetTrimming
LL_VREFBUF_GetVoltageScaling
LL_VREFBUF_IsVREFReady
LL_VREFBUF_SetTrimming
LL_VREFBUF_SetVoltageScaling
FLASH
LL_FLASH_DisableDataCacheReset
LL_FLASH_DisableInstCache
LL_FLASH_DisableInstCacheReset
LL_FLASH_DisablePrefetch
LL_FLASH_DisableRunPowerDown
LL_FLASH_DisableSleepPowerDown
LL_FLASH_EnableDataCache
LL_FLASH_EnableDataCacheReset
LL_FLASH_EnableInstCache
LL_FLASH_EnableInstCacheReset
LL_FLASH_EnablePrefetch
LL_FLASH_EnableRunPowerDown
LL_FLASH_EnableSleepPowerDown
LL_FLASH_GetLatency
LL_FLASH_IsPrefetchEnabled
LL_FLASH_SetLatency
TIM
IC2Config
IC3Config
IC4Config
OC1Config
OC2Config
OC3Config
OC4Config
OC5Config
OC6Config
TIM Private Variables
SHIFT_TAB_CCxP
SHIFT_TAB_ICxx
SHIFT_TAB_OCxx
SHIFT_TAB_OISx
TIM Private Constants
DT_DELAY_2
DT_DELAY_3
DT_DELAY_4
DT_RANGE_1
DT_RANGE_2
DT_RANGE_3
DT_RANGE_4
OCREF_CLEAR_SELECT_Msk
OCREF_CLEAR_SELECT_Pos
TIM_POSITION_BRK_SOURCE
TIMx_AF1_BKINP
TIMx_AF1_ETRSEL
TIM Private Macros
IS_LL_TIM_AUTOMATIC_OUTPUT_STATE
IS_LL_TIM_BREAK2_AFMODE
IS_LL_TIM_BREAK2_FILTER
IS_LL_TIM_BREAK2_POLARITY
IS_LL_TIM_BREAK2_STATE
IS_LL_TIM_BREAK_AFMODE
IS_LL_TIM_BREAK_FILTER
IS_LL_TIM_BREAK_POLARITY
IS_LL_TIM_BREAK_STATE
IS_LL_TIM_CLOCKDIVISION
IS_LL_TIM_COUNTERMODE
IS_LL_TIM_ENCODERMODE
IS_LL_TIM_IC_FILTER
IS_LL_TIM_IC_POLARITY
IS_LL_TIM_IC_POLARITY_ENCODER
IS_LL_TIM_ICPSC
IS_LL_TIM_LOCK_LEVEL
IS_LL_TIM_OCIDLESTATE
IS_LL_TIM_OCMODE
IS_LL_TIM_OCPOLARITY
IS_LL_TIM_OCSTATE
IS_LL_TIM_OSSI_STATE
IS_LL_TIM_OSSR_STATE
TIM_CALC_DTS
TIM_GET_CHANNEL_INDEX
TIM Exported Init structure
LL_TIM_OC_InitTypeDef
LL_TIM_IC_InitTypeDef
LL_TIM_ENCODER_InitTypeDef
LL_TIM_HALLSENSOR_InitTypeDef
LL_TIM_BDTR_InitTypeDef
TIM Exported Constants
LL_TIM_SR_BIF
LL_TIM_SR_CC1IF
LL_TIM_SR_CC1OF
LL_TIM_SR_CC2IF
LL_TIM_SR_CC2OF
LL_TIM_SR_CC3IF
LL_TIM_SR_CC3OF
LL_TIM_SR_CC4IF
LL_TIM_SR_CC4OF
LL_TIM_SR_CC5IF
LL_TIM_SR_CC6IF
LL_TIM_SR_COMIF
LL_TIM_SR_DIRF
LL_TIM_SR_IDXF
LL_TIM_SR_IERRF
LL_TIM_SR_SBIF
LL_TIM_SR_TERRF
LL_TIM_SR_TIF
LL_TIM_SR_UIF
Break Enable
LL_TIM_BREAK_ENABLE
Break2 Enable
LL_TIM_BREAK2_ENABLE
Automatic output enable
LL_TIM_AUTOMATICOUTPUT_ENABLE
IT Defines
LL_TIM_DIER_CC1IE
LL_TIM_DIER_CC2IE
LL_TIM_DIER_CC3IE
LL_TIM_DIER_CC4IE
LL_TIM_DIER_COMIE
LL_TIM_DIER_DIRIE
LL_TIM_DIER_IDXIE
LL_TIM_DIER_IERRIE
LL_TIM_DIER_TERRIE
LL_TIM_DIER_TIE
LL_TIM_DIER_UIE
Update Source
LL_TIM_UPDATESOURCE_REGULAR
One Pulse Mode
LL_TIM_ONEPULSEMODE_SINGLE
Counter Mode
LL_TIM_COUNTERMODE_CENTER_UP
LL_TIM_COUNTERMODE_CENTER_UP_DOWN
LL_TIM_COUNTERMODE_DOWN
LL_TIM_COUNTERMODE_UP
Clock Division
LL_TIM_CLOCKDIVISION_DIV2
LL_TIM_CLOCKDIVISION_DIV4
Counter Direction
LL_TIM_COUNTERDIRECTION_UP
Capture Compare Update Source
LL_TIM_CCUPDATESOURCE_COMG_ONLY
Capture Compare DMA Request
LL_TIM_CCDMAREQUEST_UPDATE
Lock Level
LL_TIM_LOCKLEVEL_2
LL_TIM_LOCKLEVEL_3
LL_TIM_LOCKLEVEL_OFF
Channel
LL_TIM_CHANNEL_CH1N
LL_TIM_CHANNEL_CH2
LL_TIM_CHANNEL_CH2N
LL_TIM_CHANNEL_CH3
LL_TIM_CHANNEL_CH3N
LL_TIM_CHANNEL_CH4
LL_TIM_CHANNEL_CH4N
LL_TIM_CHANNEL_CH5
LL_TIM_CHANNEL_CH6
Output Configuration State
LL_TIM_OCSTATE_ENABLE
Output Configuration Mode
LL_TIM_OCMODE_ASYMMETRIC_PWM1
LL_TIM_OCMODE_ASYMMETRIC_PWM2
LL_TIM_OCMODE_COMBINED_PWM1
LL_TIM_OCMODE_COMBINED_PWM2
LL_TIM_OCMODE_DIRECTION_OUTPUT
LL_TIM_OCMODE_FORCED_ACTIVE
LL_TIM_OCMODE_FORCED_INACTIVE
LL_TIM_OCMODE_FROZEN
LL_TIM_OCMODE_INACTIVE
LL_TIM_OCMODE_PULSE_ON_COMPARE
LL_TIM_OCMODE_PWM1
LL_TIM_OCMODE_PWM2
LL_TIM_OCMODE_RETRIG_OPM1
LL_TIM_OCMODE_RETRIG_OPM2
LL_TIM_OCMODE_TOGGLE
Output Configuration Polarity
LL_TIM_OCPOLARITY_LOW
Output Configuration Idle State
LL_TIM_OCIDLESTATE_LOW
GROUPCH5
LL_TIM_GROUPCH5_OC1REFC
LL_TIM_GROUPCH5_OC2REFC
LL_TIM_GROUPCH5_OC3REFC
Active Input Selection
LL_TIM_ACTIVEINPUT_INDIRECTTI
LL_TIM_ACTIVEINPUT_TRC
Input Configuration Prescaler
LL_TIM_ICPSC_DIV2
LL_TIM_ICPSC_DIV4
LL_TIM_ICPSC_DIV8
Input Configuration Filter
LL_TIM_IC_FILTER_FDIV16_N5
LL_TIM_IC_FILTER_FDIV16_N6
LL_TIM_IC_FILTER_FDIV16_N8
LL_TIM_IC_FILTER_FDIV1_N2
LL_TIM_IC_FILTER_FDIV1_N4
LL_TIM_IC_FILTER_FDIV1_N8
LL_TIM_IC_FILTER_FDIV2_N6
LL_TIM_IC_FILTER_FDIV2_N8
LL_TIM_IC_FILTER_FDIV32_N5
LL_TIM_IC_FILTER_FDIV32_N6
LL_TIM_IC_FILTER_FDIV32_N8
LL_TIM_IC_FILTER_FDIV4_N6
LL_TIM_IC_FILTER_FDIV4_N8
LL_TIM_IC_FILTER_FDIV8_N6
LL_TIM_IC_FILTER_FDIV8_N8
Input Configuration Polarity
LL_TIM_IC_POLARITY_FALLING
LL_TIM_IC_POLARITY_RISING
Clock Source
LL_TIM_CLOCKSOURCE_EXT_MODE2
LL_TIM_CLOCKSOURCE_INTERNAL
Encoder Mode
LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
LL_TIM_ENCODERMODE_X1_TI1
LL_TIM_ENCODERMODE_X1_TI2
LL_TIM_ENCODERMODE_X2_TI1
LL_TIM_ENCODERMODE_X2_TI2
LL_TIM_ENCODERMODE_X4_TI12
Trigger Output
LL_TIM_TRGO_ENABLE
LL_TIM_TRGO_ENCODERCLK
LL_TIM_TRGO_OC1REF
LL_TIM_TRGO_OC2REF
LL_TIM_TRGO_OC3REF
LL_TIM_TRGO_OC4REF
LL_TIM_TRGO_RESET
LL_TIM_TRGO_UPDATE
Trigger Output 2
LL_TIM_TRGO2_ENABLE
LL_TIM_TRGO2_OC1
LL_TIM_TRGO2_OC2
LL_TIM_TRGO2_OC3
LL_TIM_TRGO2_OC4
LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
LL_TIM_TRGO2_OC4_RISING_OC6_RISING
LL_TIM_TRGO2_OC4_RISINGFALLING
LL_TIM_TRGO2_OC5
LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
LL_TIM_TRGO2_OC5_RISING_OC6_RISING
LL_TIM_TRGO2_OC6
LL_TIM_TRGO2_OC6_RISINGFALLING
LL_TIM_TRGO2_RESET
LL_TIM_TRGO2_UPDATE
Slave Mode
LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
LL_TIM_SLAVEMODE_DISABLED
LL_TIM_SLAVEMODE_GATED
LL_TIM_SLAVEMODE_RESET
LL_TIM_SLAVEMODE_TRIGGER
SMS Preload Source
LL_TIM_SMSPS_TIMUPDATE
Trigger Selection
LL_TIM_TS_ITR0
LL_TIM_TS_ITR1
LL_TIM_TS_ITR10
LL_TIM_TS_ITR11
LL_TIM_TS_ITR2
LL_TIM_TS_ITR3
LL_TIM_TS_ITR4
LL_TIM_TS_ITR5
LL_TIM_TS_ITR6
LL_TIM_TS_ITR7
LL_TIM_TS_ITR8
LL_TIM_TS_ITR9
LL_TIM_TS_TI1F_ED
LL_TIM_TS_TI1FP1
LL_TIM_TS_TI2FP2
External Trigger Polarity
LL_TIM_ETR_POLARITY_NONINVERTED
External Trigger Prescaler
LL_TIM_ETR_PRESCALER_DIV2
LL_TIM_ETR_PRESCALER_DIV4
LL_TIM_ETR_PRESCALER_DIV8
External Trigger Filter
LL_TIM_ETR_FILTER_FDIV16_N5
LL_TIM_ETR_FILTER_FDIV16_N6
LL_TIM_ETR_FILTER_FDIV16_N8
LL_TIM_ETR_FILTER_FDIV1_N2
LL_TIM_ETR_FILTER_FDIV1_N4
LL_TIM_ETR_FILTER_FDIV1_N8
LL_TIM_ETR_FILTER_FDIV2_N6
LL_TIM_ETR_FILTER_FDIV2_N8
LL_TIM_ETR_FILTER_FDIV32_N5
LL_TIM_ETR_FILTER_FDIV32_N6
LL_TIM_ETR_FILTER_FDIV32_N8
LL_TIM_ETR_FILTER_FDIV4_N6
LL_TIM_ETR_FILTER_FDIV4_N8
LL_TIM_ETR_FILTER_FDIV8_N6
LL_TIM_ETR_FILTER_FDIV8_N8
External Trigger Source TIM1
LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
LL_TIM_TIM1_ETRSOURCE_COMP1
LL_TIM_TIM1_ETRSOURCE_COMP2
LL_TIM_TIM1_ETRSOURCE_COMP3
LL_TIM_TIM1_ETRSOURCE_COMP4
LL_TIM_TIM1_ETRSOURCE_COMP5
LL_TIM_TIM1_ETRSOURCE_COMP6
LL_TIM_TIM1_ETRSOURCE_COMP7
LL_TIM_TIM1_ETRSOURCE_GPIO
External Trigger Source TIM2
LL_TIM_TIM2_ETRSOURCE_COMP2
LL_TIM_TIM2_ETRSOURCE_COMP3
LL_TIM_TIM2_ETRSOURCE_COMP4
LL_TIM_TIM2_ETRSOURCE_COMP5
LL_TIM_TIM2_ETRSOURCE_COMP6
LL_TIM_TIM2_ETRSOURCE_COMP7
LL_TIM_TIM2_ETRSOURCE_GPIO
LL_TIM_TIM2_ETRSOURCE_LSE
LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
External Trigger Source TIM3
LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
LL_TIM_TIM3_ETRSOURCE_COMP1
LL_TIM_TIM3_ETRSOURCE_COMP2
LL_TIM_TIM3_ETRSOURCE_COMP3
LL_TIM_TIM3_ETRSOURCE_COMP4
LL_TIM_TIM3_ETRSOURCE_COMP5
LL_TIM_TIM3_ETRSOURCE_COMP6
LL_TIM_TIM3_ETRSOURCE_COMP7
LL_TIM_TIM3_ETRSOURCE_GPIO
LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
External Trigger Source TIM4
LL_TIM_TIM4_ETRSOURCE_COMP2
LL_TIM_TIM4_ETRSOURCE_COMP3
LL_TIM_TIM4_ETRSOURCE_COMP4
LL_TIM_TIM4_ETRSOURCE_COMP5
LL_TIM_TIM4_ETRSOURCE_COMP6
LL_TIM_TIM4_ETRSOURCE_COMP7
LL_TIM_TIM4_ETRSOURCE_GPIO
LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
External Trigger Source TIM5
LL_TIM_TIM5_ETRSOURCE_COMP2
LL_TIM_TIM5_ETRSOURCE_COMP3
LL_TIM_TIM5_ETRSOURCE_COMP4
LL_TIM_TIM5_ETRSOURCE_COMP5
LL_TIM_TIM5_ETRSOURCE_COMP6
LL_TIM_TIM5_ETRSOURCE_COMP7
LL_TIM_TIM5_ETRSOURCE_GPIO
LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
External Trigger Source TIM8
LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3
LL_TIM_TIM8_ETRSOURCE_COMP1
LL_TIM_TIM8_ETRSOURCE_COMP2
LL_TIM_TIM8_ETRSOURCE_COMP3
LL_TIM_TIM8_ETRSOURCE_COMP4
LL_TIM_TIM8_ETRSOURCE_COMP5
LL_TIM_TIM8_ETRSOURCE_COMP6
LL_TIM_TIM8_ETRSOURCE_COMP7
LL_TIM_TIM8_ETRSOURCE_GPIO
External Trigger Source TIM20
LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2
LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3
LL_TIM_TIM20_ETRSOURCE_COMP1
LL_TIM_TIM20_ETRSOURCE_COMP2
LL_TIM_TIM20_ETRSOURCE_COMP3
LL_TIM_TIM20_ETRSOURCE_COMP4
LL_TIM_TIM20_ETRSOURCE_COMP5
LL_TIM_TIM20_ETRSOURCE_COMP6
LL_TIM_TIM20_ETRSOURCE_COMP7
LL_TIM_TIM20_ETRSOURCE_GPIO
break polarity
LL_TIM_BREAK_POLARITY_LOW
break filter
LL_TIM_BREAK_FILTER_FDIV16_N5
LL_TIM_BREAK_FILTER_FDIV16_N6
LL_TIM_BREAK_FILTER_FDIV16_N8
LL_TIM_BREAK_FILTER_FDIV1_N2
LL_TIM_BREAK_FILTER_FDIV1_N4
LL_TIM_BREAK_FILTER_FDIV1_N8
LL_TIM_BREAK_FILTER_FDIV2_N6
LL_TIM_BREAK_FILTER_FDIV2_N8
LL_TIM_BREAK_FILTER_FDIV32_N5
LL_TIM_BREAK_FILTER_FDIV32_N6
LL_TIM_BREAK_FILTER_FDIV32_N8
LL_TIM_BREAK_FILTER_FDIV4_N6
LL_TIM_BREAK_FILTER_FDIV4_N8
LL_TIM_BREAK_FILTER_FDIV8_N6
LL_TIM_BREAK_FILTER_FDIV8_N8
BREAK2 POLARITY
LL_TIM_BREAK2_POLARITY_LOW
BREAK2 FILTER
LL_TIM_BREAK2_FILTER_FDIV16_N5
LL_TIM_BREAK2_FILTER_FDIV16_N6
LL_TIM_BREAK2_FILTER_FDIV16_N8
LL_TIM_BREAK2_FILTER_FDIV1_N2
LL_TIM_BREAK2_FILTER_FDIV1_N4
LL_TIM_BREAK2_FILTER_FDIV1_N8
LL_TIM_BREAK2_FILTER_FDIV2_N6
LL_TIM_BREAK2_FILTER_FDIV2_N8
LL_TIM_BREAK2_FILTER_FDIV32_N5
LL_TIM_BREAK2_FILTER_FDIV32_N6
LL_TIM_BREAK2_FILTER_FDIV32_N8
LL_TIM_BREAK2_FILTER_FDIV4_N6
LL_TIM_BREAK2_FILTER_FDIV4_N8
LL_TIM_BREAK2_FILTER_FDIV8_N6
LL_TIM_BREAK2_FILTER_FDIV8_N8
OSSI
LL_TIM_OSSI_ENABLE
OSSR
LL_TIM_OSSR_ENABLE
BREAK INPUT
LL_TIM_BREAK_INPUT_BKIN2
BKIN SOURCE
LL_TIM_BKIN_SOURCE_BKCOMP2
LL_TIM_BKIN_SOURCE_BKCOMP3
LL_TIM_BKIN_SOURCE_BKCOMP4
LL_TIM_BKIN_SOURCE_BKCOMP5
LL_TIM_BKIN_SOURCE_BKCOMP6
LL_TIM_BKIN_SOURCE_BKCOMP7
LL_TIM_BKIN_SOURCE_BKIN
BKIN POLARITY
LL_TIM_BKIN_POLARITY_LOW
BREAK AF MODE
LL_TIM_BREAK_AFMODE_INPUT
BREAK2 AF MODE
LL_TIM_BREAK2_AFMODE_INPUT
DMA Burst Base Address
LL_TIM_DMABURST_BASEADDR_AF2
LL_TIM_DMABURST_BASEADDR_ARR
LL_TIM_DMABURST_BASEADDR_BDTR
LL_TIM_DMABURST_BASEADDR_CCER
LL_TIM_DMABURST_BASEADDR_CCMR1
LL_TIM_DMABURST_BASEADDR_CCMR2
LL_TIM_DMABURST_BASEADDR_CCMR3
LL_TIM_DMABURST_BASEADDR_CCR1
LL_TIM_DMABURST_BASEADDR_CCR2
LL_TIM_DMABURST_BASEADDR_CCR3
LL_TIM_DMABURST_BASEADDR_CCR4
LL_TIM_DMABURST_BASEADDR_CCR5
LL_TIM_DMABURST_BASEADDR_CCR6
LL_TIM_DMABURST_BASEADDR_CNT
LL_TIM_DMABURST_BASEADDR_CR1
LL_TIM_DMABURST_BASEADDR_CR2
LL_TIM_DMABURST_BASEADDR_DIER
LL_TIM_DMABURST_BASEADDR_DTR2
LL_TIM_DMABURST_BASEADDR_ECR
LL_TIM_DMABURST_BASEADDR_EGR
LL_TIM_DMABURST_BASEADDR_OR
LL_TIM_DMABURST_BASEADDR_PSC
LL_TIM_DMABURST_BASEADDR_RCR
LL_TIM_DMABURST_BASEADDR_SMCR
LL_TIM_DMABURST_BASEADDR_SR
LL_TIM_DMABURST_BASEADDR_TISEL
DMA Burst Length
LL_TIM_DMABURST_LENGTH_11TRANSFERS
LL_TIM_DMABURST_LENGTH_12TRANSFERS
LL_TIM_DMABURST_LENGTH_13TRANSFERS
LL_TIM_DMABURST_LENGTH_14TRANSFERS
LL_TIM_DMABURST_LENGTH_15TRANSFERS
LL_TIM_DMABURST_LENGTH_16TRANSFERS
LL_TIM_DMABURST_LENGTH_17TRANSFERS
LL_TIM_DMABURST_LENGTH_18TRANSFERS
LL_TIM_DMABURST_LENGTH_19TRANSFERS
LL_TIM_DMABURST_LENGTH_1TRANSFER
LL_TIM_DMABURST_LENGTH_20TRANSFERS
LL_TIM_DMABURST_LENGTH_21TRANSFERS
LL_TIM_DMABURST_LENGTH_22TRANSFERS
LL_TIM_DMABURST_LENGTH_23TRANSFERS
LL_TIM_DMABURST_LENGTH_24TRANSFERS
LL_TIM_DMABURST_LENGTH_25TRANSFERS
LL_TIM_DMABURST_LENGTH_26TRANSFERS
LL_TIM_DMABURST_LENGTH_2TRANSFERS
LL_TIM_DMABURST_LENGTH_3TRANSFERS
LL_TIM_DMABURST_LENGTH_4TRANSFERS
LL_TIM_DMABURST_LENGTH_5TRANSFERS
LL_TIM_DMABURST_LENGTH_6TRANSFERS
LL_TIM_DMABURST_LENGTH_7TRANSFERS
LL_TIM_DMABURST_LENGTH_8TRANSFERS
LL_TIM_DMABURST_LENGTH_9TRANSFERS
TIM1 Timer Input Ch1 Remap
LL_TIM_TIM1_TI1_RMP_COMP2
LL_TIM_TIM1_TI1_RMP_COMP3
LL_TIM_TIM1_TI1_RMP_COMP4
LL_TIM_TIM1_TI1_RMP_GPIO
TIM2 Timer Input Ch1 Remap
LL_TIM_TIM2_TI1_RMP_COMP2
LL_TIM_TIM2_TI1_RMP_COMP3
LL_TIM_TIM2_TI1_RMP_COMP4
LL_TIM_TIM2_TI1_RMP_COMP5
LL_TIM_TIM2_TI1_RMP_GPIO
TIM2 Timer Input Ch2 Remap
LL_TIM_TIM2_TI2_RMP_COMP2
LL_TIM_TIM2_TI2_RMP_COMP3
LL_TIM_TIM2_TI2_RMP_COMP4
LL_TIM_TIM2_TI2_RMP_COMP6
LL_TIM_TIM2_TI2_RMP_GPIO
TIM2 Timer Input Ch3 Remap
LL_TIM_TIM2_TI3_RMP_GPIO
TIM2 Timer Input Ch4 Remap
LL_TIM_TIM2_TI4_RMP_COMP2
LL_TIM_TIM2_TI4_RMP_GPIO
TIM3 Timer Input Ch1 Remap
LL_TIM_TIM3_TI1_RMP_COMP2
LL_TIM_TIM3_TI1_RMP_COMP3
LL_TIM_TIM3_TI1_RMP_COMP4
LL_TIM_TIM3_TI1_RMP_COMP5
LL_TIM_TIM3_TI1_RMP_COMP6
LL_TIM_TIM3_TI1_RMP_COMP7
LL_TIM_TIM3_TI1_RMP_GPIO
TIM3 Timer Input Ch2 Remap
LL_TIM_TIM3_TI2_RMP_COMP2
LL_TIM_TIM3_TI2_RMP_COMP3
LL_TIM_TIM3_TI2_RMP_COMP4
LL_TIM_TIM3_TI2_RMP_COMP5
LL_TIM_TIM3_TI2_RMP_COMP6
LL_TIM_TIM3_TI2_RMP_COMP7
LL_TIM_TIM3_TI2_RMP_GPIO
TIM3 Timer Input Ch3 Remap
LL_TIM_TIM3_TI3_RMP_GPIO
TIM4 Timer Input Ch1 Remap
LL_TIM_TIM4_TI1_RMP_COMP2
LL_TIM_TIM4_TI1_RMP_COMP3
LL_TIM_TIM4_TI1_RMP_COMP4
LL_TIM_TIM4_TI1_RMP_COMP5
LL_TIM_TIM4_TI1_RMP_COMP6
LL_TIM_TIM4_TI1_RMP_COMP7
LL_TIM_TIM4_TI1_RMP_GPIO
TIM4 Timer Input Ch2 Remap
LL_TIM_TIM4_TI2_RMP_COMP2
LL_TIM_TIM4_TI2_RMP_COMP3
LL_TIM_TIM4_TI2_RMP_COMP4
LL_TIM_TIM4_TI2_RMP_COMP5
LL_TIM_TIM4_TI2_RMP_COMP6
LL_TIM_TIM4_TI2_RMP_COMP7
LL_TIM_TIM4_TI2_RMP_GPIO
TIM4 Timer Input Ch3 Remap
LL_TIM_TIM4_TI3_RMP_GPIO
TIM4 Timer Input Ch4 Remap
LL_TIM_TIM4_TI4_RMP_GPIO
TIM5 Timer Input Ch1 Remap
LL_TIM_TIM5_TI1_RMP_COMP2
LL_TIM_TIM5_TI1_RMP_COMP3
LL_TIM_TIM5_TI1_RMP_COMP4
LL_TIM_TIM5_TI1_RMP_COMP5
LL_TIM_TIM5_TI1_RMP_COMP6
LL_TIM_TIM5_TI1_RMP_COMP7
LL_TIM_TIM5_TI1_RMP_GPIO
LL_TIM_TIM5_TI1_RMP_LSE
LL_TIM_TIM5_TI1_RMP_LSI
LL_TIM_TIM5_TI1_RMP_RTC_WK
TIM5 Timer Input Ch2 Remap
LL_TIM_TIM5_TI2_RMP_COMP2
LL_TIM_TIM5_TI2_RMP_COMP3
LL_TIM_TIM5_TI2_RMP_COMP4
LL_TIM_TIM5_TI2_RMP_COMP5
LL_TIM_TIM5_TI2_RMP_COMP6
LL_TIM_TIM5_TI2_RMP_COMP7
LL_TIM_TIM5_TI2_RMP_GPIO
TIM8 Timer Input Ch1 Remap
LL_TIM_TIM8_TI1_RMP_COMP2
LL_TIM_TIM8_TI1_RMP_COMP3
LL_TIM_TIM8_TI1_RMP_COMP4
LL_TIM_TIM8_TI1_RMP_GPIO
TIM15 Timer Input Ch1 Remap
LL_TIM_TIM15_TI1_RMP_COMP2
LL_TIM_TIM15_TI1_RMP_COMP5
LL_TIM_TIM15_TI1_RMP_COMP7
LL_TIM_TIM15_TI1_RMP_GPIO
LL_TIM_TIM15_TI1_RMP_LSE
TIM15 Timer Input Ch2 Remap
LL_TIM_TIM15_TI2_RMP_COMP3
LL_TIM_TIM15_TI2_RMP_COMP6
LL_TIM_TIM15_TI2_RMP_COMP7
LL_TIM_TIM15_TI2_RMP_GPIO
TIM16 Timer Input Ch1 Remap
LL_TIM_TIM16_TI1_RMP_GPIO
LL_TIM_TIM16_TI1_RMP_HSE_32
LL_TIM_TIM16_TI1_RMP_LSE
LL_TIM_TIM16_TI1_RMP_LSI
LL_TIM_TIM16_TI1_RMP_MCO
LL_TIM_TIM16_TI1_RMP_RTC_WK
TIM17 Timer Input Ch1 Remap
LL_TIM_TIM17_TI1_RMP_GPIO
LL_TIM_TIM17_TI1_RMP_HSE_32
LL_TIM_TIM17_TI1_RMP_LSE
LL_TIM_TIM17_TI1_RMP_LSI
LL_TIM_TIM17_TI1_RMP_MCO
LL_TIM_TIM17_TI1_RMP_RTC_WK
TIM20 Timer Input Ch1 Remap
LL_TIM_TIM20_TI1_RMP_COMP2
LL_TIM_TIM20_TI1_RMP_COMP3
LL_TIM_TIM20_TI1_RMP_COMP4
LL_TIM_TIM20_TI1_RMP_GPIO
OCREF clear input selection
LL_TIM_OCREF_CLR_INT_COMP2
LL_TIM_OCREF_CLR_INT_COMP3
LL_TIM_OCREF_CLR_INT_COMP4
LL_TIM_OCREF_CLR_INT_COMP5
LL_TIM_OCREF_CLR_INT_COMP6
LL_TIM_OCREF_CLR_INT_COMP7
LL_TIM_OCREF_CLR_INT_ETR
index direction selection
LL_TIM_INDEX_UP
LL_TIM_INDEX_UP_DOWN
index positioning selection
LL_TIM_INDEX_POSITION_DOWN_DOWN
LL_TIM_INDEX_POSITION_DOWN_UP
LL_TIM_INDEX_POSITION_UP
LL_TIM_INDEX_POSITION_UP_DOWN
LL_TIM_INDEX_POSITION_UP_UP
first index selection
LL_TIM_INDEX_FIRST_ONLY
Pulse on compare pulse width prescaler
LL_TIM_PWPRSC_X128
LL_TIM_PWPRSC_X16
LL_TIM_PWPRSC_X2
LL_TIM_PWPRSC_X32
LL_TIM_PWPRSC_X4
LL_TIM_PWPRSC_X64
LL_TIM_PWPRSC_X8
Clock HSE/32 request
LL_TIM_HSE_32_REQUEST
TIM Exported Macros
LL_TIM_WriteReg
Defines
__LL_TIM_CALC_ARR_DITHER
__LL_TIM_CALC_DEADTIME
__LL_TIM_CALC_DELAY
__LL_TIM_CALC_DELAY_DITHER
__LL_TIM_CALC_PSC
__LL_TIM_CALC_PULSE
__LL_TIM_CALC_PULSE_DITHER
__LL_TIM_GET_ICPSC_RATIO
__LL_TIM_GETFLAG_UIFCPY
TIM Exported Functions
LL_TIM_DisableCounter
LL_TIM_DisableDithering
LL_TIM_DisableUIFRemap
LL_TIM_DisableUpdateEvent
LL_TIM_EnableARRPreload
LL_TIM_EnableCounter
LL_TIM_EnableDithering
LL_TIM_EnableUIFRemap
LL_TIM_EnableUpdateEvent
LL_TIM_GetAutoReload
LL_TIM_GetClockDivision
LL_TIM_GetCounter
LL_TIM_GetCounterMode
LL_TIM_GetDirection
LL_TIM_GetOnePulseMode
LL_TIM_GetPrescaler
LL_TIM_GetRepetitionCounter
LL_TIM_GetUpdateSource
LL_TIM_IsActiveUIFCPY
LL_TIM_IsEnabledARRPreload
LL_TIM_IsEnabledCounter
LL_TIM_IsEnabledDithering
LL_TIM_IsEnabledUpdateEvent
LL_TIM_SetAutoReload
LL_TIM_SetClockDivision
LL_TIM_SetCounter
LL_TIM_SetCounterMode
LL_TIM_SetOnePulseMode
LL_TIM_SetPrescaler
LL_TIM_SetRepetitionCounter
LL_TIM_SetUpdateSource
Capture Compare configuration
LL_TIM_CC_DisablePreload
LL_TIM_CC_EnableChannel
LL_TIM_CC_EnablePreload
LL_TIM_CC_GetDMAReqTrigger
LL_TIM_CC_IsEnabledChannel
LL_TIM_CC_IsEnabledPreload
LL_TIM_CC_SetDMAReqTrigger
LL_TIM_CC_SetLockLevel
LL_TIM_CC_SetUpdate
Output channel configuration
LL_TIM_OC_DisableClear
LL_TIM_OC_DisableFast
LL_TIM_OC_DisablePreload
LL_TIM_OC_EnableClear
LL_TIM_OC_EnableFast
LL_TIM_OC_EnablePreload
LL_TIM_OC_GetCompareCH1
LL_TIM_OC_GetCompareCH2
LL_TIM_OC_GetCompareCH3
LL_TIM_OC_GetCompareCH4
LL_TIM_OC_GetCompareCH5
LL_TIM_OC_GetCompareCH6
LL_TIM_OC_GetIdleState
LL_TIM_OC_GetMode
LL_TIM_OC_GetPolarity
LL_TIM_OC_GetPulseWidth
LL_TIM_OC_GetPulseWidthPrescaler
LL_TIM_OC_IsEnabledClear
LL_TIM_OC_IsEnabledFast
LL_TIM_OC_IsEnabledPreload
LL_TIM_OC_SetCompareCH1
LL_TIM_OC_SetCompareCH2
LL_TIM_OC_SetCompareCH3
LL_TIM_OC_SetCompareCH4
LL_TIM_OC_SetCompareCH5
LL_TIM_OC_SetCompareCH6
LL_TIM_OC_SetDeadTime
LL_TIM_OC_SetIdleState
LL_TIM_OC_SetMode
LL_TIM_OC_SetPolarity
LL_TIM_OC_SetPulseWidth
LL_TIM_OC_SetPulseWidthPrescaler
LL_TIM_SetCH5CombinedChannels
Input channel configuration
LL_TIM_IC_DisableXORCombination
LL_TIM_IC_EnableXORCombination
LL_TIM_IC_GetActiveInput
LL_TIM_IC_GetCaptureCH1
LL_TIM_IC_GetCaptureCH2
LL_TIM_IC_GetCaptureCH3
LL_TIM_IC_GetCaptureCH4
LL_TIM_IC_GetFilter
LL_TIM_IC_GetPolarity
LL_TIM_IC_GetPrescaler
LL_TIM_IC_IsEnabledXORCombination
LL_TIM_IC_SetActiveInput
LL_TIM_IC_SetFilter
LL_TIM_IC_SetPolarity
LL_TIM_IC_SetPrescaler
Counter clock selection
LL_TIM_EnableExternalClock
LL_TIM_IsEnabledExternalClock
LL_TIM_SetClockSource
LL_TIM_SetEncoderMode
Timer synchronisation configuration
LL_TIM_DisableMasterSlaveMode
LL_TIM_DisableSMSPreload
LL_TIM_EnableMasterSlaveMode
LL_TIM_EnableSMSPreload
LL_TIM_GetSMSPreloadSource
LL_TIM_IsEnabledMasterSlaveMode
LL_TIM_IsEnabledSMSPreload
LL_TIM_SetETRSource
LL_TIM_SetSlaveMode
LL_TIM_SetSMSPreloadSource
LL_TIM_SetTriggerInput
LL_TIM_SetTriggerOutput
LL_TIM_SetTriggerOutput2
Break function configuration
LL_TIM_ConfigBRK2
LL_TIM_DisableAllOutputs
LL_TIM_DisableAsymmetricalDeadTime
LL_TIM_DisableAutomaticOutput
LL_TIM_DisableBreakInputSource
LL_TIM_DisableBRK
LL_TIM_DisableBRK2
LL_TIM_DisableDeadTimePreload
LL_TIM_DisarmBRK
LL_TIM_DisarmBRK2
LL_TIM_EnableAllOutputs
LL_TIM_EnableAsymmetricalDeadTime
LL_TIM_EnableAutomaticOutput
LL_TIM_EnableBreakInputSource
LL_TIM_EnableBRK
LL_TIM_EnableBRK2
LL_TIM_EnableDeadTimePreload
LL_TIM_GetFallingDeadTime
LL_TIM_IsEnabledAllOutputs
LL_TIM_IsEnabledAsymmetricalDeadTime
LL_TIM_IsEnabledAutomaticOutput
LL_TIM_IsEnabledDeadTimePreload
LL_TIM_SetBreakInputSourcePolarity
LL_TIM_SetFallingDeadTime
LL_TIM_SetOffStates
DMA burst mode configuration
Encoder configuration
LL_TIM_DisableEncoderIndex
LL_TIM_DisableFirstIndex
LL_TIM_EnableEncoderIndex
LL_TIM_EnableFirstIndex
LL_TIM_GetIndexDirection
LL_TIM_GetIndexPositionning
LL_TIM_IsEnabledEncoderIndex
LL_TIM_IsEnabledFirstIndex
LL_TIM_SetIndexDirection
LL_TIM_SetIndexPositionning
Timer input remapping
LL_TIM_EnableHSE32
LL_TIM_IsEnabledHSE32
LL_TIM_SetRemap
OCREF_Clear_Management
FLAG-Management
LL_TIM_ClearFlag_BRK2
LL_TIM_ClearFlag_CC1
LL_TIM_ClearFlag_CC1OVR
LL_TIM_ClearFlag_CC2
LL_TIM_ClearFlag_CC2OVR
LL_TIM_ClearFlag_CC3
LL_TIM_ClearFlag_CC3OVR
LL_TIM_ClearFlag_CC4
LL_TIM_ClearFlag_CC4OVR
LL_TIM_ClearFlag_CC5
LL_TIM_ClearFlag_CC6
LL_TIM_ClearFlag_COM
LL_TIM_ClearFlag_DIR
LL_TIM_ClearFlag_IDX
LL_TIM_ClearFlag_IERR
LL_TIM_ClearFlag_SYSBRK
LL_TIM_ClearFlag_TERR
LL_TIM_ClearFlag_TRIG
LL_TIM_ClearFlag_UPDATE
LL_TIM_IsActiveFlag_BRK
LL_TIM_IsActiveFlag_BRK2
LL_TIM_IsActiveFlag_CC1
LL_TIM_IsActiveFlag_CC1OVR
LL_TIM_IsActiveFlag_CC2
LL_TIM_IsActiveFlag_CC2OVR
LL_TIM_IsActiveFlag_CC3
LL_TIM_IsActiveFlag_CC3OVR
LL_TIM_IsActiveFlag_CC4
LL_TIM_IsActiveFlag_CC4OVR
LL_TIM_IsActiveFlag_CC5
LL_TIM_IsActiveFlag_CC6
LL_TIM_IsActiveFlag_COM
LL_TIM_IsActiveFlag_DIR
LL_TIM_IsActiveFlag_IDX
LL_TIM_IsActiveFlag_IERR
LL_TIM_IsActiveFlag_SYSBRK
LL_TIM_IsActiveFlag_TERR
LL_TIM_IsActiveFlag_TRIG
LL_TIM_IsActiveFlag_UPDATE
IT-Management
LL_TIM_DisableIT_CC1
LL_TIM_DisableIT_CC2
LL_TIM_DisableIT_CC3
LL_TIM_DisableIT_CC4
LL_TIM_DisableIT_COM
LL_TIM_DisableIT_DIR
LL_TIM_DisableIT_IDX
LL_TIM_DisableIT_IERR
LL_TIM_DisableIT_TERR
LL_TIM_DisableIT_TRIG
LL_TIM_DisableIT_UPDATE
LL_TIM_EnableIT_BRK
LL_TIM_EnableIT_CC1
LL_TIM_EnableIT_CC2
LL_TIM_EnableIT_CC3
LL_TIM_EnableIT_CC4
LL_TIM_EnableIT_COM
LL_TIM_EnableIT_DIR
LL_TIM_EnableIT_IDX
LL_TIM_EnableIT_IERR
LL_TIM_EnableIT_TERR
LL_TIM_EnableIT_TRIG
LL_TIM_EnableIT_UPDATE
LL_TIM_IsEnabledIT_BRK
LL_TIM_IsEnabledIT_CC1
LL_TIM_IsEnabledIT_CC2
LL_TIM_IsEnabledIT_CC3
LL_TIM_IsEnabledIT_CC4
LL_TIM_IsEnabledIT_COM
LL_TIM_IsEnabledIT_DIR
LL_TIM_IsEnabledIT_IDX
LL_TIM_IsEnabledIT_IERR
LL_TIM_IsEnabledIT_TERR
LL_TIM_IsEnabledIT_TRIG
LL_TIM_IsEnabledIT_UPDATE
DMA Management
LL_TIM_DisableDMAReq_CC2
LL_TIM_DisableDMAReq_CC3
LL_TIM_DisableDMAReq_CC4
LL_TIM_DisableDMAReq_COM
LL_TIM_DisableDMAReq_TRIG
LL_TIM_DisableDMAReq_UPDATE
LL_TIM_EnableDMAReq_CC1
LL_TIM_EnableDMAReq_CC2
LL_TIM_EnableDMAReq_CC3
LL_TIM_EnableDMAReq_CC4
LL_TIM_EnableDMAReq_COM
LL_TIM_EnableDMAReq_TRIG
LL_TIM_EnableDMAReq_UPDATE
LL_TIM_IsEnabledDMAReq_CC1
LL_TIM_IsEnabledDMAReq_CC2
LL_TIM_IsEnabledDMAReq_CC3
LL_TIM_IsEnabledDMAReq_CC4
LL_TIM_IsEnabledDMAReq_COM
LL_TIM_IsEnabledDMAReq_TRIG
LL_TIM_IsEnabledDMAReq_UPDATE
EVENT-Management
LL_TIM_GenerateEvent_BRK2
LL_TIM_GenerateEvent_CC1
LL_TIM_GenerateEvent_CC2
LL_TIM_GenerateEvent_CC3
LL_TIM_GenerateEvent_CC4
LL_TIM_GenerateEvent_COM
LL_TIM_GenerateEvent_TRIG
LL_TIM_GenerateEvent_UPDATE
Initialisation and deinitialisation functions
LL_TIM_BDTR_StructInit
LL_TIM_DeInit
LL_TIM_ENCODER_Init
LL_TIM_ENCODER_StructInit
LL_TIM_HALLSENSOR_Init
LL_TIM_HALLSENSOR_StructInit
LL_TIM_IC_Init
LL_TIM_IC_StructInit
LL_TIM_Init
LL_TIM_OC_Init
LL_TIM_OC_StructInit
LL_TIM_StructInit
UCPD
UCPD Private Macros
UCPD Exported Init structure
UCPD Exported Constants
LL_UCPD_SR_HRSTDISC
LL_UCPD_SR_HRSTSENT
LL_UCPD_SR_RXERR
LL_UCPD_SR_RXHRSTDET
LL_UCPD_SR_RXMSGEND
LL_UCPD_SR_RXNE
LL_UCPD_SR_RXORDDET
LL_UCPD_SR_RXOVR
LL_UCPD_SR_TXIS
LL_UCPD_SR_TXMSGABT
LL_UCPD_SR_TXMSGDISC
LL_UCPD_SR_TXMSGSENT
LL_UCPD_SR_TXUND
LL_UCPD_SR_TYPEC_VSTATE_CC1
LL_UCPD_SR_TYPEC_VSTATE_CC2
LL_UCPD_SR_TYPECEVT1
LL_UCPD_SR_TYPECEVT2
IT Defines
LL_UCPD_IMR_HRSTDISC
LL_UCPD_IMR_HRSTSENT
LL_UCPD_IMR_RXHRSTDET
LL_UCPD_IMR_RXMSGEND
LL_UCPD_IMR_RXNE
LL_UCPD_IMR_RXORDDET
LL_UCPD_IMR_RXOVR
LL_UCPD_IMR_TXIS
LL_UCPD_IMR_TXMSGABT
LL_UCPD_IMR_TXMSGDISC
LL_UCPD_IMR_TXMSGSENT
LL_UCPD_IMR_TXUND
LL_UCPD_IMR_TYPECEVT1
LL_UCPD_IMR_TYPECEVT2
Ordered sets value
LL_UCPD_ORDERED_SET_CABLE_RESET
LL_UCPD_ORDERED_SET_HARD_RESET
LL_UCPD_ORDERED_SET_SOP
LL_UCPD_ORDERED_SET_SOP1
LL_UCPD_ORDERED_SET_SOP1_DEBUG
LL_UCPD_ORDERED_SET_SOP2
LL_UCPD_ORDERED_SET_SOP2_DEBUG
LL_UCPD_RST1
LL_UCPD_RST2
LL_UCPD_SYNC1
LL_UCPD_SYNC2
LL_UCPD_SYNC3
Role Mode
LL_UCPD_ROLE_SRC
Resistor value
LL_UCPD_RESISTOR_3_0A
LL_UCPD_RESISTOR_DEFAULT
LL_UCPD_RESISTOR_NONE
ordered set configuration
LL_UCPD_ORDERSET_HARDRST
LL_UCPD_ORDERSET_SOP
LL_UCPD_ORDERSET_SOP1
LL_UCPD_ORDERSET_SOP1_DEBUG
LL_UCPD_ORDERSET_SOP2
LL_UCPD_ORDERSET_SOP2_DEBUG
LL_UCPD_ORDERSET_SOP_EXT1
LL_UCPD_ORDERSET_SOP_EXT2
CCx event
LL_UCPD_SNK_CC1_VRP
LL_UCPD_SNK_CC1_VRP15A
LL_UCPD_SNK_CC1_VRP30A
LL_UCPD_SNK_CC2_VOPEN
LL_UCPD_SNK_CC2_VRP
LL_UCPD_SNK_CC2_VRP15A
LL_UCPD_SNK_CC2_VRP30A
LL_UCPD_SRC_CC1_OPEN
LL_UCPD_SRC_CC1_VRA
LL_UCPD_SRC_CC1_VRD
LL_UCPD_SRC_CC2_OPEN
LL_UCPD_SRC_CC2_VRA
LL_UCPD_SRC_CC2_VRD
prescaler for UCPDCLK
LL_UCPD_PSC_DIV16
LL_UCPD_PSC_DIV2
LL_UCPD_PSC_DIV4
LL_UCPD_PSC_DIV8
CC pin enable
LL_UCPD_CCENABLE_CC1CC2
LL_UCPD_CCENABLE_CC2
LL_UCPD_CCENABLE_NONE
CC pin selection
LL_UCPD_CCPIN_CC2
Receiver mode
LL_UCPD_RXMODE_NORMAL
Type of Tx packet
LL_UCPD_TXMODE_CABLE_RESET
LL_UCPD_TXMODE_NORMAL
Rx ordered set code detected
LL_UCPD_RXORDSET_SOP
LL_UCPD_RXORDSET_SOP1
LL_UCPD_RXORDSET_SOP1_DEBUG
LL_UCPD_RXORDSET_SOP2
LL_UCPD_RXORDSET_SOP2_DEBUG
LL_UCPD_RXORDSET_SOPEXT1
LL_UCPD_RXORDSET_SOPEXT2
UCPD Exported Macros
LL_UCPD_WriteReg
UCPD Exported Functions
LL_UCPD_Enable
LL_UCPD_IsEnabled
LL_UCPD_SetHbitClockDiv
LL_UCPD_SetIfrGap
LL_UCPD_SetPSCClk
LL_UCPD_SetRxOrderSet
LL_UCPD_SetTransWin
CFG2 register
LL_UCPD_ForceClockEnable
LL_UCPD_RxFilterDisable
LL_UCPD_RxFilterEnable
LL_UCPD_WakeUpDisable
LL_UCPD_WakeUpEnable
CR register
LL_UCPD_FRSDetectionEnable
LL_UCPD_GetRole
LL_UCPD_RxDisable
LL_UCPD_RxEnable
LL_UCPD_SendHardReset
LL_UCPD_SendMessage
LL_UCPD_SetccEnable
LL_UCPD_SetCCPin
LL_UCPD_SetRpResistor
LL_UCPD_SetRxMode
LL_UCPD_SetSNKRole
LL_UCPD_SetSRCRole
LL_UCPD_SetTxMode
LL_UCPD_SignalFRSTX
LL_UCPD_TypeCDetectionCC1Disable
LL_UCPD_TypeCDetectionCC1Enable
LL_UCPD_TypeCDetectionCC2Disable
LL_UCPD_TypeCDetectionCC2Enable
LL_UCPD_VconnDischargeDisable
LL_UCPD_VconnDischargeEnable
Interrupt Management
LL_UCPD_DisableIT_RxHRST
LL_UCPD_DisableIT_RxMsgEnd
LL_UCPD_DisableIT_RxNE
LL_UCPD_DisableIT_RxOrderSet
LL_UCPD_DisableIT_RxOvr
LL_UCPD_DisableIT_TxHRSTDISC
LL_UCPD_DisableIT_TxHRSTSENT
LL_UCPD_DisableIT_TxIS
LL_UCPD_DisableIT_TxMSGABT
LL_UCPD_DisableIT_TxMSGDISC
LL_UCPD_DisableIT_TxMSGSENT
LL_UCPD_DisableIT_TxUND
LL_UCPD_DisableIT_TypeCEventCC1
LL_UCPD_DisableIT_TypeCEventCC2
LL_UCPD_EnableIT_FRS
LL_UCPD_EnableIT_RxHRST
LL_UCPD_EnableIT_RxMsgEnd
LL_UCPD_EnableIT_RxNE
LL_UCPD_EnableIT_RxOrderSet
LL_UCPD_EnableIT_RxOvr
LL_UCPD_EnableIT_TxHRSTDISC
LL_UCPD_EnableIT_TxHRSTSENT
LL_UCPD_EnableIT_TxIS
LL_UCPD_EnableIT_TxMSGABT
LL_UCPD_EnableIT_TxMSGDISC
LL_UCPD_EnableIT_TxMSGSENT
LL_UCPD_EnableIT_TxUND
LL_UCPD_EnableIT_TypeCEventCC1
LL_UCPD_EnableIT_TypeCEventCC2
LL_UCPD_IsEnableIT_FRS
LL_UCPD_IsEnableIT_RxHRST
LL_UCPD_IsEnableIT_RxMsgEnd
LL_UCPD_IsEnableIT_RxNE
LL_UCPD_IsEnableIT_RxOrderSet
LL_UCPD_IsEnableIT_RxOvr
LL_UCPD_IsEnableIT_TxHRSTDISC
LL_UCPD_IsEnableIT_TxHRSTSENT
LL_UCPD_IsEnableIT_TxIS
LL_UCPD_IsEnableIT_TxMSGABT
LL_UCPD_IsEnableIT_TxMSGDISC
LL_UCPD_IsEnableIT_TxMSGSENT
LL_UCPD_IsEnableIT_TxUND
LL_UCPD_IsEnableIT_TypeCEventCC1
LL_UCPD_IsEnableIT_TypeCEventCC2
Interrupt Clear
LL_UCPD_ClearFlag_RxHRST
LL_UCPD_ClearFlag_RxMsgEnd
LL_UCPD_ClearFlag_RxOrderSet
LL_UCPD_ClearFlag_RxOvr
LL_UCPD_ClearFlag_TxHRSTDISC
LL_UCPD_ClearFlag_TxHRSTSENT
LL_UCPD_ClearFlag_TxMSGABT
LL_UCPD_ClearFlag_TxMSGDISC
LL_UCPD_ClearFlag_TxMSGSENT
LL_UCPD_ClearFlag_TxUND
LL_UCPD_ClearFlag_TypeCEventCC1
LL_UCPD_ClearFlag_TypeCEventCC2
FLAG Management
LL_UCPD_GetTypeCVstateCC2
LL_UCPD_IsActiveFlag_FRS
LL_UCPD_IsActiveFlag_RxErr
LL_UCPD_IsActiveFlag_RxHRST
LL_UCPD_IsActiveFlag_RxMsgEnd
LL_UCPD_IsActiveFlag_RxNE
LL_UCPD_IsActiveFlag_RxOrderSet
LL_UCPD_IsActiveFlag_RxOvr
LL_UCPD_IsActiveFlag_TxHRSTDISC
LL_UCPD_IsActiveFlag_TxHRSTSENT
LL_UCPD_IsActiveFlag_TxIS
LL_UCPD_IsActiveFlag_TxMSGABT
LL_UCPD_IsActiveFlag_TxMSGDISC
LL_UCPD_IsActiveFlag_TxMSGSENT
LL_UCPD_IsActiveFlag_TxUND
LL_UCPD_IsActiveFlag_TypeCEventCC1
LL_UCPD_IsActiveFlag_TypeCEventCC2
DMA Management
LL_UCPD_IsEnabledTxDMA
LL_UCPD_RxDMADisable
LL_UCPD_RxDMAEnable
LL_UCPD_TxDMADisable
LL_UCPD_TxDMAEnable
DATA Management
LL_UCPD_ReadRxOrderSet
LL_UCPD_ReadRxPaySize
LL_UCPD_SetRxOrdExt1
LL_UCPD_SetRxOrdExt2
LL_UCPD_WriteData
LL_UCPD_WriteTxOrderSet
LL_UCPD_WriteTxPaySize
Initialization and de-initialization functions
LL_UCPD_Init
LL_UCPD_StructInit
USART
USART Private Constants
USART Private Macros
IS_LL_USART_BRR_MIN
IS_LL_USART_CLOCKOUTPUT
IS_LL_USART_CLOCKPHASE
IS_LL_USART_CLOCKPOLARITY
IS_LL_USART_DATAWIDTH
IS_LL_USART_DIRECTION
IS_LL_USART_HWCONTROL
IS_LL_USART_LASTBITCLKOUTPUT
IS_LL_USART_OVERSAMPLING
IS_LL_USART_PARITY
IS_LL_USART_PRESCALER
IS_LL_USART_STOPBITS
USART Exported Init structures
LL_USART_ClockInitTypeDef
USART Exported Constants
LL_USART_ICR_CTSCF
LL_USART_ICR_EOBCF
LL_USART_ICR_FECF
LL_USART_ICR_IDLECF
LL_USART_ICR_LBDCF
LL_USART_ICR_NECF
LL_USART_ICR_ORECF
LL_USART_ICR_PECF
LL_USART_ICR_RTOCF
LL_USART_ICR_TCBGTCF
LL_USART_ICR_TCCF
LL_USART_ICR_TXFECF
LL_USART_ICR_UDRCF
LL_USART_ICR_WUCF
Get Flags Defines
LL_USART_ISR_ABRF
LL_USART_ISR_BUSY
LL_USART_ISR_CMF
LL_USART_ISR_CTS
LL_USART_ISR_CTSIF
LL_USART_ISR_EOBF
LL_USART_ISR_FE
LL_USART_ISR_IDLE
LL_USART_ISR_LBDF
LL_USART_ISR_NE
LL_USART_ISR_ORE
LL_USART_ISR_PE
LL_USART_ISR_REACK
LL_USART_ISR_RTOF
LL_USART_ISR_RWU
LL_USART_ISR_RXFF
LL_USART_ISR_RXFT
LL_USART_ISR_RXNE_RXFNE
LL_USART_ISR_SBKF
LL_USART_ISR_TC
LL_USART_ISR_TCBGT
LL_USART_ISR_TEACK
LL_USART_ISR_TXE_TXFNF
LL_USART_ISR_TXFE
LL_USART_ISR_TXFT
LL_USART_ISR_UDR
LL_USART_ISR_WUF
IT Defines
LL_USART_CR1_EOBIE
LL_USART_CR1_IDLEIE
LL_USART_CR1_PEIE
LL_USART_CR1_RTOIE
LL_USART_CR1_RXFFIE
LL_USART_CR1_RXNEIE_RXFNEIE
LL_USART_CR1_TCIE
LL_USART_CR1_TXEIE_TXFNFIE
LL_USART_CR1_TXFEIE
LL_USART_CR2_LBDIE
LL_USART_CR3_CTSIE
LL_USART_CR3_EIE
LL_USART_CR3_RXFTIE
LL_USART_CR3_TCBGTIE
LL_USART_CR3_TXFTIE
LL_USART_CR3_WUFIE
FIFO Threshold
LL_USART_FIFOTHRESHOLD_1_4
LL_USART_FIFOTHRESHOLD_1_8
LL_USART_FIFOTHRESHOLD_3_4
LL_USART_FIFOTHRESHOLD_7_8
LL_USART_FIFOTHRESHOLD_8_8
Communication Direction
LL_USART_DIRECTION_RX
LL_USART_DIRECTION_TX
LL_USART_DIRECTION_TX_RX
Parity Control
LL_USART_PARITY_NONE
LL_USART_PARITY_ODD
Wakeup
LL_USART_WAKEUP_IDLELINE
Datawidth
LL_USART_DATAWIDTH_8B
LL_USART_DATAWIDTH_9B
Oversampling
LL_USART_OVERSAMPLING_8
Clock Signal
LL_USART_CLOCK_ENABLE
Last Clock Pulse
LL_USART_LASTCLKPULSE_OUTPUT
Clock Phase
LL_USART_PHASE_2EDGE
Clock Polarity
LL_USART_POLARITY_LOW
Clock Source Prescaler
LL_USART_PRESCALER_DIV10
LL_USART_PRESCALER_DIV12
LL_USART_PRESCALER_DIV128
LL_USART_PRESCALER_DIV16
LL_USART_PRESCALER_DIV2
LL_USART_PRESCALER_DIV256
LL_USART_PRESCALER_DIV32
LL_USART_PRESCALER_DIV4
LL_USART_PRESCALER_DIV6
LL_USART_PRESCALER_DIV64
LL_USART_PRESCALER_DIV8
Stop Bits
LL_USART_STOPBITS_1
LL_USART_STOPBITS_1_5
LL_USART_STOPBITS_2
TX RX Pins Swap
LL_USART_TXRX_SWAPPED
RX Pin Active Level Inversion
LL_USART_RXPIN_LEVEL_STANDARD
TX Pin Active Level Inversion
LL_USART_TXPIN_LEVEL_STANDARD
Binary Data Inversion
LL_USART_BINARY_LOGIC_POSITIVE
Bit Order
LL_USART_BITORDER_MSBFIRST
Autobaud Detection
LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
Address Length Detection
LL_USART_ADDRESS_DETECT_7B
Hardware Control
LL_USART_HWCONTROL_NONE
LL_USART_HWCONTROL_RTS
LL_USART_HWCONTROL_RTS_CTS
Wakeup Activation
LL_USART_WAKEUP_ON_RXNE
LL_USART_WAKEUP_ON_STARTBIT
IrDA Power
LL_USART_IRDA_POWER_NORMAL
LIN Break Detection Length
LL_USART_LINBREAK_DETECT_11B
Driver Enable Polarity
LL_USART_DE_POLARITY_LOW
DMA Register Data
LL_USART_DMA_REG_DATA_TRANSMIT
USART Exported Macros
LL_USART_WriteReg
Exported_Macros_Helper
__LL_USART_DIV_SAMPLING8
USART Exported Functions
LL_USART_ConfigClock
LL_USART_ConfigFIFOsThreshold
LL_USART_ConfigNodeAddress
LL_USART_Disable
LL_USART_DisableAutoBaudRate
LL_USART_DisableCTSHWFlowCtrl
LL_USART_DisableDirectionRx
LL_USART_DisableDirectionTx
LL_USART_DisableFIFO
LL_USART_DisableInStopMode
LL_USART_DisableMuteMode
LL_USART_DisableOneBitSamp
LL_USART_DisableOverrunDetect
LL_USART_DisableRTSHWFlowCtrl
LL_USART_DisableRxTimeout
LL_USART_DisableSCLKOutput
LL_USART_Enable
LL_USART_EnableAutoBaudRate
LL_USART_EnableCTSHWFlowCtrl
LL_USART_EnableDirectionRx
LL_USART_EnableDirectionTx
LL_USART_EnableFIFO
LL_USART_EnableInStopMode
LL_USART_EnableMuteMode
LL_USART_EnableOneBitSamp
LL_USART_EnableOverrunDetect
LL_USART_EnableRTSHWFlowCtrl
LL_USART_EnableRxTimeout
LL_USART_EnableSCLKOutput
LL_USART_GetAutoBaudRateMode
LL_USART_GetBaudRate
LL_USART_GetBinaryDataLogic
LL_USART_GetBlockLength
LL_USART_GetClockPhase
LL_USART_GetClockPolarity
LL_USART_GetDataWidth
LL_USART_GetHWFlowCtrl
LL_USART_GetLastClkPulseOutput
LL_USART_GetNodeAddress
LL_USART_GetNodeAddressLen
LL_USART_GetOverSampling
LL_USART_GetParity
LL_USART_GetPrescaler
LL_USART_GetRXFIFOThreshold
LL_USART_GetRXPinLevel
LL_USART_GetRxTimeout
LL_USART_GetStopBitsLength
LL_USART_GetTransferBitOrder
LL_USART_GetTransferDirection
LL_USART_GetTXFIFOThreshold
LL_USART_GetTXPinLevel
LL_USART_GetTXRXSwap
LL_USART_GetWakeUpMethod
LL_USART_GetWKUPType
LL_USART_IsEnabled
LL_USART_IsEnabledAutoBaud
LL_USART_IsEnabledFIFO
LL_USART_IsEnabledInStopMode
LL_USART_IsEnabledMuteMode
LL_USART_IsEnabledOneBitSamp
LL_USART_IsEnabledOverrunDetect
LL_USART_IsEnabledRxTimeout
LL_USART_IsEnabledSCLKOutput
LL_USART_SetAutoBaudRateMode
LL_USART_SetBaudRate
LL_USART_SetBinaryDataLogic
LL_USART_SetBlockLength
LL_USART_SetClockPhase
LL_USART_SetClockPolarity
LL_USART_SetDataWidth
LL_USART_SetHWFlowCtrl
LL_USART_SetLastClkPulseOutput
LL_USART_SetOverSampling
LL_USART_SetParity
LL_USART_SetPrescaler
LL_USART_SetRXFIFOThreshold
LL_USART_SetRXPinLevel
LL_USART_SetRxTimeout
LL_USART_SetStopBitsLength
LL_USART_SetTransferBitOrder
LL_USART_SetTransferDirection
LL_USART_SetTXFIFOThreshold
LL_USART_SetTXPinLevel
LL_USART_SetTXRXSwap
LL_USART_SetWakeUpMethod
LL_USART_SetWKUPType
Configuration functions related to Irda feature
LL_USART_EnableIrda
LL_USART_GetIrdaPowerMode
LL_USART_GetIrdaPrescaler
LL_USART_IsEnabledIrda
LL_USART_SetIrdaPowerMode
LL_USART_SetIrdaPrescaler
Configuration functions related to Smartcard feature
LL_USART_DisableSmartcardNACK
LL_USART_EnableSmartcard
LL_USART_EnableSmartcardNACK
LL_USART_GetSmartcardAutoRetryCount
LL_USART_GetSmartcardGuardTime
LL_USART_GetSmartcardPrescaler
LL_USART_IsEnabledSmartcard
LL_USART_IsEnabledSmartcardNACK
LL_USART_SetSmartcardAutoRetryCount
LL_USART_SetSmartcardGuardTime
LL_USART_SetSmartcardPrescaler
Configuration functions related to Half Duplex feature
LL_USART_EnableHalfDuplex
LL_USART_IsEnabledHalfDuplex
Configuration functions related to SPI Slave feature
LL_USART_DisableSPISlaveSelect
LL_USART_EnableSPISlave
LL_USART_EnableSPISlaveSelect
LL_USART_IsEnabledSPISlave
LL_USART_IsEnabledSPISlaveSelect
Configuration functions related to LIN feature
LL_USART_EnableLIN
LL_USART_GetLINBrkDetectionLen
LL_USART_IsEnabledLIN
LL_USART_SetLINBrkDetectionLen
Configuration functions related to Driver Enable feature
LL_USART_EnableDEMode
LL_USART_GetDEAssertionTime
LL_USART_GetDEDeassertionTime
LL_USART_GetDESignalPolarity
LL_USART_IsEnabledDEMode
LL_USART_SetDEAssertionTime
LL_USART_SetDEDeassertionTime
LL_USART_SetDESignalPolarity
Advanced Configurations services
LL_USART_ConfigHalfDuplexMode
LL_USART_ConfigIrdaMode
LL_USART_ConfigLINMode
LL_USART_ConfigMultiProcessMode
LL_USART_ConfigSmartcardMode
LL_USART_ConfigSyncMode
FLAG_Management
LL_USART_IsActiveFlag_TXE
Functions
LL_USART_ClearFlag_EOB
LL_USART_ClearFlag_FE
LL_USART_ClearFlag_IDLE
LL_USART_ClearFlag_LBD
LL_USART_ClearFlag_nCTS
LL_USART_ClearFlag_NE
LL_USART_ClearFlag_ORE
LL_USART_ClearFlag_PE
LL_USART_ClearFlag_RTO
LL_USART_ClearFlag_TC
LL_USART_ClearFlag_TCBGT
LL_USART_ClearFlag_TXFE
LL_USART_ClearFlag_UDR
LL_USART_ClearFlag_WKUP
LL_USART_IsActiveFlag_ABR
LL_USART_IsActiveFlag_ABRE
LL_USART_IsActiveFlag_BUSY
LL_USART_IsActiveFlag_CM
LL_USART_IsActiveFlag_CTS
LL_USART_IsActiveFlag_EOB
LL_USART_IsActiveFlag_FE
LL_USART_IsActiveFlag_IDLE
LL_USART_IsActiveFlag_LBD
LL_USART_IsActiveFlag_nCTS
LL_USART_IsActiveFlag_NE
LL_USART_IsActiveFlag_ORE
LL_USART_IsActiveFlag_PE
LL_USART_IsActiveFlag_REACK
LL_USART_IsActiveFlag_RTO
LL_USART_IsActiveFlag_RWU
LL_USART_IsActiveFlag_RXFF
LL_USART_IsActiveFlag_RXFT
LL_USART_IsActiveFlag_RXNE_RXFNE
LL_USART_IsActiveFlag_SBK
LL_USART_IsActiveFlag_TC
LL_USART_IsActiveFlag_TCBGT
LL_USART_IsActiveFlag_TEACK
LL_USART_IsActiveFlag_TXE_TXFNF
LL_USART_IsActiveFlag_TXFE
LL_USART_IsActiveFlag_TXFT
LL_USART_IsActiveFlag_UDR
LL_USART_IsActiveFlag_WKUP
IT_Management
LL_USART_DisableIT_TXE
LL_USART_EnableIT_RXNE
LL_USART_EnableIT_TXE
LL_USART_IsEnabledIT_RXNE
LL_USART_IsEnabledIT_TXE
Functions
LL_USART_DisableIT_CTS
LL_USART_DisableIT_EOB
LL_USART_DisableIT_ERROR
LL_USART_DisableIT_IDLE
LL_USART_DisableIT_LBD
LL_USART_DisableIT_PE
LL_USART_DisableIT_RTO
LL_USART_DisableIT_RXFF
LL_USART_DisableIT_RXFT
LL_USART_DisableIT_RXNE_RXFNE
LL_USART_DisableIT_TC
LL_USART_DisableIT_TCBGT
LL_USART_DisableIT_TXE_TXFNF
LL_USART_DisableIT_TXFE
LL_USART_DisableIT_TXFT
LL_USART_DisableIT_WKUP
LL_USART_EnableIT_CM
LL_USART_EnableIT_CTS
LL_USART_EnableIT_EOB
LL_USART_EnableIT_ERROR
LL_USART_EnableIT_IDLE
LL_USART_EnableIT_LBD
LL_USART_EnableIT_PE
LL_USART_EnableIT_RTO
LL_USART_EnableIT_RXFF
LL_USART_EnableIT_RXFT
LL_USART_EnableIT_RXNE_RXFNE
LL_USART_EnableIT_TC
LL_USART_EnableIT_TCBGT
LL_USART_EnableIT_TXE_TXFNF
LL_USART_EnableIT_TXFE
LL_USART_EnableIT_TXFT
LL_USART_EnableIT_WKUP
LL_USART_IsEnabledIT_CM
LL_USART_IsEnabledIT_CTS
LL_USART_IsEnabledIT_EOB
LL_USART_IsEnabledIT_ERROR
LL_USART_IsEnabledIT_IDLE
LL_USART_IsEnabledIT_LBD
LL_USART_IsEnabledIT_PE
LL_USART_IsEnabledIT_RTO
LL_USART_IsEnabledIT_RXFF
LL_USART_IsEnabledIT_RXFT
LL_USART_IsEnabledIT_RXNE_RXFNE
LL_USART_IsEnabledIT_TC
LL_USART_IsEnabledIT_TCBGT
LL_USART_IsEnabledIT_TXE_TXFNF
LL_USART_IsEnabledIT_TXFE
LL_USART_IsEnabledIT_TXFT
LL_USART_IsEnabledIT_WKUP
DMA_Management
LL_USART_DisableDMAReq_RX
LL_USART_DisableDMAReq_TX
LL_USART_DMA_GetRegAddr
LL_USART_EnableDMADeactOnRxErr
LL_USART_EnableDMAReq_RX
LL_USART_EnableDMAReq_TX
LL_USART_IsEnabledDMADeactOnRxErr
LL_USART_IsEnabledDMAReq_RX
LL_USART_IsEnabledDMAReq_TX
Data_Management
LL_USART_ReceiveData9
LL_USART_TransmitData8
LL_USART_TransmitData9
Execution
LL_USART_RequestBreakSending
LL_USART_RequestEnterMuteMode
LL_USART_RequestRxDataFlush
LL_USART_RequestTxDataFlush
Initialization and de-initialization functions
LL_USART_ClockStructInit
LL_USART_DeInit
LL_USART_Init
LL_USART_StructInit
UTILS
UTILS_GetPLLOutputFrequency
UTILS_PLL_IsBusy
UTILS Private Constants
LL_MAX_DELAY
PACKAGE_BASE_ADDRESS
UID_BASE_ADDRESS
UTILS_HSE_FREQUENCY_MAX
UTILS_HSE_FREQUENCY_MIN
UTILS_MAX_FREQUENCY_SCALE1
UTILS_MAX_FREQUENCY_SCALE2
UTILS_PLLVCO_INPUT_MAX
UTILS_PLLVCO_INPUT_MIN
UTILS_PLLVCO_OUTPUT_MAX
UTILS_PLLVCO_OUTPUT_MIN
UTILS_SCALE1_LATENCY1_BOOST_FREQ
UTILS_SCALE1_LATENCY1_FREQ
UTILS_SCALE1_LATENCY2_BOOST_FREQ
UTILS_SCALE1_LATENCY2_FREQ
UTILS_SCALE1_LATENCY3_BOOST_FREQ
UTILS_SCALE1_LATENCY3_FREQ
UTILS_SCALE1_LATENCY4_BOOST_FREQ
UTILS_SCALE1_LATENCY4_FREQ
UTILS_SCALE1_LATENCY5_BOOST_FREQ
UTILS_SCALE1_LATENCY5_FREQ
UTILS_SCALE2_LATENCY1_FREQ
UTILS_SCALE2_LATENCY2_FREQ
UTILS_SCALE2_LATENCY3_FREQ
UTILS Private Macros
IS_LL_UTILS_APB2_DIV
IS_LL_UTILS_HSE_BYPASS
IS_LL_UTILS_HSE_FREQUENCY
IS_LL_UTILS_PLL_FREQUENCY
IS_LL_UTILS_PLLM_VALUE
IS_LL_UTILS_PLLN_VALUE
IS_LL_UTILS_PLLR_VALUE
IS_LL_UTILS_PLLVCO_INPUT
IS_LL_UTILS_PLLVCO_OUTPUT
IS_LL_UTILS_SYSCLK_DIV
UTILS Exported structures
LL_UTILS_ClkInitTypeDef
UTILS Exported Constants
LL_UTILS_HSEBYPASS_ON
PACKAGE TYPE
LL_UTILS_PACKAGETYPE_LQFP100_LQFP80
LL_UTILS_PACKAGETYPE_LQFP128
LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121
LL_UTILS_PACKAGETYPE_LQFP32
LL_UTILS_PACKAGETYPE_LQFP48
LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
LL_UTILS_PACKAGETYPE_LQFP64
LL_UTILS_PACKAGETYPE_TFBGA100
LL_UTILS_PACKAGETYPE_UFBGA100
LL_UTILS_PACKAGETYPE_UFBGA64
LL_UTILS_PACKAGETYPE_UFQFPN32
LL_UTILS_PACKAGETYPE_UFQFPN48
LL_UTILS_PACKAGETYPE_WLCSP49
LL_UTILS_PACKAGETYPE_WLCSP64
LL_UTILS_PACKAGETYPE_WLCSP81
UTILS Exported Functions
LL_GetPackageType
LL_GetUID_Word0
LL_GetUID_Word1
LL_GetUID_Word2
DELAY
LL_InitTick
LL_mDelay
SYSTEM
LL_PLL_ConfigSystemClock_HSI
LL_SetFlashLatency
LL_SetSystemCoreClock
WWDG
PRESCALER
LL_WWDG_PRESCALER_128
LL_WWDG_PRESCALER_16
LL_WWDG_PRESCALER_2
LL_WWDG_PRESCALER_32
LL_WWDG_PRESCALER_4
LL_WWDG_PRESCALER_64
LL_WWDG_PRESCALER_8
WWDG Exported Macros
LL_WWDG_WriteReg
WWDG Exported Functions
LL_WWDG_GetCounter
LL_WWDG_GetPrescaler
LL_WWDG_GetWindow
LL_WWDG_IsEnabled
LL_WWDG_SetCounter
LL_WWDG_SetPrescaler
LL_WWDG_SetWindow
FLAG_Management
LL_WWDG_IsActiveFlag_EWKUP
IT_Management
LL_WWDG_IsEnabledIT_EWKUP
Data Structures
ConvHalfCpltCallback
DMA_Handle
EndOfSamplingCallback
ErrorCallback
ErrorCode
Init
InjectedConvCpltCallback
InjectedQueueOverflowCallback
InjectionConfig
Instance
LevelOutOfWindow2Callback
LevelOutOfWindow3Callback
LevelOutOfWindowCallback
Lock
MspDeInitCallback
MspInitCallback
State
__COMP_HandleTypeDef
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
State
TriggerCallback
__CORDIC_HandleTypeDef
DMADirection
ErrorCallback
ErrorCode
hdmaIn
hdmaOut
Instance
Lock
MspDeInitCallback
MspInitCallback
NbCalcToGet
NbCalcToOrder
pInBuff
pOutBuff
State
__DAC_HandleTypeDef
ConvCpltCallbackCh2
ConvHalfCpltCallbackCh1
ConvHalfCpltCallbackCh2
DMA_Handle1
DMA_Handle2
DMAUnderrunCallbackCh1
DMAUnderrunCallbackCh2
ErrorCallbackCh1
ErrorCallbackCh2
ErrorCode
Instance
Lock
MspDeInitCallback
MspInitCallback
State
__DMA_HandleTypeDef
DmaBaseAddress
DMAmuxChannel
DMAmuxChannelStatus
DMAmuxChannelStatusMask
DMAmuxRequestGen
DMAmuxRequestGenStatus
DMAmuxRequestGenStatusMask
ErrorCode
Init
Instance
Lock
Parent
State
XferAbortCallback
XferCpltCallback
XferErrorCallback
XferHalfCpltCallback
__FDCAN_HandleTypeDef
ErrorCode
ErrorStatusCallback
HighPriorityMessageCallback
Init
Instance
LatestTxFifoQRequest
Lock
msgRam
MspDeInitCallback
MspInitCallback
RxFifo0Callback
RxFifo1Callback
State
TimeoutOccurredCallback
TimestampWraparoundCallback
TxBufferAbortCallback
TxBufferCompleteCallback
TxEventFifoCallback
TxFifoEmptyCallback
__FMAC_HandleTypeDef
ErrorCode
FilterConfigCallback
FilterParam
FilterPreloadCallback
GetDataCallback
HalfGetDataCallback
HalfOutputDataReadyCallback
hdmaIn
hdmaOut
hdmaPreload
InputAccess
InputCurrentSize
Instance
Lock
MspDeInitCallback
MspInitCallback
OutputAccess
OutputCurrentSize
OutputDataReadyCallback
pInput
pInputSize
pOutput
pOutputSize
RdState
State
WrState
__HRTIM_HandleTypeDef
BurstModePeriodCallback
Capture1EventCallback
Capture2EventCallback
Compare1EventCallback
Compare2EventCallback
Compare3EventCallback
Compare4EventCallback
CounterResetCallback
DelayedProtectionCallback
DLLCalibrationReadyCallback
ErrorCallback
Fault1Callback
Fault2Callback
Fault3Callback
Fault4Callback
Fault5Callback
Fault6Callback
hdmaMaster
hdmaTimerA
hdmaTimerB
hdmaTimerC
hdmaTimerD
hdmaTimerE
hdmaTimerF
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
Output1ResetCallback
Output1SetCallback
Output2ResetCallback
Output2SetCallback
RegistersUpdateCallback
RepetitionEventCallback
State
SynchronizationEventCallback
SystemFaultCallback
TimerParam
__I2C_HandleTypeDef
AddrCallback
AddrEventCount
Devaddress
ErrorCallback
ErrorCode
hdmarx
hdmatx
Init
Instance
ListenCpltCallback
Lock
MasterRxCpltCallback
MasterTxCpltCallback
Memaddress
MemRxCpltCallback
MemTxCpltCallback
Mode
MspDeInitCallback
MspInitCallback
pBuffPtr
PreviousState
SlaveRxCpltCallback
SlaveTxCpltCallback
State
XferCount
XferISR
XferOptions
XferSize
__I2S_HandleTypeDef
ErrorCode
hdmarx
hdmatx
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxHalfCpltCallback
RxXferCount
RxXferSize
State
TxCpltCallback
TxHalfCpltCallback
TxXferCount
TxXferSize
__IRDA_HandleTypeDef
AbortReceiveCpltCallback
AbortTransmitCpltCallback
ErrorCallback
ErrorCode
gState
hdmarx
hdmatx
Init
Instance
Lock
Mask
MspDeInitCallback
MspInitCallback
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxHalfCpltCallback
RxState
RxXferCount
RxXferSize
TxCpltCallback
TxHalfCpltCallback
TxXferCount
TxXferSize
__LPTIM_HandleTypeDef
AutoReloadWriteCallback
CompareMatchCallback
CompareWriteCallback
DirectionDownCallback
DirectionUpCallback
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
State
Status
TriggerCallback
__OPAMP_HandleTypeDef
Instance
Lock
MspDeInitCallback
MspInitCallback
State
Status
__PCD_HandleTypeDef
BCDCallback
BESL
ConnectCallback
DataInStageCallback
DataOutStageCallback
DisconnectCallback
ErrorCode
IN_ep
Init
Instance
ISOINIncompleteCallback
ISOOUTIncompleteCallback
Lock
lpm_active
LPM_State
LPMCallback
MspDeInitCallback
MspInitCallback
OUT_ep
pData
ResetCallback
ResumeCallback
Setup
SetupStageCallback
SOFCallback
State
SuspendCallback
USB_Address
__QSPI_HandleTypeDef
CmdCpltCallback
ErrorCallback
ErrorCode
FifoThresholdCallback
hdma
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxHalfCpltCallback
RxXferCount
RxXferSize
State
StatusMatchCallback
Timeout
TimeOutCallback
TxCpltCallback
TxHalfCpltCallback
TxXferCount
TxXferSize
__RNG_HandleTypeDef
ErrorCode
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
RandomNumber
ReadyDataCallback
State
__RTC_HandleTypeDef
AlarmBEventCallback
Init
Instance
InternalTamper1EventCallback
InternalTamper3EventCallback
InternalTamper4EventCallback
InternalTamper5EventCallback
InternalTamper6EventCallback
Lock
MspDeInitCallback
MspInitCallback
State
Tamper1EventCallback
Tamper2EventCallback
Tamper3EventCallback
TimeStampEventCallback
WakeUpTimerEventCallback
__SAI_HandleTypeDef
ErrorCode
FrameInit
hdmarx
hdmatx
Init
Instance
InterruptServiceRoutine
Lock
MspDeInitCallback
MspInitCallback
mutecallback
pBuffPtr
RxCpltCallback
RxHalfCpltCallback
SlotInit
State
TxCpltCallback
TxHalfCpltCallback
XferCount
XferSize
__SMARTCARD_HandleTypeDef
AbortReceiveCpltCallback
AbortTransmitCpltCallback
AdvancedInit
ErrorCallback
ErrorCode
FifoMode
gState
hdmarx
hdmatx
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
NbRxDataToProcess
NbTxDataToProcess
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxFifoFullCallback
RxISR
RxState
RxXferCount
RxXferSize
TxCpltCallback
TxFifoEmptyCallback
TxISR
TxXferCount
TxXferSize
__SMBUS_HandleTypeDef
ErrorCallback
ErrorCode
Init
Instance
ListenCpltCallback
Lock
MasterRxCpltCallback
MasterTxCpltCallback
MspDeInitCallback
MspInitCallback
pBuffPtr
PreviousState
SlaveRxCpltCallback
SlaveTxCpltCallback
State
XferCount
XferOptions
XferSize
__SPI_HandleTypeDef
CRCSize
ErrorCallback
ErrorCode
hdmarx
hdmatx
Init
Instance
Lock
MspDeInitCallback
MspInitCallback
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxHalfCpltCallback
RxISR
RxXferCount
RxXferSize
State
TxCpltCallback
TxHalfCpltCallback
TxISR
TxRxCpltCallback
TxRxHalfCpltCallback
TxXferCount
TxXferSize
__TIM_HandleTypeDef
Base_MspInitCallback
Break2Callback
BreakCallback
Channel
ChannelNState
ChannelState
CommutationCallback
CommutationHalfCpltCallback
DirectionChangeCallback
DMABurstState
Encoder_MspDeInitCallback
Encoder_MspInitCallback
EncoderIndexCallback
ErrorCallback
HallSensor_MspDeInitCallback
HallSensor_MspInitCallback
hdma
IC_CaptureCallback
IC_CaptureHalfCpltCallback
IC_MspDeInitCallback
IC_MspInitCallback
IndexErrorCallback
Init
Instance
Lock
OC_DelayElapsedCallback
OC_MspDeInitCallback
OC_MspInitCallback
OnePulse_MspDeInitCallback
OnePulse_MspInitCallback
PeriodElapsedCallback
PeriodElapsedHalfCpltCallback
PWM_MspDeInitCallback
PWM_MspInitCallback
PWM_PulseFinishedCallback
PWM_PulseFinishedHalfCpltCallback
State
TransitionErrorCallback
TriggerCallback
TriggerHalfCpltCallback
__UART_HandleTypeDef
AbortReceiveCpltCallback
AbortTransmitCpltCallback
AdvancedInit
ErrorCallback
ErrorCode
FifoMode
gState
hdmarx
hdmatx
Init
Instance
Lock
Mask
MspDeInitCallback
MspInitCallback
NbRxDataToProcess
NbTxDataToProcess
pRxBuffPtr
pTxBuffPtr
ReceptionType
RxCpltCallback
RxEventCallback
RxEventType
RxFifoFullCallback
RxHalfCpltCallback
RxISR
RxState
RxXferCount
RxXferSize
TxCpltCallback
TxFifoEmptyCallback
TxHalfCpltCallback
TxISR
TxXferCount
TxXferSize
WakeupCallback
__USART_HandleTypeDef
ErrorCallback
ErrorCode
FifoMode
hdmarx
hdmatx
Init
Instance
Lock
Mask
MspDeInitCallback
MspInitCallback
NbRxDataToProcess
NbTxDataToProcess
pRxBuffPtr
pTxBuffPtr
RxCpltCallback
RxFifoFullCallback
RxHalfCpltCallback
RxISR
RxXferCount
RxXferSize
SlaveMode
State
TxCpltCallback
TxFifoEmptyCallback
TxHalfCpltCallback
TxISR
TxRxCpltCallback
TxXferCount
TxXferSize
__WWDG_HandleTypeDef
Init
Instance
MspInitCallback
ADC_AnalogWDGConfTypeDef
FilteringConfig
HighThreshold
ITMode
LowThreshold
WatchdogMode
WatchdogNumber
ADC_ChannelConfTypeDef
Offset
OffsetNumber
OffsetSaturation
OffsetSign
Rank
SamplingTime
SingleDiff
ADC_InitTypeDef
ContinuousConvMode
DataAlign
DiscontinuousConvMode
DMAContinuousRequests
EOCSelection
ExternalTrigConv
ExternalTrigConvEdge
GainCompensation
LowPowerAutoWait
NbrOfConversion
NbrOfDiscConversion
Overrun
Oversampling
OversamplingMode
Resolution
SamplingMode
ScanConvMode
ADC_InjectionConfigTypeDef
ContextQueue
ADC_InjectionConfTypeDef
ExternalTrigInjecConv
ExternalTrigInjecConvEdge
InjecOversampling
InjecOversamplingMode
InjectedChannel
InjectedDiscontinuousConvMode
InjectedNbrOfConversion
InjectedOffset
InjectedOffsetNumber
InjectedOffsetSaturation
InjectedOffsetSign
InjectedRank
InjectedSamplingTime
InjectedSingleDiff
QueueInjectedContext
ADC_InjOversamplingTypeDef
RightBitShift
ADC_MultiModeTypeDef
Mode
TwoSamplingDelay
ADC_OversamplingTypeDef
Ratio
RightBitShift
TriggeredMode
COMP_InitTypeDef
Hysteresis
InputMinus
InputPlus
OutputPol
TriggerMode
CORDIC_ConfigTypeDef
InSize
NbRead
NbWrite
OutSize
Precision
Scale
CRC_HandleTypeDef
InputDataFormat
Instance
Lock
State
CRC_InitTypeDef
DefaultInitValueUse
DefaultPolynomialUse
GeneratingPolynomial
InitValue
InputDataInversionMode
OutputDataInversionMode
DAC_ChannelConfTypeDef
DAC_DMADoubleDataMode
DAC_HighFrequency
DAC_OutputBuffer
DAC_SampleAndHold
DAC_SampleAndHoldConfig
DAC_SignedFormat
DAC_Trigger
DAC_Trigger2
DAC_TrimmingValue
DAC_UserTrimming
DAC_SampleAndHoldConfTypeDef
DAC_RefreshTime
DAC_SampleTime
DMA_InitTypeDef
MemDataAlignment
MemInc
Mode
PeriphDataAlignment
PeriphInc
Priority
Request
EXTI_ConfigTypeDef
Line
Mode
Trigger
EXTI_HandleTypeDef
PendingCallback
FDCAN_ErrorCountersTypeDef
RxErrorCnt
RxErrorPassive
TxErrorCnt
FDCAN_FilterTypeDef
FilterID1
FilterID2
FilterIndex
FilterType
IdType
FDCAN_HpMsgStatusTypeDef
FilterList
MessageIndex
MessageStorage
FDCAN_InitTypeDef
ClockDivider
DataPrescaler
DataSyncJumpWidth
DataTimeSeg1
DataTimeSeg2
ExtFiltersNbr
FrameFormat
Mode
NominalPrescaler
NominalSyncJumpWidth
NominalTimeSeg1
NominalTimeSeg2
ProtocolException
StdFiltersNbr
TransmitPause
TxFifoQueueMode
FDCAN_MsgRamAddressTypeDef
RxFIFO0SA
RxFIFO1SA
StandardFilterSA
TxEventFIFOSA
TxFIFOQSA
FDCAN_ProtocolStatusTypeDef
BusOff
DataLastErrorCode
ErrorPassive
LastErrorCode
ProtocolException
RxBRSflag
RxESIflag
RxFDFflag
TDCvalue
Warning
FDCAN_RxHeaderTypeDef
DataLength
ErrorStateIndicator
FDFormat
FilterIndex
Identifier
IdType
IsFilterMatchingFrame
RxFrameType
RxTimestamp
FDCAN_TxEventFifoTypeDef
DataLength
ErrorStateIndicator
EventType
FDFormat
Identifier
IdType
MessageMarker
TxFrameType
TxTimestamp
FDCAN_TxHeaderTypeDef
DataLength
ErrorStateIndicator
FDFormat
Identifier
IdType
MessageMarker
TxEventFifoControl
TxFrameType
FLASH_EraseInitTypeDef
NbPages
Page
TypeErase
FLASH_OBProgramInitTypeDef
OptionType
PCROPConfig
PCROPEndAddr
PCROPStartAddr
RDPLevel
SecBank
SecSize
USERConfig
USERType
WRPArea
WRPEndOffset
WRPStartOffset
FLASH_ProcessTypeDef
Bank
CacheToReactivate
ErrorCode
Lock
NbPagesToErase
Page
ProcedureOnGoing
FMAC_FilterConfigTypeDef
CoeffASize
CoeffBaseAddress
CoeffBSize
CoeffBufferSize
Filter
InputAccess
InputBaseAddress
InputBufferSize
InputThreshold
OutputAccess
OutputBaseAddress
OutputBufferSize
OutputThreshold
P
pCoeffA
pCoeffB
Q
R
GPIO_InitTypeDef
Mode
Pin
Pull
Speed
HAL_DMA_MuxRequestGeneratorConfigTypeDef
RequestNumber
SignalID
HAL_DMA_MuxSyncConfigTypeDef
RequestNumber
SyncEnable
SyncPolarity
SyncSignalID
HRTIM_ADCTriggerCfgTypeDef
UpdateSource
HRTIM_BurstModeCfgTypeDef
IdleDuration
Mode
Period
PreloadEnable
Prescaler
Trigger
HRTIM_CaptureCfgTypeDef
HRTIM_CaptureValueTypeDef
Value
HRTIM_ChopperModeCfgTypeDef
DutyCycle
StartPulse
HRTIM_CompareCfgTypeDef
AutoDelayedTimeout
CompareValue
HRTIM_DeadTimeCfgTypeDef
FallingSign
FallingSignLock
FallingValue
Prescaler
RisingLock
RisingSign
RisingSignLock
RisingValue
HRTIM_EventCfgTypeDef
Filter
Polarity
Sensitivity
Source
HRTIM_ExternalEventCfgTypeDef
ResetMode
Source
HRTIM_FaultBlankingCfgTypeDef
ResetMode
Threshold
HRTIM_FaultCfgTypeDef
Lock
Polarity
Source
HRTIM_InitTypeDef
SyncInputSource
SyncOptions
SyncOutputPolarity
SyncOutputSource
HRTIM_OutputCfgTypeDef
ChopperModeEnable
FaultLevel
IdleLevel
IdleMode
Polarity
ResetSource
SetSource
HRTIM_SimpleCaptureChannelCfgTypeDef
EventFilter
EventPolarity
EventSensitivity
HRTIM_SimpleOCChannelCfgTypeDef
Mode
Polarity
Pulse
HRTIM_SimpleOnePulseChannelCfgTypeDef
EventFilter
EventPolarity
EventSensitivity
OutputIdleLevel
OutputPolarity
Pulse
HRTIM_SimplePWMChannelCfgTypeDef
Polarity
Pulse
HRTIM_TimeBaseCfgTypeDef
Period
PrescalerRatio
RepetitionCounter
HRTIM_TimerCfgTypeDef
BurstMode
DACSynchro
DeadTimeInsertion
DelayedProtectionMode
DMADstAddress
DMARequests
DMASize
DMASrcAddress
FaultEnable
FaultLock
HalfModeEnable
InterleavedMode
InterruptRequests
PreloadEnable
PushPull
RepetitionUpdate
ResetOnSync
ResetTrigger
ResetUpdate
ReSyncUpdate
StartOnSync
UpdateGating
UpdateTrigger
HRTIM_TimerCtlTypeDef
DualChannelDacReset
DualChannelDacStep
GreaterCMP1
GreaterCMP3
TrigHalf
UpDownMode
HRTIM_TimerEventFilteringCfgTypeDef
Latch
HRTIM_TimerParamTypeDef
CaptureTrigger2
DMADstAddress
DMARequests
DMASize
DMASrcAddress
InterruptRequests
I2C_InitTypeDef
DualAddressMode
GeneralCallMode
NoStretchMode
OwnAddress1
OwnAddress2
OwnAddress2Masks
Timing
I2S_InitTypeDef
CPOL
DataFormat
MCLKOutput
Mode
Standard
IRDA_InitTypeDef
ClockPrescaler
Mode
Parity
PowerMode
Prescaler
WordLength
IWDG_HandleTypeDef
Instance
IWDG_InitTypeDef
Reload
Window
LL_ADC_CommonInitTypeDef
MultiDMATransfer
Multimode
MultiTwoSamplingDelay
LL_ADC_InitTypeDef
LowPowerMode
Resolution
LL_ADC_INJ_InitTypeDef
SequencerLength
TrigAuto
TriggerSource
LL_ADC_REG_InitTypeDef
DMATransfer
Overrun
SequencerDiscont
SequencerLength
TriggerSource
LL_COMP_InitTypeDef
InputMinus
InputPlus
OutputBlankingSource
OutputPolarity
LL_DAC_InitTypeDef
OutputConnection
OutputMode
TriggerSource
TriggerSource2
WaveAutoGeneration
WaveAutoGenerationConfig
LL_DMA_InitTypeDef
MemoryOrM2MDstAddress
MemoryOrM2MDstDataSize
MemoryOrM2MDstIncMode
Mode
NbData
PeriphOrM2MSrcAddress
PeriphOrM2MSrcDataSize
PeriphOrM2MSrcIncMode
PeriphRequest
Priority
LL_EXTI_InitTypeDef
Line_32_63
LineCommand
Mode
Trigger
LL_GPIO_InitTypeDef
Mode
OutputType
Pin
Pull
Speed
LL_I2C_InitTypeDef
DigitalFilter
OwnAddress1
OwnAddrSize
PeripheralMode
Timing
TypeAcknowledge
LL_I2S_InitTypeDef
ClockPolarity
DataFormat
MCLKOutput
Mode
Standard
LL_LPTIM_InitTypeDef
Polarity
Prescaler
Waveform
LL_LPUART_InitTypeDef
DataWidth
HardwareFlowControl
Parity
PrescalerValue
StopBits
TransferDirection
LL_OPAMP_InitTypeDef
InputInverting
InputNonInverting
PowerMode
LL_RCC_ClocksTypeDef
PCLK1_Frequency
PCLK2_Frequency
SYSCLK_Frequency
LL_RNG_InitTypeDef
LL_RTC_AlarmTypeDef
AlarmDateWeekDaySel
AlarmMask
AlarmTime
LL_RTC_DateTypeDef
Month
WeekDay
Year
LL_RTC_InitTypeDef
HourFormat
SynchPrescaler
LL_RTC_TimeTypeDef
Minutes
Seconds
TimeFormat
LL_SPI_InitTypeDef
BitOrder
ClockPhase
ClockPolarity
CRCCalculation
CRCPoly
DataWidth
Mode
NSS
TransferDirection
LL_TIM_BDTR_InitTypeDef
Break2AFMode
Break2Filter
Break2Polarity
Break2State
BreakAFMode
BreakFilter
BreakPolarity
BreakState
DeadTime
LockLevel
OSSIState
OSSRState
LL_TIM_ENCODER_InitTypeDef
IC1ActiveInput
IC1Filter
IC1Polarity
IC1Prescaler
IC2ActiveInput
IC2Filter
IC2Polarity
IC2Prescaler
LL_TIM_HALLSENSOR_InitTypeDef
IC1Filter
IC1Polarity
IC1Prescaler
LL_TIM_IC_InitTypeDef
ICFilter
ICPolarity
ICPrescaler
LL_TIM_InitTypeDef
ClockDivision
CounterMode
Prescaler
RepetitionCounter
LL_TIM_OC_InitTypeDef
OCIdleState
OCMode
OCNIdleState
OCNPolarity
OCNState
OCPolarity
OCState
LL_UCPD_InitTypeDef
IfrGap
psc_ucpdclk
transwin
LL_USART_ClockInitTypeDef
ClockPhase
ClockPolarity
LastBitClockPulse
LL_USART_InitTypeDef
DataWidth
HardwareFlowControl
OverSampling
Parity
PrescalerValue
StopBits
TransferDirection
LL_UTILS_ClkInitTypeDef
APB1CLKDivider
APB2CLKDivider
LL_UTILS_PLLInitTypeDef
PLLN
PLLR
LPTIM_ClockConfigTypeDef
Source
LPTIM_InitTypeDef
CounterSource
Input1Source
Input2Source
OutputPolarity
Trigger
UltraLowPowerClock
UpdateMode
LPTIM_TriggerConfigTypeDef
SampleTime
Source
LPTIM_ULPClockConfigTypeDef
SampleTime
MPU_Region_InitTypeDef
BaseAddress
DisableExec
Enable
IsBufferable
IsCacheable
IsShareable
Number
Size
SubRegionDisable
TypeExtField
OPAMP_InitTypeDef
InvertingInput
InvertingInputSecondary
Mode
NonInvertingInput
NonInvertingInputSecondary
PgaConnect
PgaGain
PowerMode
TimerControlledMuxmode
TrimmingValueN
TrimmingValueP
UserTrimming
PWR_PVDTypeDef
PVDLevel
PWR_PVMTypeDef
PVMType
QSPI_AutoPollingTypeDef
Interval
Mask
Match
MatchMode
StatusBytesSize
QSPI_CommandTypeDef
AddressMode
AddressSize
AlternateByteMode
AlternateBytes
AlternateBytesSize
DataMode
DdrHoldHalfCycle
DdrMode
DummyCycles
Instruction
InstructionMode
NbData
SIOOMode
QSPI_InitTypeDef
ClockMode
ClockPrescaler
DualFlash
FifoThreshold
FlashID
FlashSize
SampleShifting
QSPI_MemoryMappedTypeDef
TimeOutPeriod
RCC_ClkInitTypeDef
APB1CLKDivider
APB2CLKDivider
ClockType
SYSCLKSource
RCC_CRSInitTypeDef
HSI48CalibrationValue
Polarity
Prescaler
ReloadValue
Source
RCC_CRSSynchroInfoTypeDef
FreqErrorDirection
HSI48CalibrationValue
ReloadValue
RCC_OscInitTypeDef
HSI48State
HSICalibrationValue
HSIState
LSEState
LSIState
OscillatorType
PLL
RCC_PeriphCLKInitTypeDef
Adc345ClockSelection
FdcanClockSelection
I2c1ClockSelection
I2c2ClockSelection
I2c3ClockSelection
I2c4ClockSelection
I2sClockSelection
Lptim1ClockSelection
Lpuart1ClockSelection
PeriphClockSelection
QspiClockSelection
RngClockSelection
RTCClockSelection
Sai1ClockSelection
Uart4ClockSelection
Uart5ClockSelection
Usart1ClockSelection
Usart2ClockSelection
Usart3ClockSelection
UsbClockSelection
RCC_PLLInitTypeDef
PLLN
PLLP
PLLQ
PLLR
PLLSource
PLLState
RNG_InitTypeDef
RTC_AlarmTypeDef
AlarmDateWeekDay
AlarmDateWeekDaySel
AlarmMask
AlarmSubSecondMask
AlarmTime
RTC_DateTypeDef
Month
WeekDay
Year
RTC_InitTypeDef
HourFormat
OutPut
OutPutPolarity
OutPutPullUp
OutPutRemap
OutPutType
SynchPrediv
RTC_InternalTamperTypeDef
TimeStampOnTamperDetection
RTC_TamperTypeDef
MaskFlag
NoErase
PrechargeDuration
SamplingFrequency
Tamper
TamperPullUp
TimeStampOnTamperDetection
Trigger
RTC_TimeTypeDef
Hours
Minutes
SecondFraction
Seconds
StoreOperation
SubSeconds
TimeFormat
SAI_FrameInitTypeDef
FrameLength
FSDefinition
FSOffset
FSPolarity
SAI_InitTypeDef
AudioMode
ClockStrobing
CompandingMode
DataSize
FIFOThreshold
FirstBit
Mckdiv
MckOutput
MckOverSampling
MonoStereoMode
NoDivider
OutputDrive
PdmInit
Protocol
Synchro
SynchroExt
TriState
SAI_PdmInitTypeDef
ClockEnable
MicPairsNbr
SAI_SlotInitTypeDef
SlotActive
SlotNumber
SlotSize
SAIEx_PdmMicDelayParamTypeDef
MicPair
RightDelay
SMARTCARD_AdvFeatureInitTypeDef
DataInvert
DMADisableonRxError
MSBFirst
OverrunDisable
RxPinLevelInvert
Swap
TxCompletionIndication
TxPinLevelInvert
SMARTCARD_InitTypeDef
BaudRate
BlockLength
CLKLastBit
CLKPhase
CLKPolarity
ClockPrescaler
GuardTime
Mode
NACKEnable
OneBitSampling
Parity
Prescaler
StopBits
TimeOutEnable
TimeOutValue
WordLength
SMBUS_InitTypeDef
AnalogFilter
DualAddressMode
GeneralCallMode
NoStretchMode
OwnAddress1
OwnAddress2
OwnAddress2Masks
PacketErrorCheckMode
PeripheralMode
SMBusTimeout
Timing
SPI_InitTypeDef
CLKPhase
CLKPolarity
CRCCalculation
CRCLength
CRCPolynomial
DataSize
Direction
FirstBit
Mode
NSS
NSSPMode
TIMode
TIM_Base_InitTypeDef
ClockDivision
CounterMode
Period
Prescaler
RepetitionCounter
TIM_BreakDeadTimeConfigTypeDef
Break2AFMode
Break2Filter
Break2Polarity
Break2State
BreakAFMode
BreakFilter
BreakPolarity
BreakState
DeadTime
LockLevel
OffStateIDLEMode
OffStateRunMode
TIM_ClearInputConfigTypeDef
ClearInputPolarity
ClearInputPrescaler
ClearInputSource
ClearInputState
TIM_ClockConfigTypeDef
ClockPolarity
ClockPrescaler
ClockSource
TIM_Encoder_InitTypeDef
IC1Filter
IC1Polarity
IC1Prescaler
IC1Selection
IC2Filter
IC2Polarity
IC2Prescaler
IC2Selection
TIM_HallSensor_InitTypeDef
IC1Filter
IC1Polarity
IC1Prescaler
TIM_IC_InitTypeDef
ICPolarity
ICPrescaler
ICSelection
TIM_MasterConfigTypeDef
MasterOutputTrigger2
MasterSlaveMode
TIM_OC_InitTypeDef
OCIdleState
OCMode
OCNIdleState
OCNPolarity
OCPolarity
Pulse
TIM_OnePulse_InitTypeDef
ICPolarity
ICSelection
OCIdleState
OCMode
OCNIdleState
OCNPolarity
OCPolarity
Pulse
TIM_SlaveConfigTypeDef
SlaveMode
TriggerFilter
TriggerPolarity
TriggerPrescaler
TIMEx_BreakInputConfigTypeDef
Polarity
Source
TIMEx_EncoderIndexConfigTypeDef
Filter
FirstIndexEnable
Polarity
Position
Prescaler
UART_AdvFeatureInitTypeDef
AutoBaudRateEnable
AutoBaudRateMode
DataInvert
DMADisableonRxError
MSBFirst
OverrunDisable
RxPinLevelInvert
Swap
TxPinLevelInvert
UART_InitTypeDef
ClockPrescaler
HwFlowCtl
Mode
OneBitSampling
OverSampling
Parity
StopBits
WordLength
UART_WakeUpTypeDef
AddressLength
WakeUpEvent
USART_InitTypeDef
CLKLastBit
CLKPhase
CLKPolarity
ClockPrescaler
Mode
Parity
StopBits
WordLength
WWDG_InitTypeDef
EWIMode
Prescaler
Window
Data Structure Index
b
c
d
e
f
g
h
i
l
m
n
o
p
q
r
s
t
u
v
w
x
y
Variables
b
c
d
e
f
g
h
i
l
m
n
o
p
q
r
s
t
u
v
w
x
y
Files
__STM32G4xx_HAL_VERSION_MAIN
__STM32G4xx_HAL_VERSION_RC
__STM32G4xx_HAL_VERSION_SUB1
__STM32G4xx_HAL_VERSION_SUB2
CCMER_BitNumber
FB_MODE_BB
FB_MODE_BitNumber
MEMRMP_OFFSET
SCSR_CCMER_BB
SCSR_OFFSET
SYSCFG_OFFSET
VREFBUF_TIMEOUT_VALUE
HAL_DBGMCU_DisableDBGSleepMode
HAL_DBGMCU_DisableDBGStandbyMode
HAL_DBGMCU_DisableDBGStopMode
HAL_DBGMCU_EnableDBGSleepMode
HAL_DBGMCU_EnableDBGStandbyMode
HAL_DBGMCU_EnableDBGStopMode
HAL_DeInit
HAL_Delay
HAL_GetDEVID
HAL_GetHalVersion
HAL_GetREVID
HAL_GetTick
HAL_GetTickFreq
HAL_GetTickPrio
HAL_GetUIDw0
HAL_GetUIDw1
HAL_GetUIDw2
HAL_IncTick
HAL_Init
HAL_InitTick
HAL_MspDeInit
HAL_MspInit
HAL_ResumeTick
HAL_SetTickFreq
HAL_SuspendTick
HAL_SYSCFG_CCMSRAM_WriteProtectionEnable
HAL_SYSCFG_CCMSRAMErase
HAL_SYSCFG_DisableIOSwitchBooster
HAL_SYSCFG_DisableIOSwitchVDD
HAL_SYSCFG_DisableMemorySwappingBank
HAL_SYSCFG_DisableVREFBUF
HAL_SYSCFG_EnableIOSwitchBooster
HAL_SYSCFG_EnableIOSwitchVDD
HAL_SYSCFG_EnableMemorySwappingBank
HAL_SYSCFG_EnableVREFBUF
HAL_SYSCFG_VREFBUF_HighImpedanceConfig
HAL_SYSCFG_VREFBUF_TrimmingConfig
HAL_SYSCFG_VREFBUF_VoltageScalingConfig
uwTick
uwTickFreq
uwTickPrio
stm32g4xx_hal.h
__HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
__HAL_DBGMCU_FREEZE_I2C4_TIMEOUT
__HAL_DBGMCU_FREEZE_IWDG
__HAL_DBGMCU_FREEZE_LPTIM1
__HAL_DBGMCU_FREEZE_RTC
__HAL_DBGMCU_FREEZE_TIM1
__HAL_DBGMCU_FREEZE_TIM15
__HAL_DBGMCU_FREEZE_TIM16
__HAL_DBGMCU_FREEZE_TIM17
__HAL_DBGMCU_FREEZE_TIM2
__HAL_DBGMCU_FREEZE_TIM20
__HAL_DBGMCU_FREEZE_TIM3
__HAL_DBGMCU_FREEZE_TIM4
__HAL_DBGMCU_FREEZE_TIM5
__HAL_DBGMCU_FREEZE_TIM6
__HAL_DBGMCU_FREEZE_TIM7
__HAL_DBGMCU_FREEZE_TIM8
__HAL_DBGMCU_FREEZE_WWDG
__HAL_DBGMCU_UNFREEZE_HRTIM1
__HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
__HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT
__HAL_DBGMCU_UNFREEZE_IWDG
__HAL_DBGMCU_UNFREEZE_LPTIM1
__HAL_DBGMCU_UNFREEZE_RTC
__HAL_DBGMCU_UNFREEZE_TIM1
__HAL_DBGMCU_UNFREEZE_TIM15
__HAL_DBGMCU_UNFREEZE_TIM16
__HAL_DBGMCU_UNFREEZE_TIM17
__HAL_DBGMCU_UNFREEZE_TIM2
__HAL_DBGMCU_UNFREEZE_TIM20
__HAL_DBGMCU_UNFREEZE_TIM3
__HAL_DBGMCU_UNFREEZE_TIM4
__HAL_DBGMCU_UNFREEZE_TIM5
__HAL_DBGMCU_UNFREEZE_TIM6
__HAL_DBGMCU_UNFREEZE_TIM7
__HAL_DBGMCU_UNFREEZE_TIM8
__HAL_DBGMCU_UNFREEZE_WWDG
__HAL_SYSCFG_BREAK_ECC_LOCK
__HAL_SYSCFG_BREAK_LOCKUP_LOCK
__HAL_SYSCFG_BREAK_PVD_LOCK
__HAL_SYSCFG_BREAK_SRAMPARITY_LOCK
__HAL_SYSCFG_CCMSRAM_ERASE
__HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
__HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE
__HAL_SYSCFG_CCMSRAM_WRP_UNLOCK
__HAL_SYSCFG_CLEAR_FLAG
__HAL_SYSCFG_FASTMODEPLUS_DISABLE
__HAL_SYSCFG_FASTMODEPLUS_ENABLE
__HAL_SYSCFG_FPU_INTERRUPT_DISABLE
__HAL_SYSCFG_FPU_INTERRUPT_ENABLE
__HAL_SYSCFG_GET_BOOT_MODE
__HAL_SYSCFG_GET_FLAG
__HAL_SYSCFG_REMAPMEMORY_FLASH
__HAL_SYSCFG_REMAPMEMORY_FMC
__HAL_SYSCFG_REMAPMEMORY_QUADSPI
__HAL_SYSCFG_REMAPMEMORY_SRAM
__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
HAL_TICK_FREQ_100HZ
HAL_TICK_FREQ_10HZ
HAL_TICK_FREQ_1KHZ
HAL_TICK_FREQ_DEFAULT
IS_SYSCFG_BREAK_CONFIG
IS_SYSCFG_CCMSRAMWRP_PAGE
IS_SYSCFG_FASTMODEPLUS
IS_SYSCFG_FPU_INTERRUPT
IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE
IS_SYSCFG_VREFBUF_TRIMMING
IS_SYSCFG_VREFBUF_VOLTAGE_SCALE
IS_TICKFREQ
SYSCFG_BOOT_FMC
SYSCFG_BOOT_MAINFLASH
SYSCFG_BOOT_QUADSPI
SYSCFG_BOOT_SRAM
SYSCFG_BOOT_SYSTEMFLASH
SYSCFG_CCMSRAMWRP_PAGE0
SYSCFG_CCMSRAMWRP_PAGE1
SYSCFG_CCMSRAMWRP_PAGE10
SYSCFG_CCMSRAMWRP_PAGE11
SYSCFG_CCMSRAMWRP_PAGE12
SYSCFG_CCMSRAMWRP_PAGE13
SYSCFG_CCMSRAMWRP_PAGE14
SYSCFG_CCMSRAMWRP_PAGE15
SYSCFG_CCMSRAMWRP_PAGE16
SYSCFG_CCMSRAMWRP_PAGE17
SYSCFG_CCMSRAMWRP_PAGE18
SYSCFG_CCMSRAMWRP_PAGE19
SYSCFG_CCMSRAMWRP_PAGE2
SYSCFG_CCMSRAMWRP_PAGE20
SYSCFG_CCMSRAMWRP_PAGE21
SYSCFG_CCMSRAMWRP_PAGE22
SYSCFG_CCMSRAMWRP_PAGE23
SYSCFG_CCMSRAMWRP_PAGE24
SYSCFG_CCMSRAMWRP_PAGE25
SYSCFG_CCMSRAMWRP_PAGE26
SYSCFG_CCMSRAMWRP_PAGE27
SYSCFG_CCMSRAMWRP_PAGE28
SYSCFG_CCMSRAMWRP_PAGE29
SYSCFG_CCMSRAMWRP_PAGE3
SYSCFG_CCMSRAMWRP_PAGE30
SYSCFG_CCMSRAMWRP_PAGE31
SYSCFG_CCMSRAMWRP_PAGE4
SYSCFG_CCMSRAMWRP_PAGE5
SYSCFG_CCMSRAMWRP_PAGE6
SYSCFG_CCMSRAMWRP_PAGE7
SYSCFG_CCMSRAMWRP_PAGE8
SYSCFG_CCMSRAMWRP_PAGE9
SYSCFG_FASTMODEPLUS_PB6
SYSCFG_FASTMODEPLUS_PB7
SYSCFG_FASTMODEPLUS_PB8
SYSCFG_FASTMODEPLUS_PB9
SYSCFG_FLAG_CCMSRAM_BUSY
SYSCFG_FLAG_SRAM_PE
SYSCFG_IT_FPU_DZC
SYSCFG_IT_FPU_IDC
SYSCFG_IT_FPU_IOC
SYSCFG_IT_FPU_IXC
SYSCFG_IT_FPU_OFC
SYSCFG_IT_FPU_UFC
SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE
SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE
SYSCFG_VREFBUF_VOLTAGE_SCALE0
SYSCFG_VREFBUF_VOLTAGE_SCALE1
SYSCFG_VREFBUF_VOLTAGE_SCALE2
HAL_DBGMCU_DisableDBGSleepMode
HAL_DBGMCU_DisableDBGStandbyMode
HAL_DBGMCU_DisableDBGStopMode
HAL_DBGMCU_EnableDBGSleepMode
HAL_DBGMCU_EnableDBGStandbyMode
HAL_DBGMCU_EnableDBGStopMode
HAL_DeInit
HAL_Delay
HAL_GetDEVID
HAL_GetHalVersion
HAL_GetREVID
HAL_GetTick
HAL_GetTickFreq
HAL_GetTickPrio
HAL_GetUIDw0
HAL_GetUIDw1
HAL_GetUIDw2
HAL_IncTick
HAL_Init
HAL_InitTick
HAL_MspDeInit
HAL_MspInit
HAL_ResumeTick
HAL_SetTickFreq
HAL_SuspendTick
HAL_SYSCFG_CCMSRAM_WriteProtectionEnable
HAL_SYSCFG_CCMSRAMErase
HAL_SYSCFG_DisableIOSwitchBooster
HAL_SYSCFG_DisableIOSwitchVDD
HAL_SYSCFG_DisableMemorySwappingBank
HAL_SYSCFG_DisableVREFBUF
HAL_SYSCFG_EnableIOSwitchBooster
HAL_SYSCFG_EnableIOSwitchVDD
HAL_SYSCFG_EnableMemorySwappingBank
HAL_SYSCFG_EnableVREFBUF
HAL_SYSCFG_VREFBUF_HighImpedanceConfig
HAL_SYSCFG_VREFBUF_TrimmingConfig
HAL_SYSCFG_VREFBUF_VoltageScalingConfig
uwTick
uwTickFreq
uwTickPrio
stm32g4xx_hal_adc.c
ADC_CONVERSION_TIME_MAX_CPU_CYCLES
ADC_DISABLE_TIMEOUT
ADC_ENABLE_TIMEOUT
ADC_ConversionStop
ADC_Disable
ADC_DMAConvCplt
ADC_DMAError
ADC_DMAHalfConvCplt
ADC_Enable
HAL_ADC_AnalogWDGConfig
HAL_ADC_ConfigChannel
HAL_ADC_ConvCpltCallback
HAL_ADC_ConvHalfCpltCallback
HAL_ADC_DeInit
HAL_ADC_ErrorCallback
HAL_ADC_GetError
HAL_ADC_GetState
HAL_ADC_GetValue
HAL_ADC_Init
HAL_ADC_IRQHandler
HAL_ADC_LevelOutOfWindowCallback
HAL_ADC_MspDeInit
HAL_ADC_MspInit
HAL_ADC_PollForConversion
HAL_ADC_PollForEvent
HAL_ADC_RegisterCallback
HAL_ADC_Start
HAL_ADC_Start_DMA
HAL_ADC_Start_IT
HAL_ADC_StartSampling
HAL_ADC_Stop
HAL_ADC_Stop_DMA
HAL_ADC_Stop_IT
HAL_ADC_StopSampling
HAL_ADC_UnRegisterCallback
stm32g4xx_hal_adc.h
__HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE
__HAL_ADC_CALC_TEMPERATURE
__HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS
__HAL_ADC_CALC_VREFANALOG_VOLTAGE
__HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL
__HAL_ADC_CHANNEL_TO_DECIMAL_NB
__HAL_ADC_CLEAR_FLAG
__HAL_ADC_COMMON_INSTANCE
__HAL_ADC_CONVERT_DATA_RESOLUTION
__HAL_ADC_DECIMAL_NB_TO_CHANNEL
__HAL_ADC_DIGITAL_SCALE
__HAL_ADC_DISABLE_IT
__HAL_ADC_ENABLE_IT
__HAL_ADC_GET_FLAG
__HAL_ADC_GET_IT_SOURCE
__HAL_ADC_IS_CHANNEL_INTERNAL
__HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE
__HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE
__HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE
__HAL_ADC_RESET_HANDLE_STATE
ADC_ANALOGWATCHDOG_1
ADC_ANALOGWATCHDOG_2
ADC_ANALOGWATCHDOG_3
ADC_ANALOGWATCHDOG_ALL_INJEC
ADC_ANALOGWATCHDOG_ALL_REG
ADC_ANALOGWATCHDOG_ALL_REGINJEC
ADC_ANALOGWATCHDOG_NONE
ADC_ANALOGWATCHDOG_SINGLE_INJEC
ADC_ANALOGWATCHDOG_SINGLE_REG
ADC_ANALOGWATCHDOG_SINGLE_REGINJEC
ADC_AWD1_EVENT
ADC_AWD2_EVENT
ADC_AWD3_EVENT
ADC_AWD_EVENT
ADC_AWD_FILTERING_2SAMPLES
ADC_AWD_FILTERING_3SAMPLES
ADC_AWD_FILTERING_4SAMPLES
ADC_AWD_FILTERING_5SAMPLES
ADC_AWD_FILTERING_6SAMPLES
ADC_AWD_FILTERING_7SAMPLES
ADC_AWD_FILTERING_8SAMPLES
ADC_AWD_FILTERING_NONE
ADC_CHANNEL_0
ADC_CHANNEL_1
ADC_CHANNEL_10
ADC_CHANNEL_11
ADC_CHANNEL_12
ADC_CHANNEL_13
ADC_CHANNEL_14
ADC_CHANNEL_15
ADC_CHANNEL_16
ADC_CHANNEL_17
ADC_CHANNEL_18
ADC_CHANNEL_2
ADC_CHANNEL_3
ADC_CHANNEL_4
ADC_CHANNEL_5
ADC_CHANNEL_6
ADC_CHANNEL_7
ADC_CHANNEL_8
ADC_CHANNEL_9
ADC_CHANNEL_TEMPSENSOR_ADC1
ADC_CHANNEL_TEMPSENSOR_ADC5
ADC_CHANNEL_VBAT
ADC_CHANNEL_VOPAMP1
ADC_CHANNEL_VOPAMP2
ADC_CHANNEL_VOPAMP3_ADC2
ADC_CHANNEL_VOPAMP3_ADC3
ADC_CHANNEL_VOPAMP4
ADC_CHANNEL_VOPAMP5
ADC_CHANNEL_VOPAMP6
ADC_CHANNEL_VREFINT
ADC_CLEAR_ERRORCODE
ADC_CLOCK_ASYNC_DIV1
ADC_CLOCK_ASYNC_DIV10
ADC_CLOCK_ASYNC_DIV12
ADC_CLOCK_ASYNC_DIV128
ADC_CLOCK_ASYNC_DIV16
ADC_CLOCK_ASYNC_DIV2
ADC_CLOCK_ASYNC_DIV256
ADC_CLOCK_ASYNC_DIV32
ADC_CLOCK_ASYNC_DIV4
ADC_CLOCK_ASYNC_DIV6
ADC_CLOCK_ASYNC_DIV64
ADC_CLOCK_ASYNC_DIV8
ADC_CLOCK_SYNC_PCLK_DIV1
ADC_CLOCK_SYNC_PCLK_DIV2
ADC_CLOCK_SYNC_PCLK_DIV4
ADC_DATAALIGN_LEFT
ADC_DATAALIGN_RIGHT
ADC_EOC_SEQ_CONV
ADC_EOC_SINGLE_CONV
ADC_EOSMP_EVENT
ADC_EXTERNALTRIG_EXT_IT11
ADC_EXTERNALTRIG_EXT_IT2
ADC_EXTERNALTRIG_HRTIM_TRG1
ADC_EXTERNALTRIG_HRTIM_TRG10
ADC_EXTERNALTRIG_HRTIM_TRG2
ADC_EXTERNALTRIG_HRTIM_TRG3
ADC_EXTERNALTRIG_HRTIM_TRG4
ADC_EXTERNALTRIG_HRTIM_TRG5
ADC_EXTERNALTRIG_HRTIM_TRG6
ADC_EXTERNALTRIG_HRTIM_TRG7
ADC_EXTERNALTRIG_HRTIM_TRG8
ADC_EXTERNALTRIG_HRTIM_TRG9
ADC_EXTERNALTRIG_LPTIM_OUT
ADC_EXTERNALTRIG_T15_TRGO
ADC_EXTERNALTRIG_T1_CC1
ADC_EXTERNALTRIG_T1_CC2
ADC_EXTERNALTRIG_T1_CC3
ADC_EXTERNALTRIG_T1_TRGO
ADC_EXTERNALTRIG_T1_TRGO2
ADC_EXTERNALTRIG_T20_CC1
ADC_EXTERNALTRIG_T20_CC2
ADC_EXTERNALTRIG_T20_CC3
ADC_EXTERNALTRIG_T20_TRGO
ADC_EXTERNALTRIG_T20_TRGO2
ADC_EXTERNALTRIG_T2_CC1
ADC_EXTERNALTRIG_T2_CC2
ADC_EXTERNALTRIG_T2_CC3
ADC_EXTERNALTRIG_T2_TRGO
ADC_EXTERNALTRIG_T3_CC1
ADC_EXTERNALTRIG_T3_CC4
ADC_EXTERNALTRIG_T3_TRGO
ADC_EXTERNALTRIG_T4_CC1
ADC_EXTERNALTRIG_T4_CC4
ADC_EXTERNALTRIG_T4_TRGO
ADC_EXTERNALTRIG_T6_TRGO
ADC_EXTERNALTRIG_T7_TRGO
ADC_EXTERNALTRIG_T8_CC1
ADC_EXTERNALTRIG_T8_TRGO
ADC_EXTERNALTRIG_T8_TRGO2
ADC_EXTERNALTRIGCONVEDGE_FALLING
ADC_EXTERNALTRIGCONVEDGE_NONE
ADC_EXTERNALTRIGCONVEDGE_RISING
ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
ADC_FLAG_AWD1
ADC_FLAG_AWD2
ADC_FLAG_AWD3
ADC_FLAG_EOC
ADC_FLAG_EOS
ADC_FLAG_EOSMP
ADC_FLAG_JEOC
ADC_FLAG_JEOS
ADC_FLAG_JQOVF
ADC_FLAG_OVR
ADC_FLAG_RDY
ADC_GET_RESOLUTION
ADC_IT_AWD1
ADC_IT_AWD2
ADC_IT_AWD3
ADC_IT_EOC
ADC_IT_EOS
ADC_IT_EOSMP
ADC_IT_JEOC
ADC_IT_JEOS
ADC_IT_JQOVF
ADC_IT_OVR
ADC_IT_RDY
ADC_JQOVF_EVENT
ADC_OVERSAMPLING_RATIO_128
ADC_OVERSAMPLING_RATIO_16
ADC_OVERSAMPLING_RATIO_2
ADC_OVERSAMPLING_RATIO_256
ADC_OVERSAMPLING_RATIO_32
ADC_OVERSAMPLING_RATIO_4
ADC_OVERSAMPLING_RATIO_64
ADC_OVERSAMPLING_RATIO_8
ADC_OVR_DATA_OVERWRITTEN
ADC_OVR_DATA_PRESERVED
ADC_OVR_EVENT
ADC_REGOVERSAMPLING_CONTINUED_MODE
ADC_REGOVERSAMPLING_RESUMED_MODE
ADC_REGULAR_RANK_1
ADC_REGULAR_RANK_10
ADC_REGULAR_RANK_11
ADC_REGULAR_RANK_12
ADC_REGULAR_RANK_13
ADC_REGULAR_RANK_14
ADC_REGULAR_RANK_15
ADC_REGULAR_RANK_16
ADC_REGULAR_RANK_2
ADC_REGULAR_RANK_3
ADC_REGULAR_RANK_4
ADC_REGULAR_RANK_5
ADC_REGULAR_RANK_6
ADC_REGULAR_RANK_7
ADC_REGULAR_RANK_8
ADC_REGULAR_RANK_9
ADC_RESOLUTION_10B
ADC_RESOLUTION_12B
ADC_RESOLUTION_6B
ADC_RESOLUTION_8B
ADC_RIGHTBITSHIFT_1
ADC_RIGHTBITSHIFT_2
ADC_RIGHTBITSHIFT_3
ADC_RIGHTBITSHIFT_4
ADC_RIGHTBITSHIFT_5
ADC_RIGHTBITSHIFT_6
ADC_RIGHTBITSHIFT_7
ADC_RIGHTBITSHIFT_8
ADC_RIGHTBITSHIFT_NONE
ADC_SAMPLETIME_12CYCLES_5
ADC_SAMPLETIME_247CYCLES_5
ADC_SAMPLETIME_24CYCLES_5
ADC_SAMPLETIME_2CYCLES_5
ADC_SAMPLETIME_3CYCLES_5
ADC_SAMPLETIME_47CYCLES_5
ADC_SAMPLETIME_640CYCLES_5
ADC_SAMPLETIME_6CYCLES_5
ADC_SAMPLETIME_92CYCLES_5
ADC_SAMPLING_MODE_BULB
ADC_SAMPLING_MODE_NORMAL
ADC_SAMPLING_MODE_TRIGGER_CONTROLED
ADC_SCAN_DISABLE
ADC_SCAN_ENABLE
ADC_SOFTWARE_START
ADC_STATE_CLR_SET
ADC_STOP_CONVERSION_TIMEOUT
ADC_TEMPSENSOR_DELAY_US
ADC_TRIGGEREDMODE_MULTI_TRIGGER
ADC_TRIGGEREDMODE_SINGLE_TRIGGER
HAL_ADC_ERROR_DMA
HAL_ADC_ERROR_INTERNAL
HAL_ADC_ERROR_INVALID_CALLBACK
HAL_ADC_ERROR_JQOVF
HAL_ADC_ERROR_NONE
HAL_ADC_ERROR_OVR
HAL_ADC_STATE_AWD1
HAL_ADC_STATE_AWD2
HAL_ADC_STATE_AWD3
HAL_ADC_STATE_BUSY_INTERNAL
HAL_ADC_STATE_ERROR_CONFIG
HAL_ADC_STATE_ERROR_DMA
HAL_ADC_STATE_ERROR_INTERNAL
HAL_ADC_STATE_INJ_BUSY
HAL_ADC_STATE_INJ_EOC
HAL_ADC_STATE_INJ_JQOVF
HAL_ADC_STATE_MULTIMODE_SLAVE
HAL_ADC_STATE_READY
HAL_ADC_STATE_REG_BUSY
HAL_ADC_STATE_REG_EOC
HAL_ADC_STATE_REG_EOSMP
HAL_ADC_STATE_REG_OVR
HAL_ADC_STATE_RESET
HAL_ADC_STATE_TIMEOUT
IS_ADC_CLOCKPRESCALER
IS_ADC_DATA_ALIGN
IS_ADC_EOC_SELECTION
IS_ADC_EXTTRIG
IS_ADC_EXTTRIG_EDGE
IS_ADC_GAIN_COMPENSATION
IS_ADC_OVERRUN
IS_ADC_RANGE
IS_ADC_REGULAR_DISCONT_NUMBER
IS_ADC_REGULAR_NB_CONV
IS_ADC_REGULAR_RANK
IS_ADC_RESOLUTION
IS_ADC_RESOLUTION_8_6_BITS
IS_ADC_SAMPLE_TIME
IS_ADC_SAMPLINGMODE
IS_ADC_SCAN_MODE
ADC_HandleTypeDef
pADC_CallbackTypeDef
HAL_ADC_CallbackIDTypeDef
ADC_ConversionStop
ADC_Disable
ADC_DMAConvCplt
ADC_DMAError
ADC_DMAHalfConvCplt
ADC_Enable
HAL_ADC_AnalogWDGConfig
HAL_ADC_ConfigChannel
HAL_ADC_ConvCpltCallback
HAL_ADC_ConvHalfCpltCallback
HAL_ADC_DeInit
HAL_ADC_ErrorCallback
HAL_ADC_GetError
HAL_ADC_GetState
HAL_ADC_GetValue
HAL_ADC_Init
HAL_ADC_IRQHandler
HAL_ADC_LevelOutOfWindowCallback
HAL_ADC_MspDeInit
HAL_ADC_MspInit
HAL_ADC_PollForConversion
HAL_ADC_PollForEvent
HAL_ADC_RegisterCallback
HAL_ADC_Start
HAL_ADC_Start_DMA
HAL_ADC_Start_IT
HAL_ADC_StartSampling
HAL_ADC_Stop
HAL_ADC_Stop_DMA
HAL_ADC_Stop_IT
HAL_ADC_StopSampling
HAL_ADC_UnRegisterCallback
stm32g4xx_hal_adc_ex.c
ADC_JSQR_FIELDS
HAL_ADCEx_Calibration_GetValue
HAL_ADCEx_Calibration_SetValue
HAL_ADCEx_Calibration_Start
HAL_ADCEx_DisableInjectedQueue
HAL_ADCEx_DisableVoltageRegulator
HAL_ADCEx_EnableInjectedQueue
HAL_ADCEx_EndOfSamplingCallback
HAL_ADCEx_EnterADCDeepPowerDownMode
HAL_ADCEx_InjectedConfigChannel
HAL_ADCEx_InjectedConvCpltCallback
HAL_ADCEx_InjectedGetValue
HAL_ADCEx_InjectedPollForConversion
HAL_ADCEx_InjectedQueueOverflowCallback
HAL_ADCEx_InjectedStart
HAL_ADCEx_InjectedStart_IT
HAL_ADCEx_InjectedStop
HAL_ADCEx_InjectedStop_IT
HAL_ADCEx_LevelOutOfWindow2Callback
HAL_ADCEx_LevelOutOfWindow3Callback
HAL_ADCEx_MultiModeConfigChannel
HAL_ADCEx_MultiModeGetValue
HAL_ADCEx_MultiModeStart_DMA
HAL_ADCEx_MultiModeStop_DMA
HAL_ADCEx_RegularMultiModeStop_DMA
HAL_ADCEx_RegularStop
HAL_ADCEx_RegularStop_DMA
HAL_ADCEx_RegularStop_IT
stm32g4xx_hal_adc_ex.h
ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
ADC_BATTERY_VOLTAGE_INSTANCE
ADC_CCR_MULTI_DMACONTREQ
ADC_CFGR_AUTOWAIT
ADC_CFGR_CONTINUOUS
ADC_CFGR_DFSDM
ADC_CFGR_DISCONTINUOUS_NUM
ADC_CFGR_DMACONTREQ
ADC_CFGR_FIELDS
ADC_CFGR_FIELDS_2
ADC_CFGR_INJECT_CONTEXT_QUEUE
ADC_CFGR_INJECT_DISCCONTINUOUS
ADC_CFGR_REG_DISCONTINUOUS
ADC_CLEAR_COMMON_CONTROL_REGISTER
ADC_DIFFERENTIAL_ENDED
ADC_DMAACCESSMODE_12_10_BITS
ADC_DMAACCESSMODE_8_6_BITS
ADC_DMAACCESSMODE_DISABLED
ADC_DUALMODE_ALTERTRIG
ADC_DUALMODE_INJECSIMULT
ADC_DUALMODE_INTERL
ADC_DUALMODE_REGINTERL_INJECSIMULT
ADC_DUALMODE_REGSIMULT
ADC_DUALMODE_REGSIMULT_ALTERTRIG
ADC_DUALMODE_REGSIMULT_INJECSIMULT
ADC_EXTERNALTRIGINJEC_EXT_IT15
ADC_EXTERNALTRIGINJEC_EXT_IT3
ADC_EXTERNALTRIGINJEC_HRTIM_TRG1
ADC_EXTERNALTRIGINJEC_HRTIM_TRG10
ADC_EXTERNALTRIGINJEC_HRTIM_TRG2
ADC_EXTERNALTRIGINJEC_HRTIM_TRG3
ADC_EXTERNALTRIGINJEC_HRTIM_TRG4
ADC_EXTERNALTRIGINJEC_HRTIM_TRG5
ADC_EXTERNALTRIGINJEC_HRTIM_TRG6
ADC_EXTERNALTRIGINJEC_HRTIM_TRG7
ADC_EXTERNALTRIGINJEC_HRTIM_TRG8
ADC_EXTERNALTRIGINJEC_HRTIM_TRG9
ADC_EXTERNALTRIGINJEC_LPTIM_OUT
ADC_EXTERNALTRIGINJEC_T15_TRGO
ADC_EXTERNALTRIGINJEC_T16_CC1
ADC_EXTERNALTRIGINJEC_T1_CC3
ADC_EXTERNALTRIGINJEC_T1_CC4
ADC_EXTERNALTRIGINJEC_T1_TRGO
ADC_EXTERNALTRIGINJEC_T1_TRGO2
ADC_EXTERNALTRIGINJEC_T20_CC2
ADC_EXTERNALTRIGINJEC_T20_CC4
ADC_EXTERNALTRIGINJEC_T20_TRGO
ADC_EXTERNALTRIGINJEC_T20_TRGO2
ADC_EXTERNALTRIGINJEC_T2_CC1
ADC_EXTERNALTRIGINJEC_T2_TRGO
ADC_EXTERNALTRIGINJEC_T3_CC1
ADC_EXTERNALTRIGINJEC_T3_CC3
ADC_EXTERNALTRIGINJEC_T3_CC4
ADC_EXTERNALTRIGINJEC_T3_TRGO
ADC_EXTERNALTRIGINJEC_T4_CC3
ADC_EXTERNALTRIGINJEC_T4_CC4
ADC_EXTERNALTRIGINJEC_T4_TRGO
ADC_EXTERNALTRIGINJEC_T6_TRGO
ADC_EXTERNALTRIGINJEC_T7_TRGO
ADC_EXTERNALTRIGINJEC_T8_CC2
ADC_EXTERNALTRIGINJEC_T8_CC4
ADC_EXTERNALTRIGINJEC_T8_TRGO
ADC_EXTERNALTRIGINJEC_T8_TRGO2
ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING
ADC_EXTERNALTRIGINJECCONV_EDGE_NONE
ADC_EXTERNALTRIGINJECCONV_EDGE_RISING
ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING
ADC_FORCE_MODE_INDEPENDENT
ADC_INJECTED_GROUP
ADC_INJECTED_RANK_1
ADC_INJECTED_RANK_2
ADC_INJECTED_RANK_3
ADC_INJECTED_RANK_4
ADC_INJECTED_SOFTWARE_START
ADC_IS_INDEPENDENT
ADC_IS_SOFTWARE_START_INJECTED
ADC_JSQR_RK
ADC_MODE_INDEPENDENT
ADC_MULTI_SLAVE
ADC_OFFSET_1
ADC_OFFSET_2
ADC_OFFSET_3
ADC_OFFSET_4
ADC_OFFSET_NONE
ADC_OFFSET_SHIFT_RESOLUTION
ADC_OFFSET_SIGN_NEGATIVE
ADC_OFFSET_SIGN_POSITIVE
ADC_REGULAR_GROUP
ADC_REGULAR_INJECTED_GROUP
ADC_SINGLE_ENDED
ADC_SMPR1_FIELDS
ADC_TEMPERATURE_SENSOR_INSTANCE
ADC_TWOSAMPLINGDELAY_10CYCLES
ADC_TWOSAMPLINGDELAY_11CYCLES
ADC_TWOSAMPLINGDELAY_12CYCLES
ADC_TWOSAMPLINGDELAY_1CYCLE
ADC_TWOSAMPLINGDELAY_2CYCLES
ADC_TWOSAMPLINGDELAY_3CYCLES
ADC_TWOSAMPLINGDELAY_4CYCLES
ADC_TWOSAMPLINGDELAY_5CYCLES
ADC_TWOSAMPLINGDELAY_6CYCLES
ADC_TWOSAMPLINGDELAY_7CYCLES
ADC_TWOSAMPLINGDELAY_8CYCLES
ADC_TWOSAMPLINGDELAY_9CYCLES
ADC_VREFINT_INSTANCE
IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE
IS_ADC_ANALOG_WATCHDOG_MODE
IS_ADC_ANALOG_WATCHDOG_NUMBER
IS_ADC_CALFACT
IS_ADC_CHANNEL
IS_ADC_CONVERSION_GROUP
IS_ADC_DFSDMCFG_MODE
IS_ADC_DIFF_CHANNEL
IS_ADC_DMA_ACCESS_MULTIMODE
IS_ADC_EVENT_TYPE
IS_ADC_EXTTRIGINJEC
IS_ADC_EXTTRIGINJEC_EDGE
IS_ADC_INJECTED_NB_CONV
IS_ADC_INJECTED_RANK
IS_ADC_MULTIMODE
IS_ADC_OFFSET_NUMBER
IS_ADC_OFFSET_SIGN
IS_ADC_OVERSAMPLING_RATIO
IS_ADC_REGOVERSAMPLING_MODE
IS_ADC_RIGHT_BIT_SHIFT
IS_ADC_SAMPLING_DELAY
IS_ADC_SINGLE_DIFFERENTIAL
IS_ADC_TRIGGERED_OVERSAMPLING_MODE
HAL_ADCEx_Calibration_GetValue
HAL_ADCEx_Calibration_SetValue
HAL_ADCEx_Calibration_Start
HAL_ADCEx_DisableInjectedQueue
HAL_ADCEx_DisableVoltageRegulator
HAL_ADCEx_EnableInjectedQueue
HAL_ADCEx_EndOfSamplingCallback
HAL_ADCEx_EnterADCDeepPowerDownMode
HAL_ADCEx_InjectedConfigChannel
HAL_ADCEx_InjectedConvCpltCallback
HAL_ADCEx_InjectedGetValue
HAL_ADCEx_InjectedPollForConversion
HAL_ADCEx_InjectedQueueOverflowCallback
HAL_ADCEx_InjectedStart
HAL_ADCEx_InjectedStart_IT
HAL_ADCEx_InjectedStop
HAL_ADCEx_InjectedStop_IT
HAL_ADCEx_LevelOutOfWindow2Callback
HAL_ADCEx_LevelOutOfWindow3Callback
HAL_ADCEx_MultiModeConfigChannel
HAL_ADCEx_MultiModeGetValue
HAL_ADCEx_MultiModeStart_DMA
HAL_ADCEx_MultiModeStop_DMA
HAL_ADCEx_RegularMultiModeStop_DMA
HAL_ADCEx_RegularStop
HAL_ADCEx_RegularStop_DMA
HAL_ADCEx_RegularStop_IT
stm32g4xx_hal_comp.c
COMP_DELAY_VOLTAGE_SCALER_STAB_US
COMP_OUTPUT_LEVEL_BITOFFSET_POS
HAL_COMP_DeInit
HAL_COMP_GetError
HAL_COMP_GetOutputLevel
HAL_COMP_GetState
HAL_COMP_Init
HAL_COMP_IRQHandler
HAL_COMP_Lock
HAL_COMP_MspDeInit
HAL_COMP_MspInit
HAL_COMP_RegisterCallback
HAL_COMP_Start
HAL_COMP_Stop
HAL_COMP_TriggerCallback
HAL_COMP_UnRegisterCallback
stm32g4xx_hal_comp.h
__HAL_COMP_COMP1_EXTI_DISABLE_EVENT
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_DISABLE_IT
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_EVENT
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_IT
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP1_EXTI_GENERATE_SWIT
__HAL_COMP_COMP1_EXTI_GET_FLAG
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG
__HAL_COMP_COMP2_EXTI_DISABLE_EVENT
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_DISABLE_IT
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_EVENT
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_IT
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP2_EXTI_GENERATE_SWIT
__HAL_COMP_COMP2_EXTI_GET_FLAG
__HAL_COMP_COMP3_EXTI_CLEAR_FLAG
__HAL_COMP_COMP3_EXTI_DISABLE_EVENT
__HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_DISABLE_IT
__HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_EVENT
__HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_IT
__HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP3_EXTI_GENERATE_SWIT
__HAL_COMP_COMP3_EXTI_GET_FLAG
__HAL_COMP_COMP4_EXTI_CLEAR_FLAG
__HAL_COMP_COMP4_EXTI_DISABLE_EVENT
__HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_DISABLE_IT
__HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_EVENT
__HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_IT
__HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP4_EXTI_GENERATE_SWIT
__HAL_COMP_COMP4_EXTI_GET_FLAG
__HAL_COMP_COMP5_EXTI_CLEAR_FLAG
__HAL_COMP_COMP5_EXTI_DISABLE_EVENT
__HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_DISABLE_IT
__HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_EVENT
__HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_IT
__HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP5_EXTI_GENERATE_SWIT
__HAL_COMP_COMP5_EXTI_GET_FLAG
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG
__HAL_COMP_COMP6_EXTI_DISABLE_EVENT
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_DISABLE_IT
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_EVENT
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_IT
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP6_EXTI_GENERATE_SWIT
__HAL_COMP_COMP6_EXTI_GET_FLAG
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG
__HAL_COMP_COMP7_EXTI_DISABLE_EVENT
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_DISABLE_IT
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_EVENT
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_IT
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_COMP_COMP7_EXTI_GENERATE_SWIT
__HAL_COMP_COMP7_EXTI_GET_FLAG
__HAL_COMP_DISABLE
__HAL_COMP_ENABLE
__HAL_COMP_IS_LOCKED
__HAL_COMP_LOCK
__HAL_COMP_RESET_HANDLE_STATE
COMP_BLANKINGSRC_NONE
COMP_BLANKINGSRC_TIM15_OC1
COMP_BLANKINGSRC_TIM15_OC1_COMP4
COMP_BLANKINGSRC_TIM15_OC2_COMP6
COMP_BLANKINGSRC_TIM15_OC2_COMP7
COMP_BLANKINGSRC_TIM1_OC5_COMP1
COMP_BLANKINGSRC_TIM1_OC5_COMP2
COMP_BLANKINGSRC_TIM1_OC5_COMP3
COMP_BLANKINGSRC_TIM1_OC5_COMP4
COMP_BLANKINGSRC_TIM1_OC5_COMP5
COMP_BLANKINGSRC_TIM1_OC5_COMP6
COMP_BLANKINGSRC_TIM1_OC5_COMP7
COMP_BLANKINGSRC_TIM20_OC5
COMP_BLANKINGSRC_TIM2_OC3_COMP1
COMP_BLANKINGSRC_TIM2_OC3_COMP2
COMP_BLANKINGSRC_TIM2_OC3_COMP5
COMP_BLANKINGSRC_TIM2_OC4_COMP3
COMP_BLANKINGSRC_TIM2_OC4_COMP6
COMP_BLANKINGSRC_TIM3_OC3_COMP1
COMP_BLANKINGSRC_TIM3_OC3_COMP2
COMP_BLANKINGSRC_TIM3_OC3_COMP3
COMP_BLANKINGSRC_TIM3_OC3_COMP5
COMP_BLANKINGSRC_TIM3_OC3_COMP7
COMP_BLANKINGSRC_TIM3_OC4_COMP4
COMP_BLANKINGSRC_TIM4_OC3
COMP_BLANKINGSRC_TIM8_OC5_COMP1
COMP_BLANKINGSRC_TIM8_OC5_COMP2
COMP_BLANKINGSRC_TIM8_OC5_COMP3
COMP_BLANKINGSRC_TIM8_OC5_COMP4
COMP_BLANKINGSRC_TIM8_OC5_COMP5
COMP_BLANKINGSRC_TIM8_OC5_COMP6
COMP_BLANKINGSRC_TIM8_OC5_COMP7
COMP_CLEAR_ERRORCODE
COMP_EXTI_EVENT
COMP_EXTI_FALLING
COMP_EXTI_IT
COMP_EXTI_LINE_COMP1
COMP_EXTI_LINE_COMP2
COMP_EXTI_LINE_COMP3
COMP_EXTI_LINE_COMP4
COMP_EXTI_LINE_COMP5
COMP_EXTI_LINE_COMP6
COMP_EXTI_LINE_COMP7
COMP_EXTI_RISING
COMP_GET_EXTI_LINE
COMP_HYSTERESIS_10MV
COMP_HYSTERESIS_20MV
COMP_HYSTERESIS_30MV
COMP_HYSTERESIS_40MV
COMP_HYSTERESIS_50MV
COMP_HYSTERESIS_60MV
COMP_HYSTERESIS_70MV
COMP_HYSTERESIS_HIGH
COMP_HYSTERESIS_LOW
COMP_HYSTERESIS_MEDIUM
COMP_HYSTERESIS_NONE
COMP_INPUT_MINUS_1_2VREFINT
COMP_INPUT_MINUS_1_4VREFINT
COMP_INPUT_MINUS_3_4VREFINT
COMP_INPUT_MINUS_DAC1_CH1
COMP_INPUT_MINUS_DAC1_CH2
COMP_INPUT_MINUS_DAC2_CH1
COMP_INPUT_MINUS_DAC3_CH1
COMP_INPUT_MINUS_DAC3_CH2
COMP_INPUT_MINUS_DAC4_CH1
COMP_INPUT_MINUS_DAC4_CH2
COMP_INPUT_MINUS_IO1
COMP_INPUT_MINUS_IO2
COMP_INPUT_MINUS_VREFINT
COMP_INPUT_PLUS_IO1
COMP_INPUT_PLUS_IO2
COMP_OUTPUT_LEVEL_HIGH
COMP_OUTPUT_LEVEL_LOW
COMP_OUTPUTPOL_INVERTED
COMP_OUTPUTPOL_NONINVERTED
COMP_STATE_BITFIELD_LOCK
COMP_TRIGGERMODE_EVENT_FALLING
COMP_TRIGGERMODE_EVENT_RISING
COMP_TRIGGERMODE_EVENT_RISING_FALLING
COMP_TRIGGERMODE_IT_FALLING
COMP_TRIGGERMODE_IT_RISING
COMP_TRIGGERMODE_IT_RISING_FALLING
COMP_TRIGGERMODE_NONE
HAL_COMP_ERROR_INVALID_CALLBACK
HAL_COMP_ERROR_NONE
IS_COMP_BLANKINGSRC_INSTANCE
IS_COMP_BLANKINGSRCE
IS_COMP_HYSTERESIS
IS_COMP_INPUT_MINUS
IS_COMP_INPUT_PLUS
IS_COMP_OUTPUT_LEVEL
IS_COMP_OUTPUTPOL
IS_COMP_TRIGGERMODE
COMP_HandleTypeDef
pCOMP_CallbackTypeDef
HAL_COMP_CallbackIDTypeDef
HAL_COMP_StateTypeDef
HAL_COMP_DeInit
HAL_COMP_GetError
HAL_COMP_GetOutputLevel
HAL_COMP_GetState
HAL_COMP_Init
HAL_COMP_IRQHandler
HAL_COMP_Lock
HAL_COMP_MspDeInit
HAL_COMP_MspInit
HAL_COMP_RegisterCallback
HAL_COMP_Start
HAL_COMP_Stop
HAL_COMP_TriggerCallback
HAL_COMP_UnRegisterCallback
stm32g4xx_hal_conf.h
DATA_CACHE_ENABLE
EXTERNAL_CLOCK_VALUE
HAL_ADC_MODULE_ENABLED
HAL_COMP_MODULE_ENABLED
HAL_CORDIC_MODULE_ENABLED
HAL_CORTEX_MODULE_ENABLED
HAL_CRC_MODULE_ENABLED
HAL_CRYP_MODULE_ENABLED
HAL_DAC_MODULE_ENABLED
HAL_DMA_MODULE_ENABLED
HAL_EXTI_MODULE_ENABLED
HAL_FDCAN_MODULE_ENABLED
HAL_FLASH_MODULE_ENABLED
HAL_FMAC_MODULE_ENABLED
HAL_GPIO_MODULE_ENABLED
HAL_HRTIM_MODULE_ENABLED
HAL_I2C_MODULE_ENABLED
HAL_I2S_MODULE_ENABLED
HAL_IRDA_MODULE_ENABLED
HAL_IWDG_MODULE_ENABLED
HAL_LPTIM_MODULE_ENABLED
HAL_MODULE_ENABLED
HAL_NAND_MODULE_ENABLED
HAL_NOR_MODULE_ENABLED
HAL_OPAMP_MODULE_ENABLED
HAL_PCD_MODULE_ENABLED
HAL_PWR_MODULE_ENABLED
HAL_QSPI_MODULE_ENABLED
HAL_RCC_MODULE_ENABLED
HAL_RNG_MODULE_ENABLED
HAL_RTC_MODULE_ENABLED
HAL_SAI_MODULE_ENABLED
HAL_SMARTCARD_MODULE_ENABLED
HAL_SMBUS_MODULE_ENABLED
HAL_SPI_MODULE_ENABLED
HAL_SRAM_MODULE_ENABLED
HAL_TIM_MODULE_ENABLED
HAL_UART_MODULE_ENABLED
HAL_USART_MODULE_ENABLED
HAL_WWDG_MODULE_ENABLED
HSE_STARTUP_TIMEOUT
HSE_VALUE
HSI48_VALUE
HSI_VALUE
INSTRUCTION_CACHE_ENABLE
LSE_STARTUP_TIMEOUT
LSE_VALUE
LSI_VALUE
PREFETCH_ENABLE
TICK_INT_PRIORITY
USE_HAL_ADC_REGISTER_CALLBACKS
USE_HAL_COMP_REGISTER_CALLBACKS
USE_HAL_CORDIC_REGISTER_CALLBACKS
USE_HAL_CRYP_REGISTER_CALLBACKS
USE_HAL_DAC_REGISTER_CALLBACKS
USE_HAL_EXTI_REGISTER_CALLBACKS
USE_HAL_FDCAN_REGISTER_CALLBACKS
USE_HAL_FMAC_REGISTER_CALLBACKS
USE_HAL_HRTIM_REGISTER_CALLBACKS
USE_HAL_I2C_REGISTER_CALLBACKS
USE_HAL_I2S_REGISTER_CALLBACKS
USE_HAL_IRDA_REGISTER_CALLBACKS
USE_HAL_LPTIM_REGISTER_CALLBACKS
USE_HAL_NAND_REGISTER_CALLBACKS
USE_HAL_NOR_REGISTER_CALLBACKS
USE_HAL_OPAMP_REGISTER_CALLBACKS
USE_HAL_PCD_REGISTER_CALLBACKS
USE_HAL_QSPI_REGISTER_CALLBACKS
USE_HAL_RNG_REGISTER_CALLBACKS
USE_HAL_RTC_REGISTER_CALLBACKS
USE_HAL_SAI_REGISTER_CALLBACKS
USE_HAL_SMARTCARD_REGISTER_CALLBACKS
USE_HAL_SMBUS_REGISTER_CALLBACKS
USE_HAL_SPI_REGISTER_CALLBACKS
USE_HAL_SRAM_REGISTER_CALLBACKS
USE_HAL_TIM_REGISTER_CALLBACKS
USE_HAL_UART_REGISTER_CALLBACKS
USE_HAL_USART_REGISTER_CALLBACKS
USE_HAL_WWDG_REGISTER_CALLBACKS
USE_RTOS
USE_SPI_CRC
VDD_VALUE
stm32g4xx_hal_cordic.c
CORDIC_DMAInCplt
CORDIC_DMAOutCplt
CORDIC_ReadOutDataIncrementPtr
CORDIC_WriteInDataIncrementPtr
HAL_CORDIC_Calculate
HAL_CORDIC_Calculate_DMA
HAL_CORDIC_Calculate_IT
HAL_CORDIC_CalculateCpltCallback
HAL_CORDIC_CalculateZO
HAL_CORDIC_Configure
HAL_CORDIC_DeInit
HAL_CORDIC_ErrorCallback
HAL_CORDIC_GetError
HAL_CORDIC_GetState
HAL_CORDIC_Init
HAL_CORDIC_IRQHandler
HAL_CORDIC_MspDeInit
HAL_CORDIC_MspInit
HAL_CORDIC_RegisterCallback
HAL_CORDIC_UnRegisterCallback
stm32g4xx_hal_cordic.h
__HAL_CORDIC_CLEAR_IT
__HAL_CORDIC_DISABLE_IT
__HAL_CORDIC_ENABLE_IT
__HAL_CORDIC_GET_FLAG
__HAL_CORDIC_GET_IT
__HAL_CORDIC_GET_IT_SOURCE
__HAL_CORDIC_RESET_HANDLE_STATE
CORDIC_DMA_DIR_IN
CORDIC_DMA_DIR_IN_OUT
CORDIC_DMA_DIR_NONE
CORDIC_DMA_DIR_OUT
CORDIC_DMA_REN
CORDIC_DMA_WEN
CORDIC_FLAG_RRDY
CORDIC_FUNCTION_ARCTANGENT
CORDIC_FUNCTION_COSINE
CORDIC_FUNCTION_HARCTANGENT
CORDIC_FUNCTION_HCOSINE
CORDIC_FUNCTION_HSINE
CORDIC_FUNCTION_MODULUS
CORDIC_FUNCTION_NATURALLOG
CORDIC_FUNCTION_PHASE
CORDIC_FUNCTION_SINE
CORDIC_FUNCTION_SQUAREROOT
CORDIC_INSIZE_16BITS
CORDIC_INSIZE_32BITS
CORDIC_IT_IEN
CORDIC_NBREAD_1
CORDIC_NBREAD_2
CORDIC_NBWRITE_1
CORDIC_NBWRITE_2
CORDIC_OUTSIZE_16BITS
CORDIC_OUTSIZE_32BITS
CORDIC_PRECISION_10CYCLES
CORDIC_PRECISION_11CYCLES
CORDIC_PRECISION_12CYCLES
CORDIC_PRECISION_13CYCLES
CORDIC_PRECISION_14CYCLES
CORDIC_PRECISION_15CYCLES
CORDIC_PRECISION_1CYCLE
CORDIC_PRECISION_2CYCLES
CORDIC_PRECISION_3CYCLES
CORDIC_PRECISION_4CYCLES
CORDIC_PRECISION_5CYCLES
CORDIC_PRECISION_6CYCLES
CORDIC_PRECISION_7CYCLES
CORDIC_PRECISION_8CYCLES
CORDIC_PRECISION_9CYCLES
CORDIC_SCALE_0
CORDIC_SCALE_1
CORDIC_SCALE_2
CORDIC_SCALE_3
CORDIC_SCALE_4
CORDIC_SCALE_5
CORDIC_SCALE_6
CORDIC_SCALE_7
HAL_CORDIC_ERROR_DMA
HAL_CORDIC_ERROR_INVALID_CALLBACK
HAL_CORDIC_ERROR_NONE
HAL_CORDIC_ERROR_NOT_READY
HAL_CORDIC_ERROR_PARAM
HAL_CORDIC_ERROR_TIMEOUT
IS_CORDIC_DMA_DIRECTION
IS_CORDIC_FUNCTION
IS_CORDIC_INSIZE
IS_CORDIC_NBREAD
IS_CORDIC_NBWRITE
IS_CORDIC_OUTSIZE
IS_CORDIC_PRECISION
IS_CORDIC_SCALE
CORDIC_HandleTypeDef
pCORDIC_CallbackTypeDef
HAL_CORDIC_CallbackIDTypeDef
HAL_CORDIC_StateTypeDef
HAL_CORDIC_Calculate
HAL_CORDIC_Calculate_DMA
HAL_CORDIC_Calculate_IT
HAL_CORDIC_CalculateCpltCallback
HAL_CORDIC_CalculateZO
HAL_CORDIC_Configure
HAL_CORDIC_DeInit
HAL_CORDIC_ErrorCallback
HAL_CORDIC_GetError
HAL_CORDIC_GetState
HAL_CORDIC_Init
HAL_CORDIC_IRQHandler
HAL_CORDIC_MspDeInit
HAL_CORDIC_MspInit
HAL_CORDIC_RegisterCallback
HAL_CORDIC_UnRegisterCallback
stm32g4xx_hal_cortex.c
HAL_MPU_Disable
HAL_MPU_DisableRegion
HAL_MPU_Enable
HAL_MPU_EnableRegion
HAL_NVIC_ClearPendingIRQ
HAL_NVIC_DisableIRQ
HAL_NVIC_EnableIRQ
HAL_NVIC_GetActive
HAL_NVIC_GetPendingIRQ
HAL_NVIC_GetPriority
HAL_NVIC_GetPriorityGrouping
HAL_NVIC_SetPendingIRQ
HAL_NVIC_SetPriority
HAL_NVIC_SetPriorityGrouping
HAL_NVIC_SystemReset
HAL_SYSTICK_Callback
HAL_SYSTICK_CLKSourceConfig
HAL_SYSTICK_Config
HAL_SYSTICK_IRQHandler
stm32g4xx_hal_cortex.h
IS_MPU_ACCESS_CACHEABLE
IS_MPU_ACCESS_SHAREABLE
IS_MPU_INSTRUCTION_ACCESS
IS_MPU_REGION_ENABLE
IS_MPU_REGION_NUMBER
IS_MPU_REGION_PERMISSION_ATTRIBUTE
IS_MPU_REGION_SIZE
IS_MPU_SUB_REGION_DISABLE
IS_MPU_TEX_LEVEL
IS_NVIC_DEVICE_IRQ
IS_NVIC_PREEMPTION_PRIORITY
IS_NVIC_PRIORITY_GROUP
IS_NVIC_SUB_PRIORITY
IS_SYSTICK_CLK_SOURCE
MPU_ACCESS_BUFFERABLE
MPU_ACCESS_CACHEABLE
MPU_ACCESS_NOT_BUFFERABLE
MPU_ACCESS_NOT_CACHEABLE
MPU_ACCESS_NOT_SHAREABLE
MPU_ACCESS_SHAREABLE
MPU_HARDFAULT_NMI
MPU_HFNMI_PRIVDEF
MPU_HFNMI_PRIVDEF_NONE
MPU_INSTRUCTION_ACCESS_DISABLE
MPU_INSTRUCTION_ACCESS_ENABLE
MPU_PRIVILEGED_DEFAULT
MPU_REGION_DISABLE
MPU_REGION_ENABLE
MPU_REGION_FULL_ACCESS
MPU_REGION_NO_ACCESS
MPU_REGION_NUMBER0
MPU_REGION_NUMBER1
MPU_REGION_NUMBER2
MPU_REGION_NUMBER3
MPU_REGION_NUMBER4
MPU_REGION_NUMBER5
MPU_REGION_NUMBER6
MPU_REGION_NUMBER7
MPU_REGION_PRIV_RO
MPU_REGION_PRIV_RO_URO
MPU_REGION_PRIV_RW
MPU_REGION_PRIV_RW_URO
MPU_REGION_SIZE_128B
MPU_REGION_SIZE_128KB
MPU_REGION_SIZE_128MB
MPU_REGION_SIZE_16KB
MPU_REGION_SIZE_16MB
MPU_REGION_SIZE_1GB
MPU_REGION_SIZE_1KB
MPU_REGION_SIZE_1MB
MPU_REGION_SIZE_256B
MPU_REGION_SIZE_256KB
MPU_REGION_SIZE_256MB
MPU_REGION_SIZE_2GB
MPU_REGION_SIZE_2KB
MPU_REGION_SIZE_2MB
MPU_REGION_SIZE_32B
MPU_REGION_SIZE_32KB
MPU_REGION_SIZE_32MB
MPU_REGION_SIZE_4GB
MPU_REGION_SIZE_4KB
MPU_REGION_SIZE_4MB
MPU_REGION_SIZE_512B
MPU_REGION_SIZE_512KB
MPU_REGION_SIZE_512MB
MPU_REGION_SIZE_64B
MPU_REGION_SIZE_64KB
MPU_REGION_SIZE_64MB
MPU_REGION_SIZE_8KB
MPU_REGION_SIZE_8MB
MPU_TEX_LEVEL0
MPU_TEX_LEVEL1
MPU_TEX_LEVEL2
MPU_TEX_LEVEL4
NVIC_PRIORITYGROUP_0
NVIC_PRIORITYGROUP_1
NVIC_PRIORITYGROUP_2
NVIC_PRIORITYGROUP_3
NVIC_PRIORITYGROUP_4
SYSTICK_CLKSOURCE_HCLK
SYSTICK_CLKSOURCE_HCLK_DIV8
HAL_MPU_ConfigRegion
HAL_MPU_Disable
HAL_MPU_DisableRegion
HAL_MPU_Enable
HAL_MPU_EnableRegion
HAL_NVIC_ClearPendingIRQ
HAL_NVIC_DisableIRQ
HAL_NVIC_EnableIRQ
HAL_NVIC_GetActive
HAL_NVIC_GetPendingIRQ
HAL_NVIC_GetPriority
HAL_NVIC_GetPriorityGrouping
HAL_NVIC_SetPendingIRQ
HAL_NVIC_SetPriority
HAL_NVIC_SetPriorityGrouping
HAL_NVIC_SystemReset
HAL_SYSTICK_Callback
HAL_SYSTICK_CLKSourceConfig
HAL_SYSTICK_Config
HAL_SYSTICK_IRQHandler
stm32g4xx_hal_crc.c
CRC_Handle_8
HAL_CRC_Accumulate
HAL_CRC_Calculate
HAL_CRC_DeInit
HAL_CRC_GetState
HAL_CRC_Init
HAL_CRC_MspDeInit
HAL_CRC_MspInit
stm32g4xx_hal_crc.h
__HAL_CRC_GET_IDR
__HAL_CRC_INITIALCRCVALUE_CONFIG
__HAL_CRC_RESET_HANDLE_STATE
__HAL_CRC_SET_IDR
CRC_INPUTDATA_FORMAT_BYTES
CRC_INPUTDATA_FORMAT_HALFWORDS
CRC_INPUTDATA_FORMAT_UNDEFINED
CRC_INPUTDATA_FORMAT_WORDS
CRC_POLYLENGTH_16B
CRC_POLYLENGTH_32B
CRC_POLYLENGTH_7B
CRC_POLYLENGTH_8B
DEFAULT_CRC32_POLY
DEFAULT_CRC_INITVALUE
DEFAULT_INIT_VALUE_DISABLE
DEFAULT_INIT_VALUE_ENABLE
DEFAULT_POLYNOMIAL_DISABLE
DEFAULT_POLYNOMIAL_ENABLE
HAL_CRC_LENGTH_16B
HAL_CRC_LENGTH_32B
HAL_CRC_LENGTH_7B
HAL_CRC_LENGTH_8B
IS_CRC_INPUTDATA_FORMAT
IS_CRC_POL_LENGTH
IS_DEFAULT_INIT_VALUE
IS_DEFAULT_POLYNOMIAL
HAL_CRC_StateTypeDef
HAL_CRC_Accumulate
HAL_CRC_Calculate
HAL_CRC_DeInit
HAL_CRC_GetState
HAL_CRC_Init
HAL_CRC_MspDeInit
HAL_CRC_MspInit
stm32g4xx_hal_crc_ex.c
HAL_CRCEx_Output_Data_Reverse
HAL_CRCEx_Polynomial_Set
stm32g4xx_hal_crc_ex.h
__HAL_CRC_OUTPUTREVERSAL_ENABLE
__HAL_CRC_POLYNOMIAL_CONFIG
CRC_INPUTDATA_INVERSION_BYTE
CRC_INPUTDATA_INVERSION_HALFWORD
CRC_INPUTDATA_INVERSION_NONE
CRC_INPUTDATA_INVERSION_WORD
CRC_OUTPUTDATA_INVERSION_DISABLE
CRC_OUTPUTDATA_INVERSION_ENABLE
IS_CRC_INPUTDATA_INVERSION_MODE
IS_CRC_OUTPUTDATA_INVERSION_MODE
HAL_CRCEx_Input_Data_Reverse
HAL_CRCEx_Output_Data_Reverse
HAL_CRCEx_Polynomial_Set
stm32g4xx_hal_cryp.c
stm32g4xx_hal_cryp.h
stm32g4xx_hal_cryp_ex.c
stm32g4xx_hal_cryp_ex.h
stm32g4xx_hal_dac.c
HFSEL_ENABLE_THRESHOLD_80MHZ
TIMEOUT_DAC_CALIBCONFIG
DAC_DMAConvCpltCh1
DAC_DMAErrorCh1
DAC_DMAHalfConvCpltCh1
HAL_DAC_ConfigChannel
HAL_DAC_ConvCpltCallbackCh1
HAL_DAC_ConvHalfCpltCallbackCh1
HAL_DAC_DeInit
HAL_DAC_DMAUnderrunCallbackCh1
HAL_DAC_ErrorCallbackCh1
HAL_DAC_GetError
HAL_DAC_GetState
HAL_DAC_GetValue
HAL_DAC_Init
HAL_DAC_IRQHandler
HAL_DAC_MspDeInit
HAL_DAC_MspInit
HAL_DAC_RegisterCallback
HAL_DAC_SetValue
HAL_DAC_Start
HAL_DAC_Start_DMA
HAL_DAC_Stop
HAL_DAC_Stop_DMA
HAL_DAC_UnRegisterCallback
stm32g4xx_hal_dac.h
__HAL_DAC_DISABLE
__HAL_DAC_DISABLE_IT
__HAL_DAC_ENABLE
__HAL_DAC_ENABLE_IT
__HAL_DAC_GET_FLAG
__HAL_DAC_GET_IT_SOURCE
__HAL_DAC_RESET_HANDLE_STATE
DAC_ALIGN_12B_L
DAC_ALIGN_12B_R
DAC_ALIGN_8B_R
DAC_CHANNEL_1
DAC_CHANNEL_2
DAC_CHIPCONNECT_BOTH
DAC_CHIPCONNECT_EXTERNAL
DAC_CHIPCONNECT_INTERNAL
DAC_DELAY_STARTUP_US
DAC_DHR12R1_ALIGNMENT
DAC_DHR12R2_ALIGNMENT
DAC_DHR12RD_ALIGNMENT
DAC_FLAG_DAC1RDY
DAC_FLAG_DAC2RDY
DAC_FLAG_DMAUDR1
DAC_FLAG_DMAUDR2
DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ
DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ
DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC
DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE
DAC_IT_DMAUDR1
DAC_IT_DMAUDR2
DAC_OUTPUTBUFFER_DISABLE
DAC_OUTPUTBUFFER_ENABLE
DAC_SAMPLEANDHOLD_DISABLE
DAC_SAMPLEANDHOLD_ENABLE
DAC_TRIGGER_EXT_IT10
DAC_TRIGGER_EXT_IT9
DAC_TRIGGER_HRTIM_RST_TRG1
DAC_TRIGGER_HRTIM_RST_TRG2
DAC_TRIGGER_HRTIM_RST_TRG3
DAC_TRIGGER_HRTIM_RST_TRG4
DAC_TRIGGER_HRTIM_RST_TRG5
DAC_TRIGGER_HRTIM_RST_TRG6
DAC_TRIGGER_HRTIM_STEP_TRG1
DAC_TRIGGER_HRTIM_STEP_TRG2
DAC_TRIGGER_HRTIM_STEP_TRG3
DAC_TRIGGER_HRTIM_STEP_TRG4
DAC_TRIGGER_HRTIM_STEP_TRG5
DAC_TRIGGER_HRTIM_STEP_TRG6
DAC_TRIGGER_HRTIM_TRG01
DAC_TRIGGER_HRTIM_TRG02
DAC_TRIGGER_HRTIM_TRG03
DAC_TRIGGER_NONE
DAC_TRIGGER_SOFTWARE
DAC_TRIGGER_T15_TRGO
DAC_TRIGGER_T1_TRGO
DAC_TRIGGER_T2_TRGO
DAC_TRIGGER_T3_TRGO
DAC_TRIGGER_T4_TRGO
DAC_TRIGGER_T6_TRGO
DAC_TRIGGER_T7_TRGO
DAC_TRIGGER_T8_TRGO
DAC_TRIMMING_FACTORY
DAC_TRIMMING_USER
HAL_DAC_ERROR_DMA
HAL_DAC_ERROR_DMAUNDERRUNCH1
HAL_DAC_ERROR_DMAUNDERRUNCH2
HAL_DAC_ERROR_INVALID_CALLBACK
HAL_DAC_ERROR_NONE
HAL_DAC_ERROR_TIMEOUT
IS_DAC_ALIGN
IS_DAC_CHANNEL
IS_DAC_DATA
IS_DAC_OUTPUT_BUFFER_STATE
IS_DAC_REFRESHTIME
DAC_HandleTypeDef
pDAC_CallbackTypeDef
HAL_DAC_CallbackIDTypeDef
HAL_DAC_StateTypeDef
DAC_DMAConvCpltCh1
DAC_DMAErrorCh1
DAC_DMAHalfConvCpltCh1
HAL_DAC_ConfigChannel
HAL_DAC_ConvCpltCallbackCh1
HAL_DAC_ConvHalfCpltCallbackCh1
HAL_DAC_DeInit
HAL_DAC_DMAUnderrunCallbackCh1
HAL_DAC_ErrorCallbackCh1
HAL_DAC_GetError
HAL_DAC_GetState
HAL_DAC_GetValue
HAL_DAC_Init
HAL_DAC_IRQHandler
HAL_DAC_MspDeInit
HAL_DAC_MspInit
HAL_DAC_RegisterCallback
HAL_DAC_SetValue
HAL_DAC_Start
HAL_DAC_Start_DMA
HAL_DAC_Stop
HAL_DAC_Stop_DMA
HAL_DAC_UnRegisterCallback
stm32g4xx_hal_dac_ex.c
DAC_DMAConvCpltCh2
DAC_DMAErrorCh2
DAC_DMAHalfConvCpltCh2
HAL_DACEx_ConvCpltCallbackCh2
HAL_DACEx_ConvHalfCpltCallbackCh2
HAL_DACEx_DMAUnderrunCallbackCh2
HAL_DACEx_DualGetValue
HAL_DACEx_DualSetValue
HAL_DACEx_DualStart
HAL_DACEx_DualStart_DMA
HAL_DACEx_DualStop
HAL_DACEx_DualStop_DMA
HAL_DACEx_ErrorCallbackCh2
HAL_DACEx_GetTrimOffset
HAL_DACEx_NoiseWaveGenerate
HAL_DACEx_SawtoothWaveDataReset
HAL_DACEx_SawtoothWaveDataStep
HAL_DACEx_SawtoothWaveGenerate
HAL_DACEx_SelfCalibrate
HAL_DACEx_SetUserTrimming
HAL_DACEx_TriangleWaveGenerate
stm32g4xx_hal_dac_ex.h
DAC_LFSRUNMASK_BITS10_0
DAC_LFSRUNMASK_BITS11_0
DAC_LFSRUNMASK_BITS1_0
DAC_LFSRUNMASK_BITS2_0
DAC_LFSRUNMASK_BITS3_0
DAC_LFSRUNMASK_BITS4_0
DAC_LFSRUNMASK_BITS5_0
DAC_LFSRUNMASK_BITS6_0
DAC_LFSRUNMASK_BITS7_0
DAC_LFSRUNMASK_BITS8_0
DAC_LFSRUNMASK_BITS9_0
DAC_SAWTOOTH_POLARITY_DECREMENT
DAC_SAWTOOTH_POLARITY_INCREMENT
DAC_TRIANGLEAMPLITUDE_1
DAC_TRIANGLEAMPLITUDE_1023
DAC_TRIANGLEAMPLITUDE_127
DAC_TRIANGLEAMPLITUDE_15
DAC_TRIANGLEAMPLITUDE_2047
DAC_TRIANGLEAMPLITUDE_255
DAC_TRIANGLEAMPLITUDE_3
DAC_TRIANGLEAMPLITUDE_31
DAC_TRIANGLEAMPLITUDE_4095
DAC_TRIANGLEAMPLITUDE_511
DAC_TRIANGLEAMPLITUDE_63
DAC_TRIANGLEAMPLITUDE_7
IS_DAC_CHIP_CONNECTION
IS_DAC_HIGH_FREQUENCY_MODE
IS_DAC_HOLDTIME
IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE
IS_DAC_NEWTRIMMINGVALUE
IS_DAC_RESET_DATA
IS_DAC_SAMPLEANDHOLD
IS_DAC_SAMPLETIME
IS_DAC_SAWTOOTH_POLARITY
IS_DAC_STEP_DATA
IS_DAC_TRIGGER
IS_DAC_TRIGGER2
IS_DAC_TRIMMING
IS_DAC_TRIMMINGVALUE
DAC_DMAConvCpltCh2
DAC_DMAErrorCh2
DAC_DMAHalfConvCpltCh2
HAL_DACEx_ConvCpltCallbackCh2
HAL_DACEx_ConvHalfCpltCallbackCh2
HAL_DACEx_DMAUnderrunCallbackCh2
HAL_DACEx_DualGetValue
HAL_DACEx_DualSetValue
HAL_DACEx_DualStart
HAL_DACEx_DualStart_DMA
HAL_DACEx_DualStop
HAL_DACEx_DualStop_DMA
HAL_DACEx_ErrorCallbackCh2
HAL_DACEx_GetTrimOffset
HAL_DACEx_NoiseWaveGenerate
HAL_DACEx_SawtoothWaveDataReset
HAL_DACEx_SawtoothWaveDataStep
HAL_DACEx_SawtoothWaveGenerate
HAL_DACEx_SelfCalibrate
HAL_DACEx_SetUserTrimming
HAL_DACEx_TriangleWaveGenerate
stm32g4xx_hal_dma.c
DMA_CalcDMAMUXRequestGenBaseAndMask
DMA_SetConfig
HAL_DMA_Abort
HAL_DMA_Abort_IT
HAL_DMA_DeInit
HAL_DMA_GetError
HAL_DMA_GetState
HAL_DMA_Init
HAL_DMA_IRQHandler
HAL_DMA_PollForTransfer
HAL_DMA_RegisterCallback
HAL_DMA_Start
HAL_DMA_Start_IT
HAL_DMA_UnRegisterCallback
stm32g4xx_hal_dma.h
__HAL_DMA_DISABLE
__HAL_DMA_DISABLE_IT
__HAL_DMA_ENABLE
__HAL_DMA_ENABLE_IT
__HAL_DMA_GET_COUNTER
__HAL_DMA_GET_FLAG
__HAL_DMA_GET_GI_FLAG_INDEX
__HAL_DMA_GET_HT_FLAG_INDEX
__HAL_DMA_GET_IT_SOURCE
__HAL_DMA_GET_TC_FLAG_INDEX
__HAL_DMA_GET_TE_FLAG_INDEX
__HAL_DMA_RESET_HANDLE_STATE
DMA_CIRCULAR
DMA_FLAG_GL1
DMA_FLAG_GL2
DMA_FLAG_GL3
DMA_FLAG_GL4
DMA_FLAG_GL5
DMA_FLAG_GL6
DMA_FLAG_GL7
DMA_FLAG_GL8
DMA_FLAG_HT1
DMA_FLAG_HT2
DMA_FLAG_HT3
DMA_FLAG_HT4
DMA_FLAG_HT5
DMA_FLAG_HT6
DMA_FLAG_HT7
DMA_FLAG_HT8
DMA_FLAG_TC1
DMA_FLAG_TC2
DMA_FLAG_TC3
DMA_FLAG_TC4
DMA_FLAG_TC5
DMA_FLAG_TC6
DMA_FLAG_TC7
DMA_FLAG_TC8
DMA_FLAG_TE1
DMA_FLAG_TE2
DMA_FLAG_TE3
DMA_FLAG_TE4
DMA_FLAG_TE5
DMA_FLAG_TE6
DMA_FLAG_TE7
DMA_FLAG_TE8
DMA_IT_HT
DMA_IT_TC
DMA_IT_TE
DMA_MDATAALIGN_BYTE
DMA_MDATAALIGN_HALFWORD
DMA_MDATAALIGN_WORD
DMA_MEMORY_TO_MEMORY
DMA_MEMORY_TO_PERIPH
DMA_MINC_DISABLE
DMA_MINC_ENABLE
DMA_NORMAL
DMA_PDATAALIGN_BYTE
DMA_PDATAALIGN_HALFWORD
DMA_PDATAALIGN_WORD
DMA_PERIPH_TO_MEMORY
DMA_PINC_DISABLE
DMA_PINC_ENABLE
DMA_PRIORITY_HIGH
DMA_PRIORITY_LOW
DMA_PRIORITY_MEDIUM
DMA_PRIORITY_VERY_HIGH
DMA_REQUEST_ADC1
DMA_REQUEST_ADC2
DMA_REQUEST_ADC3
DMA_REQUEST_ADC4
DMA_REQUEST_ADC5
DMA_REQUEST_AES_IN
DMA_REQUEST_AES_OUT
DMA_REQUEST_CORDIC_READ
DMA_REQUEST_CORDIC_WRITE
DMA_REQUEST_DAC1_CHANNEL1
DMA_REQUEST_DAC1_CHANNEL2
DMA_REQUEST_DAC2_CHANNEL1
DMA_REQUEST_DAC3_CHANNEL1
DMA_REQUEST_DAC3_CHANNEL2
DMA_REQUEST_DAC4_CHANNEL1
DMA_REQUEST_DAC4_CHANNEL2
DMA_REQUEST_FMAC_READ
DMA_REQUEST_FMAC_WRITE
DMA_REQUEST_GENERATOR0
DMA_REQUEST_GENERATOR1
DMA_REQUEST_GENERATOR2
DMA_REQUEST_GENERATOR3
DMA_REQUEST_HRTIM1_A
DMA_REQUEST_HRTIM1_B
DMA_REQUEST_HRTIM1_C
DMA_REQUEST_HRTIM1_D
DMA_REQUEST_HRTIM1_E
DMA_REQUEST_HRTIM1_F
DMA_REQUEST_HRTIM1_M
DMA_REQUEST_I2C1_RX
DMA_REQUEST_I2C1_TX
DMA_REQUEST_I2C2_RX
DMA_REQUEST_I2C2_TX
DMA_REQUEST_I2C3_RX
DMA_REQUEST_I2C3_TX
DMA_REQUEST_I2C4_RX
DMA_REQUEST_I2C4_TX
DMA_REQUEST_LPUART1_RX
DMA_REQUEST_LPUART1_TX
DMA_REQUEST_MEM2MEM
DMA_REQUEST_QUADSPI
DMA_REQUEST_SAI1_A
DMA_REQUEST_SAI1_B
DMA_REQUEST_SPI1_RX
DMA_REQUEST_SPI1_TX
DMA_REQUEST_SPI2_RX
DMA_REQUEST_SPI2_TX
DMA_REQUEST_SPI3_RX
DMA_REQUEST_SPI3_TX
DMA_REQUEST_SPI4_RX
DMA_REQUEST_SPI4_TX
DMA_REQUEST_TIM15_CH1
DMA_REQUEST_TIM15_COM
DMA_REQUEST_TIM15_TRIG
DMA_REQUEST_TIM15_UP
DMA_REQUEST_TIM16_CH1
DMA_REQUEST_TIM16_UP
DMA_REQUEST_TIM17_CH1
DMA_REQUEST_TIM17_UP
DMA_REQUEST_TIM1_CH1
DMA_REQUEST_TIM1_CH2
DMA_REQUEST_TIM1_CH3
DMA_REQUEST_TIM1_CH4
DMA_REQUEST_TIM1_COM
DMA_REQUEST_TIM1_TRIG
DMA_REQUEST_TIM1_UP
DMA_REQUEST_TIM20_CH1
DMA_REQUEST_TIM20_CH2
DMA_REQUEST_TIM20_CH3
DMA_REQUEST_TIM20_CH4
DMA_REQUEST_TIM20_COM
DMA_REQUEST_TIM20_TRIG
DMA_REQUEST_TIM20_UP
DMA_REQUEST_TIM2_CH1
DMA_REQUEST_TIM2_CH2
DMA_REQUEST_TIM2_CH3
DMA_REQUEST_TIM2_CH4
DMA_REQUEST_TIM2_UP
DMA_REQUEST_TIM3_CH1
DMA_REQUEST_TIM3_CH2
DMA_REQUEST_TIM3_CH3
DMA_REQUEST_TIM3_CH4
DMA_REQUEST_TIM3_TRIG
DMA_REQUEST_TIM3_UP
DMA_REQUEST_TIM4_CH1
DMA_REQUEST_TIM4_CH2
DMA_REQUEST_TIM4_CH3
DMA_REQUEST_TIM4_CH4
DMA_REQUEST_TIM4_UP
DMA_REQUEST_TIM5_CH1
DMA_REQUEST_TIM5_CH2
DMA_REQUEST_TIM5_CH3
DMA_REQUEST_TIM5_CH4
DMA_REQUEST_TIM5_TRIG
DMA_REQUEST_TIM5_UP
DMA_REQUEST_TIM6_UP
DMA_REQUEST_TIM7_UP
DMA_REQUEST_TIM8_CH1
DMA_REQUEST_TIM8_CH2
DMA_REQUEST_TIM8_CH3
DMA_REQUEST_TIM8_CH4
DMA_REQUEST_TIM8_COM
DMA_REQUEST_TIM8_TRIG
DMA_REQUEST_TIM8_UP
DMA_REQUEST_UART4_RX
DMA_REQUEST_UART4_TX
DMA_REQUEST_UART5_RX
DMA_REQUEST_UART5_TX
DMA_REQUEST_UCPD1_RX
DMA_REQUEST_UCPD1_TX
DMA_REQUEST_USART1_RX
DMA_REQUEST_USART1_TX
DMA_REQUEST_USART2_RX
DMA_REQUEST_USART2_TX
DMA_REQUEST_USART3_RX
DMA_REQUEST_USART3_TX
HAL_DMA_ERROR_NO_XFER
HAL_DMA_ERROR_NONE
HAL_DMA_ERROR_NOT_SUPPORTED
HAL_DMA_ERROR_REQGEN
HAL_DMA_ERROR_SYNC
HAL_DMA_ERROR_TE
HAL_DMA_ERROR_TIMEOUT
IS_DMA_ALL_REQUEST
IS_DMA_BUFFER_SIZE
IS_DMA_DIRECTION
IS_DMA_MEMORY_DATA_SIZE
IS_DMA_MEMORY_INC_STATE
IS_DMA_MODE
IS_DMA_PERIPHERAL_DATA_SIZE
IS_DMA_PERIPHERAL_INC_STATE
IS_DMA_PRIORITY
DMA_HandleTypeDef
HAL_DMA_CallbackIDTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_StateTypeDef
HAL_DMA_Abort
HAL_DMA_Abort_IT
HAL_DMA_DeInit
HAL_DMA_GetError
HAL_DMA_GetState
HAL_DMA_Init
HAL_DMA_IRQHandler
HAL_DMA_PollForTransfer
HAL_DMA_RegisterCallback
HAL_DMA_Start
HAL_DMA_Start_IT
HAL_DMA_UnRegisterCallback
stm32g4xx_hal_dma_ex.c
HAL_DMAEx_ConfigMuxSync
HAL_DMAEx_DisableMuxRequestGenerator
HAL_DMAEx_EnableMuxRequestGenerator
HAL_DMAEx_MUX_IRQHandler
stm32g4xx_hal_dma_ex.h
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
HAL_DMAMUX1_REQ_GEN_EXTI0
HAL_DMAMUX1_REQ_GEN_EXTI1
HAL_DMAMUX1_REQ_GEN_EXTI10
HAL_DMAMUX1_REQ_GEN_EXTI11
HAL_DMAMUX1_REQ_GEN_EXTI12
HAL_DMAMUX1_REQ_GEN_EXTI13
HAL_DMAMUX1_REQ_GEN_EXTI14
HAL_DMAMUX1_REQ_GEN_EXTI15
HAL_DMAMUX1_REQ_GEN_EXTI2
HAL_DMAMUX1_REQ_GEN_EXTI3
HAL_DMAMUX1_REQ_GEN_EXTI4
HAL_DMAMUX1_REQ_GEN_EXTI5
HAL_DMAMUX1_REQ_GEN_EXTI6
HAL_DMAMUX1_REQ_GEN_EXTI7
HAL_DMAMUX1_REQ_GEN_EXTI8
HAL_DMAMUX1_REQ_GEN_EXTI9
HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT
HAL_DMAMUX1_SYNC_EXTI0
HAL_DMAMUX1_SYNC_EXTI1
HAL_DMAMUX1_SYNC_EXTI10
HAL_DMAMUX1_SYNC_EXTI11
HAL_DMAMUX1_SYNC_EXTI12
HAL_DMAMUX1_SYNC_EXTI13
HAL_DMAMUX1_SYNC_EXTI14
HAL_DMAMUX1_SYNC_EXTI15
HAL_DMAMUX1_SYNC_EXTI2
HAL_DMAMUX1_SYNC_EXTI3
HAL_DMAMUX1_SYNC_EXTI4
HAL_DMAMUX1_SYNC_EXTI5
HAL_DMAMUX1_SYNC_EXTI6
HAL_DMAMUX1_SYNC_EXTI7
HAL_DMAMUX1_SYNC_EXTI8
HAL_DMAMUX1_SYNC_EXTI9
HAL_DMAMUX1_SYNC_LPTIM1_OUT
HAL_DMAMUX_REQ_GEN_FALLING
HAL_DMAMUX_REQ_GEN_NO_EVENT
HAL_DMAMUX_REQ_GEN_RISING
HAL_DMAMUX_REQ_GEN_RISING_FALLING
HAL_DMAMUX_SYNC_FALLING
HAL_DMAMUX_SYNC_NO_EVENT
HAL_DMAMUX_SYNC_RISING
HAL_DMAMUX_SYNC_RISING_FALLING
IS_DMAMUX_REQUEST_GEN_POLARITY
IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER
IS_DMAMUX_REQUEST_GEN_SIGNAL_ID
IS_DMAMUX_SYNC_EVENT
IS_DMAMUX_SYNC_POLARITY
IS_DMAMUX_SYNC_REQUEST_NUMBER
IS_DMAMUX_SYNC_SIGNAL_ID
IS_DMAMUX_SYNC_STATE
HAL_DMAEx_ConfigMuxRequestGenerator
HAL_DMAEx_ConfigMuxSync
HAL_DMAEx_DisableMuxRequestGenerator
HAL_DMAEx_EnableMuxRequestGenerator
HAL_DMAEx_MUX_IRQHandler
stm32g4xx_hal_exti.c
EXTI_MODE_OFFSET
HAL_EXTI_ClearConfigLine
HAL_EXTI_ClearPending
HAL_EXTI_GenerateSWI
HAL_EXTI_GetConfigLine
HAL_EXTI_GetHandle
HAL_EXTI_GetPending
HAL_EXTI_IRQHandler
HAL_EXTI_RegisterCallback
HAL_EXTI_SetConfigLine
stm32g4xx_hal_exti.h
EXTI_DIRECT
EXTI_GPIO
EXTI_GPIOA
EXTI_GPIOB
EXTI_GPIOC
EXTI_GPIOD
EXTI_GPIOE
EXTI_GPIOF
EXTI_GPIOG
EXTI_LINE_0
EXTI_LINE_1
EXTI_LINE_10
EXTI_LINE_11
EXTI_LINE_12
EXTI_LINE_13
EXTI_LINE_14
EXTI_LINE_15
EXTI_LINE_16
EXTI_LINE_17
EXTI_LINE_18
EXTI_LINE_19
EXTI_LINE_2
EXTI_LINE_20
EXTI_LINE_21
EXTI_LINE_22
EXTI_LINE_23
EXTI_LINE_24
EXTI_LINE_25
EXTI_LINE_26
EXTI_LINE_27
EXTI_LINE_28
EXTI_LINE_29
EXTI_LINE_3
EXTI_LINE_30
EXTI_LINE_31
EXTI_LINE_32
EXTI_LINE_33
EXTI_LINE_34
EXTI_LINE_35
EXTI_LINE_36
EXTI_LINE_37
EXTI_LINE_38
EXTI_LINE_39
EXTI_LINE_4
EXTI_LINE_40
EXTI_LINE_41
EXTI_LINE_42
EXTI_LINE_43
EXTI_LINE_5
EXTI_LINE_6
EXTI_LINE_7
EXTI_LINE_8
EXTI_LINE_9
EXTI_LINE_NB
EXTI_MODE_EVENT
EXTI_MODE_INTERRUPT
EXTI_MODE_MASK
EXTI_MODE_NONE
EXTI_PIN_MASK
EXTI_PROPERTY_MASK
EXTI_PROPERTY_SHIFT
EXTI_REG1
EXTI_REG2
EXTI_REG_MASK
EXTI_REG_SHIFT
EXTI_RESERVED
EXTI_TRIGGER_FALLING
EXTI_TRIGGER_MASK
EXTI_TRIGGER_NONE
EXTI_TRIGGER_RISING
EXTI_TRIGGER_RISING_FALLING
IS_EXTI_CB
IS_EXTI_CONFIG_LINE
IS_EXTI_GPIO_PIN
IS_EXTI_GPIO_PORT
IS_EXTI_LINE
IS_EXTI_MODE
IS_EXTI_PENDING_EDGE
IS_EXTI_TRIGGER
EXTI_CallbackIDTypeDef
HAL_EXTI_ClearConfigLine
HAL_EXTI_ClearPending
HAL_EXTI_GenerateSWI
HAL_EXTI_GetConfigLine
HAL_EXTI_GetHandle
HAL_EXTI_GetPending
HAL_EXTI_IRQHandler
HAL_EXTI_RegisterCallback
HAL_EXTI_SetConfigLine
stm32g4xx_hal_fdcan.c
FDCAN_ELEMENT_MASK_BRS
FDCAN_ELEMENT_MASK_DLC
FDCAN_ELEMENT_MASK_EFC
FDCAN_ELEMENT_MASK_ESI
FDCAN_ELEMENT_MASK_ET
FDCAN_ELEMENT_MASK_EXTID
FDCAN_ELEMENT_MASK_FDF
FDCAN_ELEMENT_MASK_FIDX
FDCAN_ELEMENT_MASK_MM
FDCAN_ELEMENT_MASK_RTR
FDCAN_ELEMENT_MASK_STDID
FDCAN_ELEMENT_MASK_TS
FDCAN_ELEMENT_MASK_XTD
FDCAN_ERROR_MASK
FDCAN_ERROR_STATUS_MASK
FDCAN_RX_FIFO0_MASK
FDCAN_RX_FIFO1_MASK
FDCAN_TIMEOUT_VALUE
FDCAN_TX_EVENT_FIFO_MASK
SRAMCAN_FLE_NBR
SRAMCAN_FLE_SIZE
SRAMCAN_FLESA
SRAMCAN_FLS_NBR
SRAMCAN_FLS_SIZE
SRAMCAN_FLSSA
SRAMCAN_RF0_NBR
SRAMCAN_RF0_SIZE
SRAMCAN_RF0SA
SRAMCAN_RF1_NBR
SRAMCAN_RF1_SIZE
SRAMCAN_RF1SA
SRAMCAN_SIZE
SRAMCAN_TEF_NBR
SRAMCAN_TEF_SIZE
SRAMCAN_TEFSA
SRAMCAN_TFQ_NBR
SRAMCAN_TFQ_SIZE
SRAMCAN_TFQSA
FDCAN_CalcultateRamBlockAddresses
FDCAN_CopyMessageToRAM
HAL_FDCAN_AbortTxRequest
HAL_FDCAN_ActivateNotification
HAL_FDCAN_AddMessageToTxFifoQ
HAL_FDCAN_ConfigExtendedIdMask
HAL_FDCAN_ConfigFilter
HAL_FDCAN_ConfigGlobalFilter
HAL_FDCAN_ConfigInterruptLines
HAL_FDCAN_ConfigRamWatchdog
HAL_FDCAN_ConfigRxFifoOverwrite
HAL_FDCAN_ConfigTimeoutCounter
HAL_FDCAN_ConfigTimestampCounter
HAL_FDCAN_ConfigTxDelayCompensation
HAL_FDCAN_DeactivateNotification
HAL_FDCAN_DeInit
HAL_FDCAN_DisableEdgeFiltering
HAL_FDCAN_DisableISOMode
HAL_FDCAN_DisableTimeoutCounter
HAL_FDCAN_DisableTimestampCounter
HAL_FDCAN_DisableTxDelayCompensation
HAL_FDCAN_EnableEdgeFiltering
HAL_FDCAN_EnableISOMode
HAL_FDCAN_EnableTimeoutCounter
HAL_FDCAN_EnableTimestampCounter
HAL_FDCAN_EnableTxDelayCompensation
HAL_FDCAN_EnterPowerDownMode
HAL_FDCAN_ErrorCallback
HAL_FDCAN_ErrorStatusCallback
HAL_FDCAN_ExitPowerDownMode
HAL_FDCAN_ExitRestrictedOperationMode
HAL_FDCAN_GetError
HAL_FDCAN_GetErrorCounters
HAL_FDCAN_GetHighPriorityMessageStatus
HAL_FDCAN_GetLatestTxFifoQRequestBuffer
HAL_FDCAN_GetProtocolStatus
HAL_FDCAN_GetRxFifoFillLevel
HAL_FDCAN_GetRxMessage
HAL_FDCAN_GetState
HAL_FDCAN_GetTimeoutCounter
HAL_FDCAN_GetTimestampCounter
HAL_FDCAN_GetTxEvent
HAL_FDCAN_GetTxFifoFreeLevel
HAL_FDCAN_HighPriorityMessageCallback
HAL_FDCAN_Init
HAL_FDCAN_IRQHandler
HAL_FDCAN_IsRestrictedOperationMode
HAL_FDCAN_IsTxBufferMessagePending
HAL_FDCAN_MspDeInit
HAL_FDCAN_MspInit
HAL_FDCAN_RegisterCallback
HAL_FDCAN_RegisterErrorStatusCallback
HAL_FDCAN_RegisterRxFifo0Callback
HAL_FDCAN_RegisterRxFifo1Callback
HAL_FDCAN_RegisterTxBufferAbortCallback
HAL_FDCAN_RegisterTxBufferCompleteCallback
HAL_FDCAN_RegisterTxEventFifoCallback
HAL_FDCAN_ResetTimeoutCounter
HAL_FDCAN_ResetTimestampCounter
HAL_FDCAN_RxFifo0Callback
HAL_FDCAN_RxFifo1Callback
HAL_FDCAN_Start
HAL_FDCAN_Stop
HAL_FDCAN_TimeoutOccurredCallback
HAL_FDCAN_TimestampWraparoundCallback
HAL_FDCAN_TxBufferAbortCallback
HAL_FDCAN_TxBufferCompleteCallback
HAL_FDCAN_TxEventFifoCallback
HAL_FDCAN_TxFifoEmptyCallback
HAL_FDCAN_UnRegisterCallback
HAL_FDCAN_UnRegisterErrorStatusCallback
HAL_FDCAN_UnRegisterRxFifo0Callback
HAL_FDCAN_UnRegisterRxFifo1Callback
HAL_FDCAN_UnRegisterTxBufferAbortCallback
HAL_FDCAN_UnRegisterTxBufferCompleteCallback
HAL_FDCAN_UnRegisterTxEventFifoCallback
DLCtoBytes
stm32g4xx_hal_fdcan.h
__HAL_FDCAN_CLEAR_IT
__HAL_FDCAN_DISABLE_IT
__HAL_FDCAN_ENABLE_IT
__HAL_FDCAN_GET_FLAG
__HAL_FDCAN_GET_IT
__HAL_FDCAN_GET_IT_SOURCE
__HAL_FDCAN_RESET_HANDLE_STATE
FDCAN_ACCEPT_IN_RX_FIFO0
FDCAN_ACCEPT_IN_RX_FIFO1
FDCAN_BRS_OFF
FDCAN_BRS_ON
FDCAN_CHECK_FLAG
FDCAN_CHECK_IT_SOURCE
FDCAN_CLASSIC_CAN
FDCAN_CLOCK_DIV1
FDCAN_CLOCK_DIV10
FDCAN_CLOCK_DIV12
FDCAN_CLOCK_DIV14
FDCAN_CLOCK_DIV16
FDCAN_CLOCK_DIV18
FDCAN_CLOCK_DIV2
FDCAN_CLOCK_DIV20
FDCAN_CLOCK_DIV22
FDCAN_CLOCK_DIV24
FDCAN_CLOCK_DIV26
FDCAN_CLOCK_DIV28
FDCAN_CLOCK_DIV30
FDCAN_CLOCK_DIV4
FDCAN_CLOCK_DIV6
FDCAN_CLOCK_DIV8
FDCAN_COM_STATE_IDLE
FDCAN_COM_STATE_RX
FDCAN_COM_STATE_SYNC
FDCAN_COM_STATE_TX
FDCAN_DATA_FRAME
FDCAN_DLC_BYTES_0
FDCAN_DLC_BYTES_1
FDCAN_DLC_BYTES_12
FDCAN_DLC_BYTES_16
FDCAN_DLC_BYTES_2
FDCAN_DLC_BYTES_20
FDCAN_DLC_BYTES_24
FDCAN_DLC_BYTES_3
FDCAN_DLC_BYTES_32
FDCAN_DLC_BYTES_4
FDCAN_DLC_BYTES_48
FDCAN_DLC_BYTES_5
FDCAN_DLC_BYTES_6
FDCAN_DLC_BYTES_64
FDCAN_DLC_BYTES_7
FDCAN_DLC_BYTES_8
FDCAN_ESI_ACTIVE
FDCAN_ESI_PASSIVE
FDCAN_EXTENDED_ID
FDCAN_FD_CAN
FDCAN_FILTER_DISABLE
FDCAN_FILTER_DUAL
FDCAN_FILTER_HP
FDCAN_FILTER_MASK
FDCAN_FILTER_RANGE
FDCAN_FILTER_RANGE_NO_EIDM
FDCAN_FILTER_REJECT
FDCAN_FILTER_REMOTE
FDCAN_FILTER_TO_RXFIFO0
FDCAN_FILTER_TO_RXFIFO0_HP
FDCAN_FILTER_TO_RXFIFO1
FDCAN_FILTER_TO_RXFIFO1_HP
FDCAN_FLAG_ARB_PROTOCOL_ERROR
FDCAN_FLAG_BUS_OFF
FDCAN_FLAG_DATA_PROTOCOL_ERROR
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW
FDCAN_FLAG_ERROR_PASSIVE
FDCAN_FLAG_ERROR_WARNING
FDCAN_FLAG_RAM_ACCESS_FAILURE
FDCAN_FLAG_RAM_WATCHDOG
FDCAN_FLAG_RESERVED_ADDRESS_ACCESS
FDCAN_FLAG_RX_FIFO0_FULL
FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST
FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE
FDCAN_FLAG_RX_FIFO1_FULL
FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST
FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE
FDCAN_FLAG_RX_HIGH_PRIORITY_MSG
FDCAN_FLAG_TIMEOUT_OCCURRED
FDCAN_FLAG_TIMESTAMP_WRAPAROUND
FDCAN_FLAG_TX_ABORT_COMPLETE
FDCAN_FLAG_TX_COMPLETE
FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST
FDCAN_FLAG_TX_EVT_FIFO_FULL
FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA
FDCAN_FLAG_TX_FIFO_EMPTY
FDCAN_FRAME_CLASSIC
FDCAN_FRAME_FD_BRS
FDCAN_FRAME_FD_NO_BRS
FDCAN_HP_STORAGE_MSG_LOST
FDCAN_HP_STORAGE_NO_FIFO
FDCAN_HP_STORAGE_RXFIFO0
FDCAN_HP_STORAGE_RXFIFO1
FDCAN_ILS_MASK
FDCAN_INTERRUPT_LINE0
FDCAN_INTERRUPT_LINE1
FDCAN_IR_MASK
FDCAN_IT_ARB_PROTOCOL_ERROR
FDCAN_IT_BUS_OFF
FDCAN_IT_DATA_PROTOCOL_ERROR
FDCAN_IT_ERROR_LOGGING_OVERFLOW
FDCAN_IT_ERROR_PASSIVE
FDCAN_IT_ERROR_WARNING
FDCAN_IT_GROUP_BIT_LINE_ERROR
FDCAN_IT_GROUP_MISC
FDCAN_IT_GROUP_PROTOCOL_ERROR
FDCAN_IT_GROUP_RX_FIFO0
FDCAN_IT_GROUP_RX_FIFO1
FDCAN_IT_GROUP_SMSG
FDCAN_IT_GROUP_TX_FIFO_ERROR
FDCAN_IT_LIST_BIT_LINE_ERROR
FDCAN_IT_LIST_MISC
FDCAN_IT_LIST_PROTOCOL_ERROR
FDCAN_IT_LIST_RX_FIFO0
FDCAN_IT_LIST_RX_FIFO1
FDCAN_IT_LIST_SMSG
FDCAN_IT_LIST_TX_FIFO_ERROR
FDCAN_IT_RAM_ACCESS_FAILURE
FDCAN_IT_RAM_WATCHDOG
FDCAN_IT_RESERVED_ADDRESS_ACCESS
FDCAN_IT_RX_FIFO0_FULL
FDCAN_IT_RX_FIFO0_MESSAGE_LOST
FDCAN_IT_RX_FIFO0_NEW_MESSAGE
FDCAN_IT_RX_FIFO1_FULL
FDCAN_IT_RX_FIFO1_MESSAGE_LOST
FDCAN_IT_RX_FIFO1_NEW_MESSAGE
FDCAN_IT_RX_HIGH_PRIORITY_MSG
FDCAN_IT_TIMEOUT_OCCURRED
FDCAN_IT_TIMESTAMP_WRAPAROUND
FDCAN_IT_TX_ABORT_COMPLETE
FDCAN_IT_TX_COMPLETE
FDCAN_IT_TX_EVT_FIFO_ELT_LOST
FDCAN_IT_TX_EVT_FIFO_FULL
FDCAN_IT_TX_EVT_FIFO_NEW_DATA
FDCAN_IT_TX_FIFO_EMPTY
FDCAN_MODE_BUS_MONITORING
FDCAN_MODE_EXTERNAL_LOOPBACK
FDCAN_MODE_INTERNAL_LOOPBACK
FDCAN_MODE_NORMAL
FDCAN_MODE_RESTRICTED_OPERATION
FDCAN_NO_TX_EVENTS
FDCAN_PROTOCOL_ERROR_ACK
FDCAN_PROTOCOL_ERROR_BIT0
FDCAN_PROTOCOL_ERROR_BIT1
FDCAN_PROTOCOL_ERROR_CRC
FDCAN_PROTOCOL_ERROR_FORM
FDCAN_PROTOCOL_ERROR_NO_CHANGE
FDCAN_PROTOCOL_ERROR_NONE
FDCAN_PROTOCOL_ERROR_STUFF
FDCAN_REJECT
FDCAN_REJECT_REMOTE
FDCAN_REMOTE_FRAME
FDCAN_RX_FIFO0
FDCAN_RX_FIFO1
FDCAN_RX_FIFO_BLOCKING
FDCAN_RX_FIFO_OVERWRITE
FDCAN_STANDARD_ID
FDCAN_STORE_TX_EVENTS
FDCAN_TIMEOUT_CONTINUOUS
FDCAN_TIMEOUT_RX_FIFO0
FDCAN_TIMEOUT_RX_FIFO1
FDCAN_TIMEOUT_TX_EVENT_FIFO
FDCAN_TIMESTAMP_EXTERNAL
FDCAN_TIMESTAMP_INTERNAL
FDCAN_TIMESTAMP_PRESC_1
FDCAN_TIMESTAMP_PRESC_10
FDCAN_TIMESTAMP_PRESC_11
FDCAN_TIMESTAMP_PRESC_12
FDCAN_TIMESTAMP_PRESC_13
FDCAN_TIMESTAMP_PRESC_14
FDCAN_TIMESTAMP_PRESC_15
FDCAN_TIMESTAMP_PRESC_16
FDCAN_TIMESTAMP_PRESC_2
FDCAN_TIMESTAMP_PRESC_3
FDCAN_TIMESTAMP_PRESC_4
FDCAN_TIMESTAMP_PRESC_5
FDCAN_TIMESTAMP_PRESC_6
FDCAN_TIMESTAMP_PRESC_7
FDCAN_TIMESTAMP_PRESC_8
FDCAN_TIMESTAMP_PRESC_9
FDCAN_TX_BUFFER0
FDCAN_TX_BUFFER1
FDCAN_TX_BUFFER2
FDCAN_TX_EVENT
FDCAN_TX_FIFO_OPERATION
FDCAN_TX_IN_SPITE_OF_ABORT
FDCAN_TX_QUEUE_OPERATION
HAL_FDCAN_ERROR_FIFO_EMPTY
HAL_FDCAN_ERROR_FIFO_FULL
HAL_FDCAN_ERROR_INVALID_CALLBACK
HAL_FDCAN_ERROR_LOG_OVERFLOW
HAL_FDCAN_ERROR_NONE
HAL_FDCAN_ERROR_NOT_INITIALIZED
HAL_FDCAN_ERROR_NOT_READY
HAL_FDCAN_ERROR_NOT_STARTED
HAL_FDCAN_ERROR_NOT_SUPPORTED
HAL_FDCAN_ERROR_PARAM
HAL_FDCAN_ERROR_PENDING
HAL_FDCAN_ERROR_PROTOCOL_ARBT
HAL_FDCAN_ERROR_PROTOCOL_DATA
HAL_FDCAN_ERROR_RAM_ACCESS
HAL_FDCAN_ERROR_RAM_WDG
HAL_FDCAN_ERROR_RESERVED_AREA
HAL_FDCAN_ERROR_TIMEOUT
IS_FDCAN_BRS
IS_FDCAN_CKDIV
IS_FDCAN_DATA_PRESCALER
IS_FDCAN_DATA_SJW
IS_FDCAN_DATA_TSEG1
IS_FDCAN_DATA_TSEG2
IS_FDCAN_DLC
IS_FDCAN_EFC
IS_FDCAN_ESI
IS_FDCAN_EXT_FILTER_TYPE
IS_FDCAN_FDF
IS_FDCAN_FILTER_CFG
IS_FDCAN_FRAME_FORMAT
IS_FDCAN_FRAME_TYPE
IS_FDCAN_ID_TYPE
IS_FDCAN_IT
IS_FDCAN_IT_GROUP
IS_FDCAN_IT_LINE
IS_FDCAN_MAX_VALUE
IS_FDCAN_MIN_VALUE
IS_FDCAN_MODE
IS_FDCAN_NOMINAL_PRESCALER
IS_FDCAN_NOMINAL_SJW
IS_FDCAN_NOMINAL_TSEG1
IS_FDCAN_NOMINAL_TSEG2
IS_FDCAN_NON_MATCHING
IS_FDCAN_REJECT_REMOTE
IS_FDCAN_RX_FIFO
IS_FDCAN_RX_FIFO_MODE
IS_FDCAN_STD_FILTER_TYPE
IS_FDCAN_TIMEOUT
IS_FDCAN_TIMESTAMP
IS_FDCAN_TIMESTAMP_PRESCALER
IS_FDCAN_TX_FIFO_QUEUE_MODE
IS_FDCAN_TX_LOCATION
IS_FDCAN_TX_LOCATION_LIST
FDCAN_HandleTypeDef
pFDCAN_CallbackTypeDef
pFDCAN_ErrorStatusCallbackTypeDef
pFDCAN_RxFifo0CallbackTypeDef
pFDCAN_RxFifo1CallbackTypeDef
pFDCAN_TxBufferAbortCallbackTypeDef
pFDCAN_TxBufferCompleteCallbackTypeDef
pFDCAN_TxEventFifoCallbackTypeDef
HAL_FDCAN_CallbackIDTypeDef
HAL_FDCAN_StateTypeDef
HAL_FDCAN_AbortTxRequest
HAL_FDCAN_ActivateNotification
HAL_FDCAN_AddMessageToTxFifoQ
HAL_FDCAN_ConfigExtendedIdMask
HAL_FDCAN_ConfigFilter
HAL_FDCAN_ConfigGlobalFilter
HAL_FDCAN_ConfigInterruptLines
HAL_FDCAN_ConfigRamWatchdog
HAL_FDCAN_ConfigRxFifoOverwrite
HAL_FDCAN_ConfigTimeoutCounter
HAL_FDCAN_ConfigTimestampCounter
HAL_FDCAN_ConfigTxDelayCompensation
HAL_FDCAN_DeactivateNotification
HAL_FDCAN_DeInit
HAL_FDCAN_DisableEdgeFiltering
HAL_FDCAN_DisableISOMode
HAL_FDCAN_DisableTimeoutCounter
HAL_FDCAN_DisableTimestampCounter
HAL_FDCAN_DisableTxDelayCompensation
HAL_FDCAN_EnableEdgeFiltering
HAL_FDCAN_EnableISOMode
HAL_FDCAN_EnableTimeoutCounter
HAL_FDCAN_EnableTimestampCounter
HAL_FDCAN_EnableTxDelayCompensation
HAL_FDCAN_EnterPowerDownMode
HAL_FDCAN_ErrorCallback
HAL_FDCAN_ErrorStatusCallback
HAL_FDCAN_ExitPowerDownMode
HAL_FDCAN_ExitRestrictedOperationMode
HAL_FDCAN_GetError
HAL_FDCAN_GetErrorCounters
HAL_FDCAN_GetHighPriorityMessageStatus
HAL_FDCAN_GetLatestTxFifoQRequestBuffer
HAL_FDCAN_GetProtocolStatus
HAL_FDCAN_GetRxFifoFillLevel
HAL_FDCAN_GetRxMessage
HAL_FDCAN_GetState
HAL_FDCAN_GetTimeoutCounter
HAL_FDCAN_GetTimestampCounter
HAL_FDCAN_GetTxEvent
HAL_FDCAN_GetTxFifoFreeLevel
HAL_FDCAN_HighPriorityMessageCallback
HAL_FDCAN_Init
HAL_FDCAN_IRQHandler
HAL_FDCAN_IsRestrictedOperationMode
HAL_FDCAN_IsTxBufferMessagePending
HAL_FDCAN_MspDeInit
HAL_FDCAN_MspInit
HAL_FDCAN_RegisterCallback
HAL_FDCAN_RegisterErrorStatusCallback
HAL_FDCAN_RegisterRxFifo0Callback
HAL_FDCAN_RegisterRxFifo1Callback
HAL_FDCAN_RegisterTxBufferAbortCallback
HAL_FDCAN_RegisterTxBufferCompleteCallback
HAL_FDCAN_RegisterTxEventFifoCallback
HAL_FDCAN_ResetTimeoutCounter
HAL_FDCAN_ResetTimestampCounter
HAL_FDCAN_RxFifo0Callback
HAL_FDCAN_RxFifo1Callback
HAL_FDCAN_Start
HAL_FDCAN_Stop
HAL_FDCAN_TimeoutOccurredCallback
HAL_FDCAN_TimestampWraparoundCallback
HAL_FDCAN_TxBufferAbortCallback
HAL_FDCAN_TxBufferCompleteCallback
HAL_FDCAN_TxEventFifoCallback
HAL_FDCAN_TxFifoEmptyCallback
HAL_FDCAN_UnRegisterCallback
HAL_FDCAN_UnRegisterErrorStatusCallback
HAL_FDCAN_UnRegisterRxFifo0Callback
HAL_FDCAN_UnRegisterRxFifo1Callback
HAL_FDCAN_UnRegisterTxBufferAbortCallback
HAL_FDCAN_UnRegisterTxBufferCompleteCallback
HAL_FDCAN_UnRegisterTxEventFifoCallback
stm32g4xx_hal_flash.c
FLASH_Program_DoubleWord
FLASH_Program_Fast
FLASH_WaitForLastOperation
HAL_FLASH_EndOfOperationCallback
HAL_FLASH_GetError
HAL_FLASH_IRQHandler
HAL_FLASH_Lock
HAL_FLASH_OB_Launch
HAL_FLASH_OB_Lock
HAL_FLASH_OB_Unlock
HAL_FLASH_OperationErrorCallback
HAL_FLASH_Program
HAL_FLASH_Program_IT
HAL_FLASH_Unlock
pFlash
stm32g4xx_hal_flash.h
__HAL_FLASH_DATA_CACHE_DISABLE
__HAL_FLASH_DATA_CACHE_ENABLE
__HAL_FLASH_DATA_CACHE_RESET
__HAL_FLASH_DISABLE_IT
__HAL_FLASH_ENABLE_IT
__HAL_FLASH_GET_FLAG
__HAL_FLASH_GET_LATENCY
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE
__HAL_FLASH_INSTRUCTION_CACHE_RESET
__HAL_FLASH_POWER_DOWN_DISABLE
__HAL_FLASH_POWER_DOWN_ENABLE
__HAL_FLASH_PREFETCH_BUFFER_DISABLE
__HAL_FLASH_PREFETCH_BUFFER_ENABLE
__HAL_FLASH_SET_LATENCY
__HAL_FLASH_SLEEP_POWERDOWN_DISABLE
__HAL_FLASH_SLEEP_POWERDOWN_ENABLE
FLASH_BANK_1
FLASH_BANK_2
FLASH_BANK_BOTH
FLASH_BANK_SIZE
FLASH_FLAG_ALL_ERRORS
FLASH_FLAG_BSY
FLASH_FLAG_ECCC
FLASH_FLAG_ECCC2
FLASH_FLAG_ECCD
FLASH_FLAG_ECCD2
FLASH_FLAG_ECCR_ERRORS
FLASH_FLAG_EOP
FLASH_FLAG_FASTERR
FLASH_FLAG_MISERR
FLASH_FLAG_OPERR
FLASH_FLAG_OPTVERR
FLASH_FLAG_PGAERR
FLASH_FLAG_PGSERR
FLASH_FLAG_PROGERR
FLASH_FLAG_RDERR
FLASH_FLAG_SIZERR
FLASH_FLAG_SR_ERRORS
FLASH_FLAG_WRPERR
FLASH_IT_ECCC
FLASH_IT_EOP
FLASH_IT_OPERR
FLASH_IT_RDERR
FLASH_KEY1
FLASH_KEY2
FLASH_LATENCY_0
FLASH_LATENCY_1
FLASH_LATENCY_10
FLASH_LATENCY_11
FLASH_LATENCY_12
FLASH_LATENCY_13
FLASH_LATENCY_14
FLASH_LATENCY_15
FLASH_LATENCY_2
FLASH_LATENCY_3
FLASH_LATENCY_4
FLASH_LATENCY_5
FLASH_LATENCY_6
FLASH_LATENCY_7
FLASH_LATENCY_8
FLASH_LATENCY_9
FLASH_OPTKEY1
FLASH_OPTKEY2
FLASH_PAGE_NB
FLASH_PAGE_SIZE
FLASH_PAGE_SIZE_128_BITS
FLASH_PDKEY1
FLASH_PDKEY2
FLASH_SIZE
FLASH_SIZE_DATA_REGISTER
FLASH_TIMEOUT_VALUE
FLASH_TYPEERASE_MASSERASE
FLASH_TYPEERASE_PAGES
FLASH_TYPEPROGRAM_DOUBLEWORD
FLASH_TYPEPROGRAM_FAST
FLASH_TYPEPROGRAM_FAST_AND_LAST
HAL_FLASH_ERROR_ECCC
HAL_FLASH_ERROR_ECCC2
HAL_FLASH_ERROR_ECCD
HAL_FLASH_ERROR_ECCD2
HAL_FLASH_ERROR_FAST
HAL_FLASH_ERROR_MIS
HAL_FLASH_ERROR_NONE
HAL_FLASH_ERROR_OP
HAL_FLASH_ERROR_OPTV
HAL_FLASH_ERROR_PGA
HAL_FLASH_ERROR_PGS
HAL_FLASH_ERROR_PROG
HAL_FLASH_ERROR_RD
HAL_FLASH_ERROR_SIZ
HAL_FLASH_ERROR_WRP
IS_FLASH_BANK
IS_FLASH_BANK_EXCLUSIVE
IS_FLASH_LATENCY
IS_FLASH_MAIN_MEM_ADDRESS
IS_FLASH_OTP_ADDRESS
IS_FLASH_PAGE
IS_FLASH_PROGRAM_ADDRESS
IS_FLASH_TYPEERASE
IS_FLASH_TYPEPROGRAM
IS_OB_BOOT_LOCK
IS_OB_PCROP_RDP
IS_OB_RDP_LEVEL
IS_OB_SECMEM_SIZE
IS_OB_USER_BFB2
IS_OB_USER_BOOT0
IS_OB_USER_BOOT1
IS_OB_USER_BOR_LEVEL
IS_OB_USER_CCMSRAM_RST
IS_OB_USER_DBANK
IS_OB_USER_IRHEN
IS_OB_USER_IWDG
IS_OB_USER_IWDG_STDBY
IS_OB_USER_IWDG_STOP
IS_OB_USER_NRST_MODE
IS_OB_USER_SHUTDOWN
IS_OB_USER_SRAM_PARITY
IS_OB_USER_STANDBY
IS_OB_USER_STOP
IS_OB_USER_SWBOOT0
IS_OB_USER_TYPE
IS_OB_USER_WWDG
IS_OB_WRPAREA
IS_OPTIONBYTE
OB_BFB2_DISABLE
OB_BFB2_ENABLE
OB_BOOT0_FROM_OB
OB_BOOT0_FROM_PIN
OB_BOOT1_SRAM
OB_BOOT1_SYSTEM
OB_BOOT_LOCK_DISABLE
OB_BOOT_LOCK_ENABLE
OB_BOR_LEVEL_0
OB_BOR_LEVEL_1
OB_BOR_LEVEL_2
OB_BOR_LEVEL_3
OB_BOR_LEVEL_4
OB_CCMSRAM_RST_ERASE
OB_CCMSRAM_RST_NOT_ERASE
OB_DBANK_128_BITS
OB_DBANK_64_BITS
OB_IRH_DISABLE
OB_IRH_ENABLE
OB_IWDG_HW
OB_IWDG_STDBY_FREEZE
OB_IWDG_STDBY_RUN
OB_IWDG_STOP_FREEZE
OB_IWDG_STOP_RUN
OB_IWDG_SW
OB_nBOOT0_RESET
OB_nBOOT0_SET
OB_NRST_MODE_GPIO
OB_NRST_MODE_INPUT_ONLY
OB_NRST_MODE_INPUT_OUTPUT
OB_PCROP_RDP_ERASE
OB_PCROP_RDP_NOT_ERASE
OB_RDP_LEVEL_0
OB_RDP_LEVEL_1
OB_RDP_LEVEL_2
OB_SHUTDOWN_NORST
OB_SHUTDOWN_RST
OB_SRAM_PARITY_DISABLE
OB_SRAM_PARITY_ENABLE
OB_STANDBY_NORST
OB_STANDBY_RST
OB_STOP_NORST
OB_STOP_RST
OB_USER_BFB2
OB_USER_BOR_LEV
OB_USER_CCMSRAM_RST
OB_USER_DBANK
OB_USER_IRHEN
OB_USER_IWDG_STDBY
OB_USER_IWDG_STOP
OB_USER_IWDG_SW
OB_USER_nBOOT0
OB_USER_nBOOT1
OB_USER_NRST_MODE
OB_USER_nRST_SHDW
OB_USER_nRST_STDBY
OB_USER_nRST_STOP
OB_USER_nSWBOOT0
OB_USER_SRAM_PE
OB_USER_WWDG_SW
OB_WRPAREA_BANK1_AREAA
OB_WRPAREA_BANK1_AREAB
OB_WRPAREA_BANK2_AREAA
OB_WRPAREA_BANK2_AREAB
OB_WWDG_HW
OB_WWDG_SW
OPTIONBYTE_BOOT_LOCK
OPTIONBYTE_PCROP
OPTIONBYTE_RDP
OPTIONBYTE_SEC
OPTIONBYTE_USER
OPTIONBYTE_WRP
FLASH_CacheTypeDef
FLASH_ProcedureTypeDef
FLASH_WaitForLastOperation
HAL_FLASH_EndOfOperationCallback
HAL_FLASH_GetError
HAL_FLASH_IRQHandler
HAL_FLASH_Lock
HAL_FLASH_OB_Launch
HAL_FLASH_OB_Lock
HAL_FLASH_OB_Unlock
HAL_FLASH_OperationErrorCallback
HAL_FLASH_Program
HAL_FLASH_Program_IT
HAL_FLASH_Unlock
pFlash
stm32g4xx_hal_flash_ex.c
FLASH_MassErase
FLASH_OB_BootLockConfig
FLASH_OB_GetBootLock
FLASH_OB_GetPCROP
FLASH_OB_GetRDP
FLASH_OB_GetSecMem
FLASH_OB_GetUser
FLASH_OB_GetWRP
FLASH_OB_PCROPConfig
FLASH_OB_RDPConfig
FLASH_OB_SecMemConfig
FLASH_OB_UserConfig
FLASH_OB_WRPConfig
FLASH_PageErase
HAL_FLASHEx_DisableDebugger
HAL_FLASHEx_EnableDebugger
HAL_FLASHEx_EnableSecMemProtection
HAL_FLASHEx_Erase
HAL_FLASHEx_Erase_IT
HAL_FLASHEx_OBGetConfig
HAL_FLASHEx_OBProgram
stm32g4xx_hal_flash_ex.h
FLASH_PageErase
HAL_FLASHEx_DisableDebugger
HAL_FLASHEx_EnableDebugger
HAL_FLASHEx_EnableSecMemProtection
HAL_FLASHEx_Erase
HAL_FLASHEx_Erase_IT
HAL_FLASHEx_OBGetConfig
HAL_FLASHEx_OBProgram
stm32g4xx_hal_flash_ramfunc.c
HAL_FLASHEx_EnableRunPowerDown
HAL_FLASHEx_OB_DBankConfig
stm32g4xx_hal_flash_ramfunc.h
HAL_FLASHEx_EnableRunPowerDown
HAL_FLASHEx_OB_DBankConfig
stm32g4xx_hal_fmac.c
FMAC_DMA_WEN
FMAC_GET_START_BIT
FMAC_GET_THRESHOLD_FROM_WM
FMAC_GET_X1_FULL_WM
FMAC_GET_X1_SIZE
FMAC_GET_X2_SIZE
FMAC_GET_Y_EMPTY_WM
FMAC_GET_Y_SIZE
FMAC_START
HAL_FMAC_RESET_TIMEOUT_VALUE
HAL_FMAC_TIMEOUT_VALUE
MAX_FILTER_DATA_SIZE_TO_HANDLE
MAX_PRELOAD_INDEX
POLLING_DISABLED
POLLING_ENABLED
POLLING_NOT_STOPPED
POLLING_STOPPED
PRELOAD_ACCESS_DMA
PRELOAD_ACCESS_POLLING
FMAC_AppendFilterDataUpdateState
FMAC_ConfigFilterOutputBufferUpdateState
FMAC_DMAError
FMAC_DMAFilterConfig
FMAC_DMAFilterPreload
FMAC_DMAGetData
FMAC_DMAHalfGetData
FMAC_DMAHalfOutputDataReady
FMAC_DMAOutputDataReady
FMAC_FilterConfig
FMAC_FilterPreload
FMAC_ReadDataIncrementPtr
FMAC_Reset
FMAC_ResetDataPointers
FMAC_ResetInputStateAndDataPointers
FMAC_ResetOutputStateAndDataPointers
FMAC_WaitOnStartUntilTimeout
FMAC_WriteDataIncrementPtr
FMAC_WritePreloadDataIncrementPtr
HAL_FMAC_AppendFilterData
HAL_FMAC_ConfigFilterOutputBuffer
HAL_FMAC_DeInit
HAL_FMAC_ErrorCallback
HAL_FMAC_FilterConfig
HAL_FMAC_FilterConfig_DMA
HAL_FMAC_FilterConfigCallback
HAL_FMAC_FilterPreload
HAL_FMAC_FilterPreload_DMA
HAL_FMAC_FilterPreloadCallback
HAL_FMAC_FilterStart
HAL_FMAC_FilterStop
HAL_FMAC_GetDataCallback
HAL_FMAC_GetError
HAL_FMAC_GetState
HAL_FMAC_HalfGetDataCallback
HAL_FMAC_HalfOutputDataReadyCallback
HAL_FMAC_Init
HAL_FMAC_IRQHandler
HAL_FMAC_MspDeInit
HAL_FMAC_MspInit
HAL_FMAC_OutputDataReadyCallback
HAL_FMAC_PollFilterData
HAL_FMAC_RegisterCallback
HAL_FMAC_UnRegisterCallback
stm32g4xx_hal_fmac.h
__HAL_FMAC_CLEAR_IT
__HAL_FMAC_DISABLE_IT
__HAL_FMAC_ENABLE_IT
__HAL_FMAC_GET_FLAG
__HAL_FMAC_GET_IT
__HAL_FMAC_GET_IT_SOURCE
__HAL_FMAC_RESET_HANDLE_STATE
FMAC_BUFFER_ACCESS_DMA
FMAC_BUFFER_ACCESS_IT
FMAC_BUFFER_ACCESS_NONE
FMAC_BUFFER_ACCESS_POLLING
FMAC_CLIP_DISABLED
FMAC_CLIP_ENABLED
FMAC_FLAG_OVFL
FMAC_FLAG_SAT
FMAC_FLAG_UNFL
FMAC_FLAG_X1FULL
FMAC_FLAG_YEMPTY
FMAC_FUNC_CONVO_FIR
FMAC_FUNC_IIR_DIRECT_FORM_1
FMAC_FUNC_LOAD_X1
FMAC_FUNC_LOAD_X2
FMAC_FUNC_LOAD_Y
FMAC_IT_OVFLIEN
FMAC_IT_RIEN
FMAC_IT_SATIEN
FMAC_IT_UNFLIEN
FMAC_IT_WIEN
FMAC_PARAM_P_MAX_FIR
FMAC_PARAM_P_MAX_IIR
FMAC_PARAM_P_MIN
FMAC_PARAM_Q_MAX
FMAC_PARAM_Q_MIN
FMAC_PARAM_R_MAX
FMAC_THRESHOLD_1
FMAC_THRESHOLD_2
FMAC_THRESHOLD_4
FMAC_THRESHOLD_8
FMAC_THRESHOLD_NO_VALUE
HAL_FMAC_ERROR_DMA
HAL_FMAC_ERROR_INVALID_CALLBACK
HAL_FMAC_ERROR_NONE
HAL_FMAC_ERROR_OVFL
HAL_FMAC_ERROR_PARAM
HAL_FMAC_ERROR_RESET
HAL_FMAC_ERROR_SAT
HAL_FMAC_ERROR_TIMEOUT
HAL_FMAC_ERROR_UNFL
IS_FMAC_BUFFER_ACCESS
IS_FMAC_CLIP_STATE
IS_FMAC_FILTER_FUNCTION
IS_FMAC_FUNCTION
IS_FMAC_LOAD_FUNCTION
IS_FMAC_N_LOAD_FUNCTION
IS_FMAC_N_M_LOAD_FUNCTION
IS_FMAC_PARAM_P
IS_FMAC_PARAM_Q
IS_FMAC_PARAM_R
IS_FMAC_THRESHOLD
IS_FMAC_THRESHOLD_APPLICABLE
FMAC_HandleTypeDef
pFMAC_CallbackTypeDef
HAL_FMAC_CallbackIDTypeDef
HAL_FMAC_StateTypeDef
HAL_FMAC_AppendFilterData
HAL_FMAC_ConfigFilterOutputBuffer
HAL_FMAC_DeInit
HAL_FMAC_ErrorCallback
HAL_FMAC_FilterConfig
HAL_FMAC_FilterConfig_DMA
HAL_FMAC_FilterConfigCallback
HAL_FMAC_FilterPreload
HAL_FMAC_FilterPreload_DMA
HAL_FMAC_FilterPreloadCallback
HAL_FMAC_FilterStart
HAL_FMAC_FilterStop
HAL_FMAC_GetDataCallback
HAL_FMAC_GetError
HAL_FMAC_GetState
HAL_FMAC_HalfGetDataCallback
HAL_FMAC_HalfOutputDataReadyCallback
HAL_FMAC_Init
HAL_FMAC_IRQHandler
HAL_FMAC_MspDeInit
HAL_FMAC_MspInit
HAL_FMAC_OutputDataReadyCallback
HAL_FMAC_PollFilterData
HAL_FMAC_RegisterCallback
HAL_FMAC_UnRegisterCallback
stm32g4xx_hal_gpio.c
HAL_GPIO_DeInit
HAL_GPIO_EXTI_Callback
HAL_GPIO_EXTI_IRQHandler
HAL_GPIO_Init
HAL_GPIO_LockPin
HAL_GPIO_ReadPin
HAL_GPIO_TogglePin
HAL_GPIO_WritePin
stm32g4xx_hal_gpio.h
__HAL_GPIO_EXTI_CLEAR_IT
__HAL_GPIO_EXTI_GENERATE_SWIT
__HAL_GPIO_EXTI_GET_FLAG
__HAL_GPIO_EXTI_GET_IT
EXTI_EVT
EXTI_IT
EXTI_MODE
EXTI_MODE_Pos
GPIO_MODE
GPIO_MODE_AF_OD
GPIO_MODE_AF_PP
GPIO_MODE_ANALOG
GPIO_MODE_EVT_FALLING
GPIO_MODE_EVT_RISING
GPIO_MODE_EVT_RISING_FALLING
GPIO_MODE_INPUT
GPIO_MODE_IT_FALLING
GPIO_MODE_IT_RISING
GPIO_MODE_IT_RISING_FALLING
GPIO_MODE_OUTPUT_OD
GPIO_MODE_OUTPUT_PP
GPIO_MODE_Pos
GPIO_NOPULL
GPIO_PIN_0
GPIO_PIN_1
GPIO_PIN_10
GPIO_PIN_11
GPIO_PIN_12
GPIO_PIN_13
GPIO_PIN_14
GPIO_PIN_15
GPIO_PIN_2
GPIO_PIN_3
GPIO_PIN_4
GPIO_PIN_5
GPIO_PIN_6
GPIO_PIN_7
GPIO_PIN_8
GPIO_PIN_9
GPIO_PIN_All
GPIO_PIN_MASK
GPIO_PULLDOWN
GPIO_PULLUP
GPIO_SPEED_FREQ_HIGH
GPIO_SPEED_FREQ_LOW
GPIO_SPEED_FREQ_MEDIUM
GPIO_SPEED_FREQ_VERY_HIGH
IS_GPIO_MODE
IS_GPIO_PIN
IS_GPIO_PIN_ACTION
IS_GPIO_PULL
IS_GPIO_SPEED
MODE_AF
MODE_ANALOG
MODE_INPUT
MODE_OUTPUT
OUTPUT_OD
OUTPUT_PP
OUTPUT_TYPE
OUTPUT_TYPE_Pos
TRIGGER_FALLING
TRIGGER_MODE
TRIGGER_MODE_Pos
TRIGGER_RISING
GPIO_PinState
HAL_GPIO_DeInit
HAL_GPIO_EXTI_Callback
HAL_GPIO_EXTI_IRQHandler
HAL_GPIO_Init
HAL_GPIO_LockPin
HAL_GPIO_ReadPin
HAL_GPIO_TogglePin
HAL_GPIO_WritePin
stm32g4xx_hal_gpio_ex.h
GPIO_AF0_RTC_50Hz
GPIO_AF0_SWJ
GPIO_AF0_TRACE
GPIO_AF10_QUADSPI
GPIO_AF10_TIM17
GPIO_AF10_TIM17_COMP1
GPIO_AF10_TIM2
GPIO_AF10_TIM3
GPIO_AF10_TIM4
GPIO_AF10_TIM8
GPIO_AF10_TIM8_COMP2
GPIO_AF11_FDCAN1
GPIO_AF11_FDCAN3
GPIO_AF11_LPTIM1
GPIO_AF11_TIM1
GPIO_AF11_TIM8
GPIO_AF11_TIM8_COMP1
GPIO_AF12_FMC
GPIO_AF12_HRTIM1
GPIO_AF12_LPUART1
GPIO_AF12_SAI1
GPIO_AF12_TIM1
GPIO_AF12_TIM1_COMP1
GPIO_AF12_TIM1_COMP2
GPIO_AF13_HRTIM1
GPIO_AF13_SAI1
GPIO_AF14_SAI1
GPIO_AF14_TIM15
GPIO_AF14_TIM2
GPIO_AF14_UART4
GPIO_AF14_UART5
GPIO_AF14_UCPD1
GPIO_AF15_EVENTOUT
GPIO_AF1_IR
GPIO_AF1_LPTIM1
GPIO_AF1_TIM15
GPIO_AF1_TIM16
GPIO_AF1_TIM17
GPIO_AF1_TIM17_COMP1
GPIO_AF1_TIM2
GPIO_AF1_TIM5
GPIO_AF2_COMP1
GPIO_AF2_I2C3
GPIO_AF2_TIM1
GPIO_AF2_TIM15
GPIO_AF2_TIM15_COMP1
GPIO_AF2_TIM16
GPIO_AF2_TIM16_COMP1
GPIO_AF2_TIM1_COMP1
GPIO_AF2_TIM2
GPIO_AF2_TIM20
GPIO_AF2_TIM20_COMP1
GPIO_AF2_TIM20_COMP2
GPIO_AF2_TIM3
GPIO_AF2_TIM4
GPIO_AF2_TIM5
GPIO_AF2_TIM8
GPIO_AF3_COMP3
GPIO_AF3_HRTIM1
GPIO_AF3_I2C3
GPIO_AF3_I2C4
GPIO_AF3_QUADSPI
GPIO_AF3_SAI1
GPIO_AF3_TIM15
GPIO_AF3_TIM20
GPIO_AF3_TIM8
GPIO_AF3_UCPD1
GPIO_AF4_I2C1
GPIO_AF4_I2C2
GPIO_AF4_I2C3
GPIO_AF4_I2C4
GPIO_AF4_TIM1
GPIO_AF4_TIM16
GPIO_AF4_TIM17
GPIO_AF4_TIM8
GPIO_AF4_TIM8_COMP1
GPIO_AF5_I2S2ext
GPIO_AF5_IR
GPIO_AF5_SPI1
GPIO_AF5_SPI2
GPIO_AF5_SPI4
GPIO_AF5_TIM8
GPIO_AF5_TIM8_COMP1
GPIO_AF5_UART4
GPIO_AF5_UART5
GPIO_AF6_I2S3ext
GPIO_AF6_IR
GPIO_AF6_SPI2
GPIO_AF6_SPI3
GPIO_AF6_TIM1
GPIO_AF6_TIM1_COMP1
GPIO_AF6_TIM1_COMP2
GPIO_AF6_TIM20
GPIO_AF6_TIM5
GPIO_AF6_TIM8
GPIO_AF6_TIM8_COMP2
GPIO_AF7_COMP5
GPIO_AF7_COMP6
GPIO_AF7_COMP7
GPIO_AF7_USART1
GPIO_AF7_USART2
GPIO_AF7_USART3
GPIO_AF8_COMP1
GPIO_AF8_COMP2
GPIO_AF8_COMP3
GPIO_AF8_COMP4
GPIO_AF8_COMP5
GPIO_AF8_COMP6
GPIO_AF8_COMP7
GPIO_AF8_I2C3
GPIO_AF8_I2C4
GPIO_AF8_LPUART1
GPIO_AF8_UART4
GPIO_AF8_UART5
GPIO_AF9_FDCAN1
GPIO_AF9_FDCAN2
GPIO_AF9_TIM1
GPIO_AF9_TIM15
GPIO_AF9_TIM15_COMP1
GPIO_AF9_TIM1_COMP1
GPIO_AF9_TIM8
GPIO_AF9_TIM8_COMP1
GPIO_GET_INDEX
IS_GPIO_AF
stm32g4xx_hal_hrtim.c
HRTIM_FLTINR2_FLTxLCK
HRTIM_FLTR_FLTxEN
HRTIM_TIMCR_TIMUPDATETRIGGER
GetTimerIdxFromDMAHandle
HAL_HRTIM_ADCPostScalerConfig
HAL_HRTIM_ADCTriggerConfig
HAL_HRTIM_BurstDMAConfig
HAL_HRTIM_BurstDMATransfer
HAL_HRTIM_BurstDMATransferCallback
HAL_HRTIM_BurstModeConfig
HAL_HRTIM_BurstModeCtl
HAL_HRTIM_BurstModePeriodCallback
HAL_HRTIM_BurstModeSoftwareTrigger
HAL_HRTIM_Capture1EventCallback
HAL_HRTIM_Capture2EventCallback
HAL_HRTIM_ChopperModeConfig
HAL_HRTIM_Compare1EventCallback
HAL_HRTIM_Compare2EventCallback
HAL_HRTIM_Compare3EventCallback
HAL_HRTIM_Compare4EventCallback
HAL_HRTIM_CounterResetCallback
HAL_HRTIM_DeadTimeConfig
HAL_HRTIM_DeInit
HAL_HRTIM_DelayedProtectionCallback
HAL_HRTIM_DLLCalibrationReadyCallback
HAL_HRTIM_DLLCalibrationStart
HAL_HRTIM_DLLCalibrationStart_IT
HAL_HRTIM_ErrorCallback
HAL_HRTIM_EventConfig
HAL_HRTIM_EventPrescalerConfig
HAL_HRTIM_ExtEventCounterConfig
HAL_HRTIM_ExtEventCounterDisable
HAL_HRTIM_ExtEventCounterEnable
HAL_HRTIM_ExtEventCounterReset
HAL_HRTIM_Fault1Callback
HAL_HRTIM_Fault2Callback
HAL_HRTIM_Fault3Callback
HAL_HRTIM_Fault4Callback
HAL_HRTIM_Fault5Callback
HAL_HRTIM_Fault6Callback
HAL_HRTIM_FaultBlankingConfigAndEnable
HAL_HRTIM_FaultConfig
HAL_HRTIM_FaultCounterConfig
HAL_HRTIM_FaultCounterReset
HAL_HRTIM_FaultModeCtl
HAL_HRTIM_FaultPrescalerConfig
HAL_HRTIM_GetBurstStatus
HAL_HRTIM_GetCaptured
HAL_HRTIM_GetCapturedDir
HAL_HRTIM_GetCapturedValue
HAL_HRTIM_GetCurrentPushPullStatus
HAL_HRTIM_GetDelayedProtectionStatus
HAL_HRTIM_GetIdlePushPullStatus
HAL_HRTIM_GetState
HAL_HRTIM_Init
HAL_HRTIM_IRQHandler
HAL_HRTIM_MspDeInit
HAL_HRTIM_MspInit
HAL_HRTIM_Output1ResetCallback
HAL_HRTIM_Output1SetCallback
HAL_HRTIM_Output2ResetCallback
HAL_HRTIM_Output2SetCallback
HAL_HRTIM_OutputSwapDisable
HAL_HRTIM_OutputSwapEnable
HAL_HRTIM_PollForDLLCalibration
HAL_HRTIM_RegisterCallback
HAL_HRTIM_RegistersUpdateCallback
HAL_HRTIM_RepetitionEventCallback
HAL_HRTIM_RollOverModeConfig
HAL_HRTIM_SimpleBaseStart
HAL_HRTIM_SimpleBaseStart_DMA
HAL_HRTIM_SimpleBaseStart_IT
HAL_HRTIM_SimpleBaseStop
HAL_HRTIM_SimpleBaseStop_DMA
HAL_HRTIM_SimpleBaseStop_IT
HAL_HRTIM_SimpleCaptureChannelConfig
HAL_HRTIM_SimpleCaptureStart
HAL_HRTIM_SimpleCaptureStart_DMA
HAL_HRTIM_SimpleCaptureStart_IT
HAL_HRTIM_SimpleCaptureStop
HAL_HRTIM_SimpleCaptureStop_DMA
HAL_HRTIM_SimpleCaptureStop_IT
HAL_HRTIM_SimpleOCChannelConfig
HAL_HRTIM_SimpleOCStart
HAL_HRTIM_SimpleOCStart_DMA
HAL_HRTIM_SimpleOCStart_IT
HAL_HRTIM_SimpleOCStop
HAL_HRTIM_SimpleOCStop_DMA
HAL_HRTIM_SimpleOCStop_IT
HAL_HRTIM_SimpleOnePulseChannelConfig
HAL_HRTIM_SimpleOnePulseStart
HAL_HRTIM_SimpleOnePulseStart_IT
HAL_HRTIM_SimpleOnePulseStop
HAL_HRTIM_SimpleOnePulseStop_IT
HAL_HRTIM_SimplePWMChannelConfig
HAL_HRTIM_SimplePWMStart
HAL_HRTIM_SimplePWMStart_DMA
HAL_HRTIM_SimplePWMStart_IT
HAL_HRTIM_SimplePWMStop
HAL_HRTIM_SimplePWMStop_DMA
HAL_HRTIM_SimplePWMStop_IT
HAL_HRTIM_SoftwareCapture
HAL_HRTIM_SoftwareReset
HAL_HRTIM_SoftwareUpdate
HAL_HRTIM_SwapTimerOutput
HAL_HRTIM_SynchronizationEventCallback
HAL_HRTIM_SystemFaultCallback
HAL_HRTIM_TimeBaseConfig
HAL_HRTIM_TimerDualChannelDacConfig
HAL_HRTIM_TimerEventFilteringConfig
HAL_HRTIM_TIMxRegisterCallback
HAL_HRTIM_TIMxUnRegisterCallback
HAL_HRTIM_UnRegisterCallback
HAL_HRTIM_UpdateDisable
HAL_HRTIM_UpdateEnable
HAL_HRTIM_WaveformCaptureConfig
HAL_HRTIM_WaveformCompareConfig
HAL_HRTIM_WaveformCountStart
HAL_HRTIM_WaveformCountStart_DMA
HAL_HRTIM_WaveformCountStart_IT
HAL_HRTIM_WaveformCountStop
HAL_HRTIM_WaveformCountStop_DMA
HAL_HRTIM_WaveformCountStop_IT
HAL_HRTIM_WaveformGetOutputLevel
HAL_HRTIM_WaveformGetOutputState
HAL_HRTIM_WaveformOutputConfig
HAL_HRTIM_WaveformOutputStart
HAL_HRTIM_WaveformOutputStop
HAL_HRTIM_WaveformSetOutputLevel
HAL_HRTIM_WaveformTimerConfig
HAL_HRTIM_WaveformTimerControl
HRTIM_BurstDMACplt
HRTIM_CaptureUnitConfig
HRTIM_DMAError
HRTIM_DMAMasterCplt
HRTIM_DMATimerxCplt
HRTIM_EventConfig
HRTIM_ForceRegistersUpdate
HRTIM_GetDMAFromOCMode
HRTIM_GetDMAHandleFromTimerIdx
HRTIM_GetITFromOCMode
HRTIM_HRTIM_ISR
HRTIM_Master_ISR
HRTIM_MasterBase_Config
HRTIM_MasterWaveform_Config
HRTIM_OutputConfig
HRTIM_TIM_ResetConfig
HRTIM_Timer_ISR
HRTIM_TimingUnitBase_Config
HRTIM_TimingUnitRollOver_Config
HRTIM_TimingUnitWaveform_Config
HRTIM_TimingUnitWaveform_Control
TimerIdxToTimerId
stm32g4xx_hal_hrtim.h
__HAL_HRTIM_CLEAR_IT
__HAL_HRTIM_COUNTER_MODE_UP
__HAL_HRTIM_COUNTER_MODE_UPDOWN
__HAL_HRTIM_DISABLE
__HAL_HRTIM_DISABLE_IT
__HAL_HRTIM_ENABLE
__HAL_HRTIM_ENABLE_IT
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE
__HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET
__HAL_HRTIM_FAULT_BLANKING_DISABLE
__HAL_HRTIM_FAULT_BLANKING_ENABLE
__HAL_HRTIM_GET_FLAG
__HAL_HRTIM_GET_ITSTATUS
__HAL_HRTIM_GETCLOCKPRESCALER
__HAL_HRTIM_GETCOMPARE
__HAL_HRTIM_GETCOUNTER
__HAL_HRTIM_GETPERIOD
__HAL_HRTIM_MASTER_CLEAR_FLAG
__HAL_HRTIM_MASTER_CLEAR_IT
__HAL_HRTIM_MASTER_DISABLE_DMA
__HAL_HRTIM_MASTER_DISABLE_IT
__HAL_HRTIM_MASTER_ENABLE_DMA
__HAL_HRTIM_MASTER_ENABLE_IT
__HAL_HRTIM_MASTER_GET_FLAG
__HAL_HRTIM_MASTER_GET_ITSTATUS
__HAL_HRTIM_RESET_HANDLE_STATE
__HAL_HRTIM_SETCLOCKPRESCALER
__HAL_HRTIM_SETCOMPARE
__HAL_HRTIM_SETCOUNTER
__HAL_HRTIM_SETPERIOD
__HAL_HRTIM_TIMER_CLEAR_FLAG
__HAL_HRTIM_TIMER_CLEAR_IT
__HAL_HRTIM_TIMER_DISABLE_DMA
__HAL_HRTIM_TIMER_DISABLE_IT
__HAL_HRTIM_TIMER_ENABLE_DMA
__HAL_HRTIM_TIMER_ENABLE_IT
__HAL_HRTIM_TIMER_GET_FLAG
__HAL_HRTIM_TIMER_GET_ITSTATUS
__HAL_HRTIM_TIMER_OUTPUT_NOSWAP
__HAL_HRTIM_TIMER_OUTPUT_SWAP
HRIM_BURSTMODEPRELOAD_DISABLED
HRIM_BURSTMODEPRELOAD_ENABLED
HRTIM_ADCTRIGGER_1
HRTIM_ADCTRIGGER_10
HRTIM_ADCTRIGGER_2
HRTIM_ADCTRIGGER_3
HRTIM_ADCTRIGGER_4
HRTIM_ADCTRIGGER_5
HRTIM_ADCTRIGGER_6
HRTIM_ADCTRIGGER_7
HRTIM_ADCTRIGGER_8
HRTIM_ADCTRIGGER_9
HRTIM_ADCTRIGGEREVENT13_EVENT_1
HRTIM_ADCTRIGGEREVENT13_EVENT_2
HRTIM_ADCTRIGGEREVENT13_EVENT_3
HRTIM_ADCTRIGGEREVENT13_EVENT_4
HRTIM_ADCTRIGGEREVENT13_EVENT_5
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT13_NONE
HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET
HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET
HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET
HRTIM_ADCTRIGGEREVENT24_EVENT_10
HRTIM_ADCTRIGGEREVENT24_EVENT_6
HRTIM_ADCTRIGGEREVENT24_EVENT_7
HRTIM_ADCTRIGGEREVENT24_EVENT_8
HRTIM_ADCTRIGGEREVENT24_EVENT_9
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT24_NONE
HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT579_EVENT_1
HRTIM_ADCTRIGGEREVENT579_EVENT_2
HRTIM_ADCTRIGGEREVENT579_EVENT_3
HRTIM_ADCTRIGGEREVENT579_EVENT_4
HRTIM_ADCTRIGGEREVENT579_EVENT_5
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET
HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET
HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD
HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET
HRTIM_ADCTRIGGEREVENT6810_EVENT_10
HRTIM_ADCTRIGGEREVENT6810_EVENT_6
HRTIM_ADCTRIGGEREVENT6810_EVENT_7
HRTIM_ADCTRIGGEREVENT6810_EVENT_8
HRTIM_ADCTRIGGEREVENT6810_EVENT_9
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3
HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4
HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD
HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3
HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3
HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4
HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD
HRTIM_ADCTRIGGERUPDATE_MASTER
HRTIM_ADCTRIGGERUPDATE_TIMER_A
HRTIM_ADCTRIGGERUPDATE_TIMER_B
HRTIM_ADCTRIGGERUPDATE_TIMER_C
HRTIM_ADCTRIGGERUPDATE_TIMER_D
HRTIM_ADCTRIGGERUPDATE_TIMER_E
HRTIM_ADCTRIGGERUPDATE_TIMER_F
HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT
HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1
HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3
HRTIM_AUTODELAYEDMODE_REGULAR
HRTIM_BASICOCMODE_ACTIVE
HRTIM_BASICOCMODE_INACTIVE
HRTIM_BASICOCMODE_TOGGLE
HRTIM_BURSTDMA_CHPR
HRTIM_BURSTDMA_CMP1
HRTIM_BURSTDMA_CMP2
HRTIM_BURSTDMA_CMP3
HRTIM_BURSTDMA_CMP4
HRTIM_BURSTDMA_CNT
HRTIM_BURSTDMA_CR
HRTIM_BURSTDMA_CR2
HRTIM_BURSTDMA_DIER
HRTIM_BURSTDMA_DTR
HRTIM_BURSTDMA_EEFR1
HRTIM_BURSTDMA_EEFR2
HRTIM_BURSTDMA_EEFR3
HRTIM_BURSTDMA_FLTR
HRTIM_BURSTDMA_ICR
HRTIM_BURSTDMA_NONE
HRTIM_BURSTDMA_OUTR
HRTIM_BURSTDMA_PER
HRTIM_BURSTDMA_REP
HRTIM_BURSTDMA_RST1R
HRTIM_BURSTDMA_RST2R
HRTIM_BURSTDMA_RSTR
HRTIM_BURSTDMA_SET1R
HRTIM_BURSTDMA_SET2R
HRTIM_BURSTMODE_CONTINOUS
HRTIM_BURSTMODE_SINGLESHOT
HRTIM_BURSTMODECLOCKSOURCE_FHRTIM
HRTIM_BURSTMODECLOCKSOURCE_MASTER
HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC
HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC
HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO
HRTIM_BURSTMODECLOCKSOURCE_TIMER_A
HRTIM_BURSTMODECLOCKSOURCE_TIMER_B
HRTIM_BURSTMODECLOCKSOURCE_TIMER_C
HRTIM_BURSTMODECLOCKSOURCE_TIMER_D
HRTIM_BURSTMODECLOCKSOURCE_TIMER_E
HRTIM_BURSTMODECLOCKSOURCE_TIMER_F
HRTIM_BURSTMODECTL_DISABLED
HRTIM_BURSTMODECTL_ENABLED
HRTIM_BURSTMODEPRESCALER_DIV1
HRTIM_BURSTMODEPRESCALER_DIV1024
HRTIM_BURSTMODEPRESCALER_DIV128
HRTIM_BURSTMODEPRESCALER_DIV16
HRTIM_BURSTMODEPRESCALER_DIV16384
HRTIM_BURSTMODEPRESCALER_DIV2
HRTIM_BURSTMODEPRESCALER_DIV2048
HRTIM_BURSTMODEPRESCALER_DIV256
HRTIM_BURSTMODEPRESCALER_DIV32
HRTIM_BURSTMODEPRESCALER_DIV32768
HRTIM_BURSTMODEPRESCALER_DIV4
HRTIM_BURSTMODEPRESCALER_DIV4096
HRTIM_BURSTMODEPRESCALER_DIV512
HRTIM_BURSTMODEPRESCALER_DIV64
HRTIM_BURSTMODEPRESCALER_DIV8
HRTIM_BURSTMODEPRESCALER_DIV8192
HRTIM_BURSTMODESTATUS_NORMAL
HRTIM_BURSTMODESTATUS_ONGOING
HRTIM_BURSTMODETRIGGER_EVENT_7
HRTIM_BURSTMODETRIGGER_EVENT_8
HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP
HRTIM_BURSTMODETRIGGER_MASTER_CMP1
HRTIM_BURSTMODETRIGGER_MASTER_CMP2
HRTIM_BURSTMODETRIGGER_MASTER_CMP3
HRTIM_BURSTMODETRIGGER_MASTER_CMP4
HRTIM_BURSTMODETRIGGER_MASTER_REPETITION
HRTIM_BURSTMODETRIGGER_MASTER_RESET
HRTIM_BURSTMODETRIGGER_NONE
HRTIM_BURSTMODETRIGGER_TIMERA_CMP1
HRTIM_BURSTMODETRIGGER_TIMERA_CMP2
HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7
HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERA_RESET
HRTIM_BURSTMODETRIGGER_TIMERB_CMP1
HRTIM_BURSTMODETRIGGER_TIMERB_CMP2
HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERB_RESET
HRTIM_BURSTMODETRIGGER_TIMERC_CMP1
HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERC_RESET
HRTIM_BURSTMODETRIGGER_TIMERD_CMP2
HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8
HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERD_RESET
HRTIM_BURSTMODETRIGGER_TIMERE_CMP1
HRTIM_BURSTMODETRIGGER_TIMERE_CMP2
HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERF_CMP1
HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION
HRTIM_BURSTMODETRIGGER_TIMERF_RESET
HRTIM_CALIBRATIONRATE_0
HRTIM_CALIBRATIONRATE_1
HRTIM_CALIBRATIONRATE_2
HRTIM_CALIBRATIONRATE_3
HRTIM_CAPTUREFTRIGGER_NONE
HRTIM_CAPTUREFTRIGGER_TF1_RESET
HRTIM_CAPTUREFTRIGGER_TF1_SET
HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1
HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2
HRTIM_CAPTURETRIGGER_EEV_1
HRTIM_CAPTURETRIGGER_EEV_10
HRTIM_CAPTURETRIGGER_EEV_2
HRTIM_CAPTURETRIGGER_EEV_3
HRTIM_CAPTURETRIGGER_EEV_4
HRTIM_CAPTURETRIGGER_EEV_5
HRTIM_CAPTURETRIGGER_EEV_6
HRTIM_CAPTURETRIGGER_EEV_7
HRTIM_CAPTURETRIGGER_EEV_8
HRTIM_CAPTURETRIGGER_EEV_9
HRTIM_CAPTURETRIGGER_NONE
HRTIM_CAPTURETRIGGER_TA1_RESET
HRTIM_CAPTURETRIGGER_TA1_SET
HRTIM_CAPTURETRIGGER_TB1_RESET
HRTIM_CAPTURETRIGGER_TB1_SET
HRTIM_CAPTURETRIGGER_TC1_RESET
HRTIM_CAPTURETRIGGER_TC1_SET
HRTIM_CAPTURETRIGGER_TD1_RESET
HRTIM_CAPTURETRIGGER_TD1_SET
HRTIM_CAPTURETRIGGER_TE1_RESET
HRTIM_CAPTURETRIGGER_TE1_SET
HRTIM_CAPTURETRIGGER_TF1_RESET
HRTIM_CAPTURETRIGGER_TF1_SET
HRTIM_CAPTURETRIGGER_TIMERA_CMP1
HRTIM_CAPTURETRIGGER_TIMERA_CMP2
HRTIM_CAPTURETRIGGER_TIMERB_CMP1
HRTIM_CAPTURETRIGGER_TIMERB_CMP2
HRTIM_CAPTURETRIGGER_TIMERC_CMP1
HRTIM_CAPTURETRIGGER_TIMERC_CMP2
HRTIM_CAPTURETRIGGER_TIMERD_CMP1
HRTIM_CAPTURETRIGGER_TIMERD_CMP2
HRTIM_CAPTURETRIGGER_TIMERE_CMP1
HRTIM_CAPTURETRIGGER_TIMERE_CMP2
HRTIM_CAPTURETRIGGER_TIMERF_CMP1
HRTIM_CAPTURETRIGGER_TIMERF_CMP2
HRTIM_CAPTURETRIGGER_UPDATE
HRTIM_CAPTUREUNIT_1
HRTIM_CAPTUREUNIT_2
HRTIM_CHOPPER_DUTYCYCLE_0
HRTIM_CHOPPER_DUTYCYCLE_125
HRTIM_CHOPPER_DUTYCYCLE_250
HRTIM_CHOPPER_DUTYCYCLE_375
HRTIM_CHOPPER_DUTYCYCLE_500
HRTIM_CHOPPER_DUTYCYCLE_625
HRTIM_CHOPPER_DUTYCYCLE_750
HRTIM_CHOPPER_DUTYCYCLE_875
HRTIM_CHOPPER_PRESCALERRATIO_DIV112
HRTIM_CHOPPER_PRESCALERRATIO_DIV128
HRTIM_CHOPPER_PRESCALERRATIO_DIV144
HRTIM_CHOPPER_PRESCALERRATIO_DIV16
HRTIM_CHOPPER_PRESCALERRATIO_DIV160
HRTIM_CHOPPER_PRESCALERRATIO_DIV176
HRTIM_CHOPPER_PRESCALERRATIO_DIV192
HRTIM_CHOPPER_PRESCALERRATIO_DIV208
HRTIM_CHOPPER_PRESCALERRATIO_DIV224
HRTIM_CHOPPER_PRESCALERRATIO_DIV240
HRTIM_CHOPPER_PRESCALERRATIO_DIV256
HRTIM_CHOPPER_PRESCALERRATIO_DIV32
HRTIM_CHOPPER_PRESCALERRATIO_DIV48
HRTIM_CHOPPER_PRESCALERRATIO_DIV64
HRTIM_CHOPPER_PRESCALERRATIO_DIV80
HRTIM_CHOPPER_PRESCALERRATIO_DIV96
HRTIM_CHOPPER_PULSEWIDTH_112
HRTIM_CHOPPER_PULSEWIDTH_128
HRTIM_CHOPPER_PULSEWIDTH_144
HRTIM_CHOPPER_PULSEWIDTH_16
HRTIM_CHOPPER_PULSEWIDTH_160
HRTIM_CHOPPER_PULSEWIDTH_176
HRTIM_CHOPPER_PULSEWIDTH_192
HRTIM_CHOPPER_PULSEWIDTH_208
HRTIM_CHOPPER_PULSEWIDTH_224
HRTIM_CHOPPER_PULSEWIDTH_240
HRTIM_CHOPPER_PULSEWIDTH_256
HRTIM_CHOPPER_PULSEWIDTH_32
HRTIM_CHOPPER_PULSEWIDTH_48
HRTIM_CHOPPER_PULSEWIDTH_64
HRTIM_CHOPPER_PULSEWIDTH_80
HRTIM_CHOPPER_PULSEWIDTH_96
HRTIM_COMPAREUNIT_1
HRTIM_COMPAREUNIT_2
HRTIM_COMPAREUNIT_3
HRTIM_COMPAREUNIT_4
HRTIM_DACSYNC_DACTRIGOUT_1
HRTIM_DACSYNC_DACTRIGOUT_2
HRTIM_DACSYNC_DACTRIGOUT_3
HRTIM_DACSYNC_NONE
HRTIM_EEV10SRC_ADC5_AWD1
HRTIM_EEV10SRC_COMP7_OUT
HRTIM_EEV10SRC_GPIO
HRTIM_EEV10SRC_TIM6_TRGO
HRTIM_EEV1SRC_ADC1_AWD1
HRTIM_EEV1SRC_COMP2_OUT
HRTIM_EEV1SRC_GPIO
HRTIM_EEV1SRC_TIM1_TRGO
HRTIM_EEV2SRC_ADC1_AWD2
HRTIM_EEV2SRC_COMP4_OUT
HRTIM_EEV2SRC_GPIO
HRTIM_EEV2SRC_TIM2_TRGO
HRTIM_EEV3SRC_ADC1_AWD3
HRTIM_EEV3SRC_COMP6_OUT
HRTIM_EEV3SRC_GPIO
HRTIM_EEV3SRC_TIM3_TRGO
HRTIM_EEV4SRC_ADC2_AWD1
HRTIM_EEV4SRC_COMP1_OUT
HRTIM_EEV4SRC_COMP5_OUT
HRTIM_EEV4SRC_GPIO
HRTIM_EEV5SRC_ADC2_AWD2
HRTIM_EEV5SRC_COMP3_OUT
HRTIM_EEV5SRC_COMP7_OUT
HRTIM_EEV5SRC_GPIO
HRTIM_EEV6SRC_ADC2_AWD3
HRTIM_EEV6SRC_COMP1_OUT
HRTIM_EEV6SRC_COMP2_OUT
HRTIM_EEV6SRC_GPIO
HRTIM_EEV7SRC_ADC3_AWD1
HRTIM_EEV7SRC_COMP4_OUT
HRTIM_EEV7SRC_GPIO
HRTIM_EEV7SRC_TIM7_TRGO
HRTIM_EEV8SRC_ADC4_AWD1
HRTIM_EEV8SRC_COMP3_OUT
HRTIM_EEV8SRC_COMP6_OUT
HRTIM_EEV8SRC_GPIO
HRTIM_EEV9SRC_COMP4_OUT
HRTIM_EEV9SRC_COMP5_OUT
HRTIM_EEV9SRC_GPIO
HRTIM_EEV9SRC_TIM15_TRGO
HRTIM_EVENT_1
HRTIM_EVENT_10
HRTIM_EVENT_2
HRTIM_EVENT_3
HRTIM_EVENT_4
HRTIM_EVENT_5
HRTIM_EVENT_6
HRTIM_EVENT_7
HRTIM_EVENT_8
HRTIM_EVENT_9
HRTIM_EVENT_NONE
HRTIM_EVENTCOUNTER_A
HRTIM_EVENTCOUNTER_B
HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
HRTIM_EVENTFASTMODE_DISABLE
HRTIM_EVENTFASTMODE_ENABLE
HRTIM_EVENTFILTER_1
HRTIM_EVENTFILTER_10
HRTIM_EVENTFILTER_11
HRTIM_EVENTFILTER_12
HRTIM_EVENTFILTER_13
HRTIM_EVENTFILTER_14
HRTIM_EVENTFILTER_15
HRTIM_EVENTFILTER_2
HRTIM_EVENTFILTER_3
HRTIM_EVENTFILTER_4
HRTIM_EVENTFILTER_5
HRTIM_EVENTFILTER_6
HRTIM_EVENTFILTER_7
HRTIM_EVENTFILTER_8
HRTIM_EVENTFILTER_9
HRTIM_EVENTFILTER_NONE
HRTIM_EVENTPOLARITY_HIGH
HRTIM_EVENTPOLARITY_LOW
HRTIM_EVENTPRESCALER_DIV1
HRTIM_EVENTPRESCALER_DIV2
HRTIM_EVENTPRESCALER_DIV4
HRTIM_EVENTPRESCALER_DIV8
HRTIM_EVENTSENSITIVITY_BOTHEDGES
HRTIM_EVENTSENSITIVITY_FALLINGEDGE
HRTIM_EVENTSENSITIVITY_LEVEL
HRTIM_EVENTSENSITIVITY_RISINGEDGE
HRTIM_FAULT_1
HRTIM_FAULT_2
HRTIM_FAULT_3
HRTIM_FAULT_4
HRTIM_FAULT_5
HRTIM_FAULT_6
HRTIM_FAULTBLANKINGCTL_DISABLED
HRTIM_FAULTBLANKINGCTL_ENABLED
HRTIM_FAULTBLANKINGMODE_MOVING
HRTIM_FAULTBLANKINGMODE_RSTALIGNED
HRTIM_FAULTCOUNTER_1
HRTIM_FAULTCOUNTER_10
HRTIM_FAULTCOUNTER_11
HRTIM_FAULTCOUNTER_12
HRTIM_FAULTCOUNTER_13
HRTIM_FAULTCOUNTER_14
HRTIM_FAULTCOUNTER_15
HRTIM_FAULTCOUNTER_2
HRTIM_FAULTCOUNTER_3
HRTIM_FAULTCOUNTER_4
HRTIM_FAULTCOUNTER_5
HRTIM_FAULTCOUNTER_6
HRTIM_FAULTCOUNTER_7
HRTIM_FAULTCOUNTER_8
HRTIM_FAULTCOUNTER_9
HRTIM_FAULTCOUNTER_NONE
HRTIM_FAULTCOUNTERRST_CONDITIONAL
HRTIM_FAULTCOUNTERRST_UNCONDITIONAL
HRTIM_FAULTFILTER_1
HRTIM_FAULTFILTER_10
HRTIM_FAULTFILTER_11
HRTIM_FAULTFILTER_12
HRTIM_FAULTFILTER_13
HRTIM_FAULTFILTER_14
HRTIM_FAULTFILTER_15
HRTIM_FAULTFILTER_2
HRTIM_FAULTFILTER_3
HRTIM_FAULTFILTER_4
HRTIM_FAULTFILTER_5
HRTIM_FAULTFILTER_6
HRTIM_FAULTFILTER_7
HRTIM_FAULTFILTER_8
HRTIM_FAULTFILTER_9
HRTIM_FAULTFILTER_NONE
HRTIM_FAULTLOCK_READONLY
HRTIM_FAULTLOCK_READWRITE
HRTIM_FAULTMODECTL_DISABLED
HRTIM_FAULTMODECTL_ENABLED
HRTIM_FAULTPOLARITY_HIGH
HRTIM_FAULTPOLARITY_LOW
HRTIM_FAULTPRESCALER_DIV1
HRTIM_FAULTPRESCALER_DIV2
HRTIM_FAULTPRESCALER_DIV4
HRTIM_FAULTPRESCALER_DIV8
HRTIM_FAULTSOURCE_DIGITALINPUT
HRTIM_FAULTSOURCE_EEVINPUT
HRTIM_FAULTSOURCE_INTERNAL
HRTIM_FLAG_BMPER
HRTIM_FLAG_DLLRDY
HRTIM_FLAG_FLT1
HRTIM_FLAG_FLT2
HRTIM_FLAG_FLT3
HRTIM_FLAG_FLT4
HRTIM_FLAG_FLT5
HRTIM_FLAG_FLT6
HRTIM_FLAG_SYSFLT
HRTIM_HALFMODE_DISABLED
HRTIM_HALFMODE_ENABLED
HRTIM_INTERLEAVED_MODE_DISABLED
HRTIM_INTERLEAVED_MODE_DUAL
HRTIM_INTERLEAVED_MODE_QUAD
HRTIM_INTERLEAVED_MODE_TRIPLE
HRTIM_IT_BMPER
HRTIM_IT_DLLRDY
HRTIM_IT_FLT1
HRTIM_IT_FLT2
HRTIM_IT_FLT3
HRTIM_IT_FLT4
HRTIM_IT_FLT5
HRTIM_IT_FLT6
HRTIM_IT_NONE
HRTIM_IT_SYSFLT
HRTIM_MASTER_DMA_MCMP1
HRTIM_MASTER_DMA_MCMP2
HRTIM_MASTER_DMA_MCMP3
HRTIM_MASTER_DMA_MCMP4
HRTIM_MASTER_DMA_MREP
HRTIM_MASTER_DMA_MUPD
HRTIM_MASTER_DMA_NONE
HRTIM_MASTER_DMA_SYNC
HRTIM_MASTER_FLAG_MCMP1
HRTIM_MASTER_FLAG_MCMP2
HRTIM_MASTER_FLAG_MCMP3
HRTIM_MASTER_FLAG_MCMP4
HRTIM_MASTER_FLAG_MREP
HRTIM_MASTER_FLAG_MUPD
HRTIM_MASTER_FLAG_SYNC
HRTIM_MASTER_IT_MCMP1
HRTIM_MASTER_IT_MCMP2
HRTIM_MASTER_IT_MCMP3
HRTIM_MASTER_IT_MCMP4
HRTIM_MASTER_IT_MREP
HRTIM_MASTER_IT_MUPD
HRTIM_MASTER_IT_NONE
HRTIM_MASTER_IT_SYNC
HRTIM_MODE_CONTINUOUS
HRTIM_MODE_SINGLESHOT
HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
HRTIM_OUTPUT_TA1
HRTIM_OUTPUT_TA2
HRTIM_OUTPUT_TB1
HRTIM_OUTPUT_TB2
HRTIM_OUTPUT_TC1
HRTIM_OUTPUT_TC2
HRTIM_OUTPUT_TD1
HRTIM_OUTPUT_TD2
HRTIM_OUTPUT_TE1
HRTIM_OUTPUT_TE2
HRTIM_OUTPUT_TF1
HRTIM_OUTPUT_TF2
HRTIM_OUTPUTBIAR_DISABLED
HRTIM_OUTPUTBIAR_ENABLED
HRTIM_OUTPUTBURSTMODEENTRY_DELAYED
HRTIM_OUTPUTBURSTMODEENTRY_REGULAR
HRTIM_OUTPUTCHOPPERMODE_DISABLED
HRTIM_OUTPUTCHOPPERMODE_ENABLED
HRTIM_OUTPUTFAULTLEVEL_ACTIVE
HRTIM_OUTPUTFAULTLEVEL_HIGHZ
HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM_OUTPUTFAULTLEVEL_NONE
HRTIM_OUTPUTIDLELEVEL_ACTIVE
HRTIM_OUTPUTIDLELEVEL_INACTIVE
HRTIM_OUTPUTIDLEMODE_IDLE
HRTIM_OUTPUTIDLEMODE_NONE
HRTIM_OUTPUTLEVEL_ACTIVE
HRTIM_OUTPUTLEVEL_INACTIVE
HRTIM_OUTPUTPOLARITY_HIGH
HRTIM_OUTPUTPOLARITY_LOW
HRTIM_OUTPUTRESET_EEV_1
HRTIM_OUTPUTRESET_EEV_10
HRTIM_OUTPUTRESET_EEV_2
HRTIM_OUTPUTRESET_EEV_3
HRTIM_OUTPUTRESET_EEV_4
HRTIM_OUTPUTRESET_EEV_5
HRTIM_OUTPUTRESET_EEV_6
HRTIM_OUTPUTRESET_EEV_7
HRTIM_OUTPUTRESET_EEV_8
HRTIM_OUTPUTRESET_EEV_9
HRTIM_OUTPUTRESET_MASTERCMP1
HRTIM_OUTPUTRESET_MASTERCMP2
HRTIM_OUTPUTRESET_MASTERCMP3
HRTIM_OUTPUTRESET_MASTERCMP4
HRTIM_OUTPUTRESET_MASTERPER
HRTIM_OUTPUTRESET_NONE
HRTIM_OUTPUTRESET_RESYNC
HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
HRTIM_OUTPUTRESET_TIMCMP1
HRTIM_OUTPUTRESET_TIMCMP2
HRTIM_OUTPUTRESET_TIMCMP3
HRTIM_OUTPUTRESET_TIMCMP4
HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
HRTIM_OUTPUTRESET_TIMPER
HRTIM_OUTPUTRESET_UPDATE
HRTIM_OUTPUTSET_EEV_1
HRTIM_OUTPUTSET_EEV_10
HRTIM_OUTPUTSET_EEV_2
HRTIM_OUTPUTSET_EEV_3
HRTIM_OUTPUTSET_EEV_4
HRTIM_OUTPUTSET_EEV_5
HRTIM_OUTPUTSET_EEV_6
HRTIM_OUTPUTSET_EEV_7
HRTIM_OUTPUTSET_EEV_8
HRTIM_OUTPUTSET_EEV_9
HRTIM_OUTPUTSET_MASTERCMP1
HRTIM_OUTPUTSET_MASTERCMP2
HRTIM_OUTPUTSET_MASTERCMP3
HRTIM_OUTPUTSET_MASTERCMP4
HRTIM_OUTPUTSET_MASTERPER
HRTIM_OUTPUTSET_NONE
HRTIM_OUTPUTSET_RESYNC
HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
HRTIM_OUTPUTSET_TIMCMP1
HRTIM_OUTPUTSET_TIMCMP2
HRTIM_OUTPUTSET_TIMCMP3
HRTIM_OUTPUTSET_TIMCMP4
HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
HRTIM_OUTPUTSET_TIMPER
HRTIM_OUTPUTSET_UPDATE
HRTIM_OUTPUTSTATE_FAULT
HRTIM_OUTPUTSTATE_IDLE
HRTIM_OUTPUTSTATE_RUN
HRTIM_PRELOAD_DISABLED
HRTIM_PRELOAD_ENABLED
HRTIM_PRESCALERRATIO_DIV1
HRTIM_PRESCALERRATIO_DIV2
HRTIM_PRESCALERRATIO_DIV4
HRTIM_PRESCALERRATIO_MUL16
HRTIM_PRESCALERRATIO_MUL2
HRTIM_PRESCALERRATIO_MUL32
HRTIM_PRESCALERRATIO_MUL4
HRTIM_PRESCALERRATIO_MUL8
HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1
HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2
HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1
HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2
HRTIM_SINGLE_CALIBRATION
HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT
HRTIM_SYNCINPUTSOURCE_INTERNALEVENT
HRTIM_SYNCINPUTSOURCE_NONE
HRTIM_SYNCOPTION_MASTER
HRTIM_SYNCOPTION_NONE
HRTIM_SYNCOPTION_SLAVE
HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE
HRTIM_SYNCOUTPUTPOLARITY_NONE
HRTIM_SYNCOUTPUTPOLARITY_POSITIVE
HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1
HRTIM_SYNCOUTPUTSOURCE_MASTER_START
HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1
HRTIM_SYNCOUTPUTSOURCE_TIMA_START
HRTIM_SYNCRESET_DISABLED
HRTIM_SYNCRESET_ENABLED
HRTIM_SYNCSTART_DISABLED
HRTIM_SYNCSTART_ENABLED
HRTIM_TAOEN_MASK
HRTIM_TBOEN_MASK
HRTIM_TCOEN_MASK
HRTIM_TDOEN_MASK
HRTIM_TEOEN_MASK
HRTIM_TFOEN_MASK
HRTIM_TIM_ADROM_BOTH
HRTIM_TIM_ADROM_CREST
HRTIM_TIM_ADROM_VALLEY
HRTIM_TIM_BMROM_BOTH
HRTIM_TIM_BMROM_CREST
HRTIM_TIM_BMROM_VALLEY
HRTIM_TIM_DMA_CMP1
HRTIM_TIM_DMA_CMP2
HRTIM_TIM_DMA_CMP3
HRTIM_TIM_DMA_CMP4
HRTIM_TIM_DMA_CPT1
HRTIM_TIM_DMA_CPT2
HRTIM_TIM_DMA_DLYPRT
HRTIM_TIM_DMA_NONE
HRTIM_TIM_DMA_REP
HRTIM_TIM_DMA_RST
HRTIM_TIM_DMA_RST1
HRTIM_TIM_DMA_RST2
HRTIM_TIM_DMA_SET1
HRTIM_TIM_DMA_SET2
HRTIM_TIM_DMA_UPD
HRTIM_TIM_FEROM_BOTH
HRTIM_TIM_FEROM_CREST
HRTIM_TIM_FEROM_VALLEY
HRTIM_TIM_FLAG_CMP1
HRTIM_TIM_FLAG_CMP2
HRTIM_TIM_FLAG_CMP3
HRTIM_TIM_FLAG_CMP4
HRTIM_TIM_FLAG_CPT1
HRTIM_TIM_FLAG_CPT2
HRTIM_TIM_FLAG_DLYPRT
HRTIM_TIM_FLAG_REP
HRTIM_TIM_FLAG_RST
HRTIM_TIM_FLAG_RST1
HRTIM_TIM_FLAG_RST2
HRTIM_TIM_FLAG_SET1
HRTIM_TIM_FLAG_SET2
HRTIM_TIM_FLAG_UPD
HRTIM_TIM_IT_CMP1
HRTIM_TIM_IT_CMP2
HRTIM_TIM_IT_CMP3
HRTIM_TIM_IT_CMP4
HRTIM_TIM_IT_CPT1
HRTIM_TIM_IT_CPT2
HRTIM_TIM_IT_DLYPRT
HRTIM_TIM_IT_NONE
HRTIM_TIM_IT_REP
HRTIM_TIM_IT_RST
HRTIM_TIM_IT_RST1
HRTIM_TIM_IT_RST2
HRTIM_TIM_IT_SET1
HRTIM_TIM_IT_SET2
HRTIM_TIM_IT_UPD
HRTIM_TIM_OUTROM_BOTH
HRTIM_TIM_OUTROM_CREST
HRTIM_TIM_OUTROM_VALLEY
HRTIM_TIM_ROM_BOTH
HRTIM_TIM_ROM_CREST
HRTIM_TIM_ROM_VALLEY
HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY
HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE
HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE
HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE
HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY
HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4
HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL16
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8
HRTIM_TIMDEADTIME_RISINGLOCK_READONLY
HRTIM_TIMDEADTIME_RISINGLOCK_WRITE
HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE
HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE
HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY
HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE
HRTIM_TIMDEADTIMEINSERTION_DISABLED
HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4
HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2
HRTIM_TIMEEVFLT_BLANKINGCMP1
HRTIM_TIMEEVFLT_BLANKINGCMP2
HRTIM_TIMEEVFLT_BLANKINGCMP3
HRTIM_TIMEEVFLT_BLANKINGCMP4
HRTIM_TIMEEVFLT_NONE
HRTIM_TIMEEVFLT_WINDOWINGCMP2
HRTIM_TIMEEVFLT_WINDOWINGCMP3
HRTIM_TIMEEVFLT_WINDOWINGTIM
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8
HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED
HRTIM_TIMER_DCDE_DISABLED
HRTIM_TIMER_DCDE_ENABLED
HRTIM_TIMER_DCDR_COUNTER
HRTIM_TIMER_DCDR_OUT1SET
HRTIM_TIMER_DCDS_CMP2
HRTIM_TIMER_DCDS_OUT1RST
HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9
HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8
HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED
HRTIM_TIMERBURSTMODE_MAINTAINCLOCK
HRTIM_TIMERBURSTMODE_RESETCOUNTER
HRTIM_TIMERESYNC_UPDATE_CONDITIONAL
HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL
HRTIM_TIMERGTCMP1_EQUAL
HRTIM_TIMERGTCMP1_GREATER
HRTIM_TIMERGTCMP3_EQUAL
HRTIM_TIMERGTCMP3_GREATER
HRTIM_TIMERID_MASTER
HRTIM_TIMERID_TIMER_A
HRTIM_TIMERID_TIMER_B
HRTIM_TIMERID_TIMER_C
HRTIM_TIMERID_TIMER_D
HRTIM_TIMERID_TIMER_E
HRTIM_TIMERID_TIMER_F
HRTIM_TIMERINDEX_COMMON
HRTIM_TIMERINDEX_MASTER
HRTIM_TIMERINDEX_TIMER_A
HRTIM_TIMERINDEX_TIMER_B
HRTIM_TIMERINDEX_TIMER_C
HRTIM_TIMERINDEX_TIMER_D
HRTIM_TIMERINDEX_TIMER_E
HRTIM_TIMERINDEX_TIMER_F
HRTIM_TIMERRESET_MASTER
HRTIM_TIMERRESET_TIMER_A
HRTIM_TIMERRESET_TIMER_B
HRTIM_TIMERRESET_TIMER_C
HRTIM_TIMERRESET_TIMER_D
HRTIM_TIMERRESET_TIMER_E
HRTIM_TIMERRESET_TIMER_F
HRTIM_TIMERSWAP_A
HRTIM_TIMERSWAP_B
HRTIM_TIMERSWAP_C
HRTIM_TIMERSWAP_D
HRTIM_TIMERSWAP_E
HRTIM_TIMERSWAP_F
HRTIM_TIMERTRIGHALF_DISABLED
HRTIM_TIMERTRIGHALF_ENABLED
HRTIM_TIMERUPDATE_A
HRTIM_TIMERUPDATE_B
HRTIM_TIMERUPDATE_C
HRTIM_TIMERUPDATE_D
HRTIM_TIMERUPDATE_E
HRTIM_TIMERUPDATE_F
HRTIM_TIMERUPDATE_MASTER
HRTIM_TIMERUPDOWNMODE_UP
HRTIM_TIMERUPDOWNMODE_UPDOWN
HRTIM_TIMEVENTLATCH_DISABLED
HRTIM_TIMEVENTLATCH_ENABLED
HRTIM_TIMFAULTENABLE_FAULT1
HRTIM_TIMFAULTENABLE_FAULT2
HRTIM_TIMFAULTENABLE_FAULT3
HRTIM_TIMFAULTENABLE_FAULT4
HRTIM_TIMFAULTENABLE_FAULT5
HRTIM_TIMFAULTENABLE_FAULT6
HRTIM_TIMFAULTENABLE_NONE
HRTIM_TIMFAULTLOCK_READONLY
HRTIM_TIMFAULTLOCK_READWRITE
HRTIM_TIMPUSHPULLMODE_DISABLED
HRTIM_TIMPUSHPULLMODE_ENABLED
HRTIM_TIMRESETTRIGGER_CMP2
HRTIM_TIMRESETTRIGGER_CMP4
HRTIM_TIMRESETTRIGGER_EEV_1
HRTIM_TIMRESETTRIGGER_EEV_10
HRTIM_TIMRESETTRIGGER_EEV_2
HRTIM_TIMRESETTRIGGER_EEV_3
HRTIM_TIMRESETTRIGGER_EEV_4
HRTIM_TIMRESETTRIGGER_EEV_5
HRTIM_TIMRESETTRIGGER_EEV_6
HRTIM_TIMRESETTRIGGER_EEV_7
HRTIM_TIMRESETTRIGGER_EEV_8
HRTIM_TIMRESETTRIGGER_EEV_9
HRTIM_TIMRESETTRIGGER_MASTER_CMP1
HRTIM_TIMRESETTRIGGER_MASTER_CMP2
HRTIM_TIMRESETTRIGGER_MASTER_CMP3
HRTIM_TIMRESETTRIGGER_MASTER_CMP4
HRTIM_TIMRESETTRIGGER_MASTER_PER
HRTIM_TIMRESETTRIGGER_NONE
HRTIM_TIMRESETTRIGGER_OTHER1_CMP1
HRTIM_TIMRESETTRIGGER_OTHER1_CMP2
HRTIM_TIMRESETTRIGGER_OTHER1_CMP4
HRTIM_TIMRESETTRIGGER_OTHER2_CMP1
HRTIM_TIMRESETTRIGGER_OTHER2_CMP2
HRTIM_TIMRESETTRIGGER_OTHER2_CMP4
HRTIM_TIMRESETTRIGGER_OTHER3_CMP1
HRTIM_TIMRESETTRIGGER_OTHER3_CMP2
HRTIM_TIMRESETTRIGGER_OTHER3_CMP4
HRTIM_TIMRESETTRIGGER_OTHER4_CMP1
HRTIM_TIMRESETTRIGGER_OTHER4_CMP2
HRTIM_TIMRESETTRIGGER_OTHER4_CMP4
HRTIM_TIMRESETTRIGGER_OTHER5_CMP1
HRTIM_TIMRESETTRIGGER_OTHER5_CMP2
HRTIM_TIMRESETTRIGGER_UPDATE
HRTIM_TIMUPDATEONRESET_DISABLED
HRTIM_TIMUPDATEONRESET_ENABLED
HRTIM_TIMUPDATETRIGGER_MASTER
HRTIM_TIMUPDATETRIGGER_NONE
HRTIM_TIMUPDATETRIGGER_TIMER_A
HRTIM_TIMUPDATETRIGGER_TIMER_B
HRTIM_TIMUPDATETRIGGER_TIMER_C
HRTIM_TIMUPDATETRIGGER_TIMER_D
HRTIM_TIMUPDATETRIGGER_TIMER_E
HRTIM_TIMUPDATETRIGGER_TIMER_F
HRTIM_UPDATEGATING_DMABURST
HRTIM_UPDATEGATING_DMABURST_UPDATE
HRTIM_UPDATEGATING_INDEPENDENT
HRTIM_UPDATEGATING_UPDEN1
HRTIM_UPDATEGATING_UPDEN1_UPDATE
HRTIM_UPDATEGATING_UPDEN2
HRTIM_UPDATEGATING_UPDEN2_UPDATE
HRTIM_UPDATEGATING_UPDEN3
HRTIM_UPDATEGATING_UPDEN3_UPDATE
HRTIM_UPDATEONREPETITION_DISABLED
HRTIM_UPDATEONREPETITION_ENABLED
IS_HRTIM_ADCEXTTRIGGER
IS_HRTIM_ADCTRIGGER
IS_HRTIM_ADCTRIGGERUPDATE
IS_HRTIM_AUTODELAYEDMODE
IS_HRTIM_BASICOCMODE
IS_HRTIM_BURSTMODE
IS_HRTIM_BURSTMODECLOCKSOURCE
IS_HRTIM_BURSTMODECTL
IS_HRTIM_BURSTMODEPRELOAD
IS_HRTIM_BURSTMODETRIGGER
IS_HRTIM_CALIBRATIONRATE
IS_HRTIM_CAPTUREUNIT
IS_HRTIM_CHOPPER_DUTYCYCLE
IS_HRTIM_CHOPPER_PRESCALERRATIO
IS_HRTIM_CHOPPER_PULSEWIDTH
IS_HRTIM_COMPAREUNIT
IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE
IS_HRTIM_DACSYNC
IS_HRTIM_DUALDAC_ENABLE
IS_HRTIM_DUALDAC_RESET
IS_HRTIM_DUALDAC_STEP
IS_HRTIM_EVENT
IS_HRTIM_EVENTFASTMODE
IS_HRTIM_EVENTFILTER
IS_HRTIM_EVENTPOLARITY
IS_HRTIM_EVENTPRESCALER
IS_HRTIM_EVENTSENSITIVITY
IS_HRTIM_EVENTSRC
IS_HRTIM_FAULT
IS_HRTIM_FAULTBLANKING
IS_HRTIM_FAULTBLANKINGCTL
IS_HRTIM_FAULTBLANKNGMODE
IS_HRTIM_FAULTCOUNTER
IS_HRTIM_FAULTCOUNTERRST
IS_HRTIM_FAULTFILTER
IS_HRTIM_FAULTLOCK
IS_HRTIM_FAULTMODECTL
IS_HRTIM_FAULTPOLARITY
IS_HRTIM_FAULTPRESCALER
IS_HRTIM_FAULTSOURCE
IS_HRTIM_HALFMODE
IS_HRTIM_HRTIM_BURSTMODEPRESCALER
IS_HRTIM_INTERLEAVEDMODE
IS_HRTIM_IT
IS_HRTIM_MASTER_DMA
IS_HRTIM_MASTER_IT
IS_HRTIM_MODE
IS_HRTIM_MODE_ONEPULSE
IS_HRTIM_OUTPUT
IS_HRTIM_OUTPUTBALANCEDIDLE
IS_HRTIM_OUTPUTBURSTMODEENTRY
IS_HRTIM_OUTPUTCHOPPERMODE
IS_HRTIM_OUTPUTFAULTLEVEL
IS_HRTIM_OUTPUTIDLELEVEL
IS_HRTIM_OUTPUTIDLEMODE
IS_HRTIM_OUTPUTLEVEL
IS_HRTIM_OUTPUTPOLARITY
IS_HRTIM_OUTPUTPULSE
IS_HRTIM_OUTPUTRESET
IS_HRTIM_OUTPUTSET
IS_HRTIM_PRELOAD
IS_HRTIM_PRESCALERRATIO
IS_HRTIM_ROLLOVERMODE
IS_HRTIM_SYNCINPUTSOURCE
IS_HRTIM_SYNCOUTPUTPOLARITY
IS_HRTIM_SYNCOUTPUTSOURCE
IS_HRTIM_SYNCRESET
IS_HRTIM_SYNCSTART
IS_HRTIM_TIM_DMA
IS_HRTIM_TIM_IT
IS_HRTIM_TIMDEADTIME_FALLINGLOCK
IS_HRTIM_TIMDEADTIME_FALLINGSIGN
IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK
IS_HRTIM_TIMDEADTIME_PRESCALERRATIO
IS_HRTIM_TIMDEADTIME_RISINGLOCK
IS_HRTIM_TIMDEADTIME_RISINGSIGN
IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK
IS_HRTIM_TIMDEADTIMEINSERTION
IS_HRTIM_TIMDELAYEDPROTECTION
IS_HRTIM_TIMEEVENT
IS_HRTIM_TIMEEVENT_COUNTER
IS_HRTIM_TIMEEVENT_RESETMODE
IS_HRTIM_TIMEEVENT_SOURCE
IS_HRTIM_TIMER_BURSTDMA
IS_HRTIM_TIMER_CAPTUREFTRIGGER
IS_HRTIM_TIMER_CAPTURETRIGGER
IS_HRTIM_TIMER_OUTPUT
IS_HRTIM_TIMERBURSTMODE
IS_HRTIM_TIMERGTCMP1
IS_HRTIM_TIMERGTCMP3
IS_HRTIM_TIMERID
IS_HRTIM_TIMERINDEX
IS_HRTIM_TIMERRESET
IS_HRTIM_TIMERSWAP
IS_HRTIM_TIMERTRGHLFMODE
IS_HRTIM_TIMERUPDATE
IS_HRTIM_TIMERUPDOWNMODE
IS_HRTIM_TIMEVENTFILTER
IS_HRTIM_TIMEVENTLATCH
IS_HRTIM_TIMFAULTENABLE
IS_HRTIM_TIMFAULTLOCK
IS_HRTIM_TIMING_UNIT
IS_HRTIM_TIMPUSHPULLMODE
IS_HRTIM_TIMRESETTRIGGER
IS_HRTIM_TIMSYNCUPDATE
IS_HRTIM_TIMUPDATEONRESET
IS_HRTIM_TIMUPDATETRIGGER
IS_HRTIM_UPDATEGATING_MASTER
IS_HRTIM_UPDATEGATING_TIM
IS_HRTIM_UPDATEONREPETITION
MAX_HRTIM_TIMER
HRTIM_HandleTypeDef
pHRTIM_CallbackTypeDef
pHRTIM_TIMxCallbackTypeDef
HAL_HRTIM_CallbackIDTypeDef
HAL_HRTIM_StateTypeDef
HAL_HRTIM_ADCPostScalerConfig
HAL_HRTIM_ADCTriggerConfig
HAL_HRTIM_BurstDMAConfig
HAL_HRTIM_BurstDMATransfer
HAL_HRTIM_BurstDMATransferCallback
HAL_HRTIM_BurstModeConfig
HAL_HRTIM_BurstModeCtl
HAL_HRTIM_BurstModePeriodCallback
HAL_HRTIM_BurstModeSoftwareTrigger
HAL_HRTIM_Capture1EventCallback
HAL_HRTIM_Capture2EventCallback
HAL_HRTIM_ChopperModeConfig
HAL_HRTIM_Compare1EventCallback
HAL_HRTIM_Compare2EventCallback
HAL_HRTIM_Compare3EventCallback
HAL_HRTIM_Compare4EventCallback
HAL_HRTIM_CounterResetCallback
HAL_HRTIM_DeadTimeConfig
HAL_HRTIM_DeInit
HAL_HRTIM_DelayedProtectionCallback
HAL_HRTIM_DLLCalibrationReadyCallback
HAL_HRTIM_DLLCalibrationStart
HAL_HRTIM_DLLCalibrationStart_IT
HAL_HRTIM_ErrorCallback
HAL_HRTIM_EventConfig
HAL_HRTIM_EventPrescalerConfig
HAL_HRTIM_ExtEventCounterConfig
HAL_HRTIM_ExtEventCounterDisable
HAL_HRTIM_ExtEventCounterEnable
HAL_HRTIM_ExtEventCounterReset
HAL_HRTIM_Fault1Callback
HAL_HRTIM_Fault2Callback
HAL_HRTIM_Fault3Callback
HAL_HRTIM_Fault4Callback
HAL_HRTIM_Fault5Callback
HAL_HRTIM_Fault6Callback
HAL_HRTIM_FaultBlankingConfigAndEnable
HAL_HRTIM_FaultConfig
HAL_HRTIM_FaultCounterConfig
HAL_HRTIM_FaultCounterReset
HAL_HRTIM_FaultModeCtl
HAL_HRTIM_FaultPrescalerConfig
HAL_HRTIM_GetBurstStatus
HAL_HRTIM_GetCaptured
HAL_HRTIM_GetCapturedDir
HAL_HRTIM_GetCapturedValue
HAL_HRTIM_GetCurrentPushPullStatus
HAL_HRTIM_GetDelayedProtectionStatus
HAL_HRTIM_GetIdlePushPullStatus
HAL_HRTIM_GetState
HAL_HRTIM_Init
HAL_HRTIM_IRQHandler
HAL_HRTIM_MspDeInit
HAL_HRTIM_MspInit
HAL_HRTIM_Output1ResetCallback
HAL_HRTIM_Output1SetCallback
HAL_HRTIM_Output2ResetCallback
HAL_HRTIM_Output2SetCallback
HAL_HRTIM_OutputSwapDisable
HAL_HRTIM_OutputSwapEnable
HAL_HRTIM_PollForDLLCalibration
HAL_HRTIM_RegisterCallback
HAL_HRTIM_RegistersUpdateCallback
HAL_HRTIM_RepetitionEventCallback
HAL_HRTIM_RollOverModeConfig
HAL_HRTIM_SimpleBaseStart
HAL_HRTIM_SimpleBaseStart_DMA
HAL_HRTIM_SimpleBaseStart_IT
HAL_HRTIM_SimpleBaseStop
HAL_HRTIM_SimpleBaseStop_DMA
HAL_HRTIM_SimpleBaseStop_IT
HAL_HRTIM_SimpleCaptureChannelConfig
HAL_HRTIM_SimpleCaptureStart
HAL_HRTIM_SimpleCaptureStart_DMA
HAL_HRTIM_SimpleCaptureStart_IT
HAL_HRTIM_SimpleCaptureStop
HAL_HRTIM_SimpleCaptureStop_DMA
HAL_HRTIM_SimpleCaptureStop_IT
HAL_HRTIM_SimpleOCChannelConfig
HAL_HRTIM_SimpleOCStart
HAL_HRTIM_SimpleOCStart_DMA
HAL_HRTIM_SimpleOCStart_IT
HAL_HRTIM_SimpleOCStop
HAL_HRTIM_SimpleOCStop_DMA
HAL_HRTIM_SimpleOCStop_IT
HAL_HRTIM_SimpleOnePulseChannelConfig
HAL_HRTIM_SimpleOnePulseStart
HAL_HRTIM_SimpleOnePulseStart_IT
HAL_HRTIM_SimpleOnePulseStop
HAL_HRTIM_SimpleOnePulseStop_IT
HAL_HRTIM_SimplePWMChannelConfig
HAL_HRTIM_SimplePWMStart
HAL_HRTIM_SimplePWMStart_DMA
HAL_HRTIM_SimplePWMStart_IT
HAL_HRTIM_SimplePWMStop
HAL_HRTIM_SimplePWMStop_DMA
HAL_HRTIM_SimplePWMStop_IT
HAL_HRTIM_SoftwareCapture
HAL_HRTIM_SoftwareReset
HAL_HRTIM_SoftwareUpdate
HAL_HRTIM_SwapTimerOutput
HAL_HRTIM_SynchronizationEventCallback
HAL_HRTIM_SystemFaultCallback
HAL_HRTIM_TimeBaseConfig
HAL_HRTIM_TimerDualChannelDacConfig
HAL_HRTIM_TimerEventFilteringConfig
HAL_HRTIM_TIMxRegisterCallback
HAL_HRTIM_TIMxUnRegisterCallback
HAL_HRTIM_UnRegisterCallback
HAL_HRTIM_UpdateDisable
HAL_HRTIM_UpdateEnable
HAL_HRTIM_WaveformCaptureConfig
HAL_HRTIM_WaveformCompareConfig
HAL_HRTIM_WaveformCountStart
HAL_HRTIM_WaveformCountStart_DMA
HAL_HRTIM_WaveformCountStart_IT
HAL_HRTIM_WaveformCountStop
HAL_HRTIM_WaveformCountStop_DMA
HAL_HRTIM_WaveformCountStop_IT
HAL_HRTIM_WaveformGetOutputLevel
HAL_HRTIM_WaveformGetOutputState
HAL_HRTIM_WaveformOutputConfig
HAL_HRTIM_WaveformOutputStart
HAL_HRTIM_WaveformOutputStop
HAL_HRTIM_WaveformSetOutputLevel
HAL_HRTIM_WaveformTimerConfig
HAL_HRTIM_WaveformTimerControl
stm32g4xx_hal_i2c.c
I2C_NO_OPTION_FRAME
I2C_STATE_MASTER_BUSY_RX
I2C_STATE_MASTER_BUSY_TX
I2C_STATE_MEM_BUSY_RX
I2C_STATE_MEM_BUSY_TX
I2C_STATE_MSK
I2C_STATE_NONE
I2C_STATE_SLAVE_BUSY_RX
I2C_STATE_SLAVE_BUSY_TX
I2C_TIMEOUT_ADDR
I2C_TIMEOUT_BUSY
I2C_TIMEOUT_DIR
I2C_TIMEOUT_FLAG
I2C_TIMEOUT_RXNE
I2C_TIMEOUT_STOPF
I2C_TIMEOUT_TC
I2C_TIMEOUT_TCR
I2C_TIMEOUT_TXIS
I2C_XFER_CPLT_IT
I2C_XFER_ERROR_IT
I2C_XFER_LISTEN_IT
I2C_XFER_RELOAD_IT
I2C_XFER_RX_IT
I2C_XFER_TX_IT
MAX_NBYTE_SIZE
SLAVE_ADDR_MSK
SLAVE_ADDR_SHIFT
TIMING_CLEAR_MASK
HAL_I2C_AbortCpltCallback
HAL_I2C_AddrCallback
HAL_I2C_DeInit
HAL_I2C_DisableListen_IT
HAL_I2C_EnableListen_IT
HAL_I2C_ER_IRQHandler
HAL_I2C_ErrorCallback
HAL_I2C_EV_IRQHandler
HAL_I2C_GetError
HAL_I2C_GetMode
HAL_I2C_GetState
HAL_I2C_Init
HAL_I2C_IsDeviceReady
HAL_I2C_ListenCpltCallback
HAL_I2C_Master_Abort_IT
HAL_I2C_Master_Receive
HAL_I2C_Master_Receive_DMA
HAL_I2C_Master_Receive_IT
HAL_I2C_Master_Seq_Receive_DMA
HAL_I2C_Master_Seq_Receive_IT
HAL_I2C_Master_Seq_Transmit_DMA
HAL_I2C_Master_Seq_Transmit_IT
HAL_I2C_Master_Transmit
HAL_I2C_Master_Transmit_DMA
HAL_I2C_Master_Transmit_IT
HAL_I2C_MasterRxCpltCallback
HAL_I2C_MasterTxCpltCallback
HAL_I2C_Mem_Read
HAL_I2C_Mem_Read_DMA
HAL_I2C_Mem_Read_IT
HAL_I2C_Mem_Write
HAL_I2C_Mem_Write_DMA
HAL_I2C_Mem_Write_IT
HAL_I2C_MemRxCpltCallback
HAL_I2C_MemTxCpltCallback
HAL_I2C_MspDeInit
HAL_I2C_MspInit
HAL_I2C_RegisterAddrCallback
HAL_I2C_RegisterCallback
HAL_I2C_Slave_Receive
HAL_I2C_Slave_Receive_DMA
HAL_I2C_Slave_Receive_IT
HAL_I2C_Slave_Seq_Receive_DMA
HAL_I2C_Slave_Seq_Receive_IT
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_I2C_Slave_Seq_Transmit_IT
HAL_I2C_Slave_Transmit
HAL_I2C_Slave_Transmit_DMA
HAL_I2C_Slave_Transmit_IT
HAL_I2C_SlaveRxCpltCallback
HAL_I2C_SlaveTxCpltCallback
HAL_I2C_UnRegisterAddrCallback
HAL_I2C_UnRegisterCallback
I2C_ConvertOtherXferOptions
I2C_Disable_IRQ
I2C_DMAAbort
I2C_DMAError
I2C_DMAMasterReceiveCplt
I2C_DMAMasterTransmitCplt
I2C_DMASlaveReceiveCplt
I2C_DMASlaveTransmitCplt
I2C_Enable_IRQ
I2C_Flush_TXDR
I2C_IsErrorOccurred
I2C_ITAddrCplt
I2C_ITError
I2C_ITListenCplt
I2C_ITMasterCplt
I2C_ITMasterSeqCplt
I2C_ITSlaveCplt
I2C_ITSlaveSeqCplt
I2C_Master_ISR_DMA
I2C_Master_ISR_IT
I2C_Mem_ISR_DMA
I2C_Mem_ISR_IT
I2C_RequestMemoryRead
I2C_RequestMemoryWrite
I2C_Slave_ISR_DMA
I2C_Slave_ISR_IT
I2C_TransferConfig
I2C_TreatErrorCallback
I2C_WaitOnFlagUntilTimeout
I2C_WaitOnRXNEFlagUntilTimeout
I2C_WaitOnSTOPFlagUntilTimeout
I2C_WaitOnTXISFlagUntilTimeout
stm32g4xx_hal_i2c.h
__HAL_I2C_DISABLE
__HAL_I2C_DISABLE_IT
__HAL_I2C_ENABLE
__HAL_I2C_ENABLE_IT
__HAL_I2C_GENERATE_NACK
__HAL_I2C_GET_FLAG
__HAL_I2C_GET_IT_SOURCE
__HAL_I2C_RESET_HANDLE_STATE
HAL_I2C_ERROR_AF
HAL_I2C_ERROR_ARLO
HAL_I2C_ERROR_BERR
HAL_I2C_ERROR_DMA
HAL_I2C_ERROR_DMA_PARAM
HAL_I2C_ERROR_INVALID_CALLBACK
HAL_I2C_ERROR_INVALID_PARAM
HAL_I2C_ERROR_NONE
HAL_I2C_ERROR_OVR
HAL_I2C_ERROR_SIZE
HAL_I2C_ERROR_TIMEOUT
I2C_ADDRESSINGMODE_10BIT
I2C_ADDRESSINGMODE_7BIT
I2C_AUTOEND_MODE
I2C_CHECK_FLAG
I2C_CHECK_IT_SOURCE
I2C_DIRECTION_RECEIVE
I2C_DIRECTION_TRANSMIT
I2C_DUALADDRESS_DISABLE
I2C_DUALADDRESS_ENABLE
I2C_FIRST_AND_LAST_FRAME
I2C_FIRST_AND_NEXT_FRAME
I2C_FIRST_FRAME
I2C_FLAG_ADDR
I2C_FLAG_AF
I2C_FLAG_ALERT
I2C_FLAG_ARLO
I2C_FLAG_BERR
I2C_FLAG_BUSY
I2C_FLAG_DIR
I2C_FLAG_MASK
I2C_FLAG_OVR
I2C_FLAG_PECERR
I2C_FLAG_RXNE
I2C_FLAG_STOPF
I2C_FLAG_TC
I2C_FLAG_TCR
I2C_FLAG_TIMEOUT
I2C_FLAG_TXE
I2C_FLAG_TXIS
I2C_GENERALCALL_DISABLE
I2C_GENERALCALL_ENABLE
I2C_GENERATE_START
I2C_GENERATE_START_READ
I2C_GENERATE_START_WRITE
I2C_GENERATE_STOP
I2C_GET_ADDR_MATCH
I2C_GET_DIR
I2C_GET_OWN_ADDRESS1
I2C_GET_OWN_ADDRESS2
I2C_GET_STOP_MODE
I2C_IT_ADDRI
I2C_IT_ERRI
I2C_IT_NACKI
I2C_IT_RXI
I2C_IT_STOPI
I2C_IT_TCI
I2C_IT_TXI
I2C_LAST_FRAME
I2C_LAST_FRAME_NO_STOP
I2C_MEM_ADD_LSB
I2C_MEM_ADD_MSB
I2C_MEMADD_SIZE_16BIT
I2C_MEMADD_SIZE_8BIT
I2C_NEXT_FRAME
I2C_NO_STARTSTOP
I2C_NOSTRETCH_DISABLE
I2C_NOSTRETCH_ENABLE
I2C_OA2_MASK01
I2C_OA2_MASK02
I2C_OA2_MASK03
I2C_OA2_MASK04
I2C_OA2_MASK05
I2C_OA2_MASK06
I2C_OA2_MASK07
I2C_OA2_NOMASK
I2C_OTHER_AND_LAST_FRAME
I2C_OTHER_FRAME
I2C_RELOAD_MODE
I2C_RESET_CR2
I2C_SOFTEND_MODE
IS_I2C_ADDRESSING_MODE
IS_I2C_DUAL_ADDRESS
IS_I2C_GENERAL_CALL
IS_I2C_MEMADD_SIZE
IS_I2C_NO_STRETCH
IS_I2C_OWN_ADDRESS1
IS_I2C_OWN_ADDRESS2
IS_I2C_OWN_ADDRESS2_MASK
IS_I2C_TRANSFER_OPTIONS_REQUEST
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST
IS_TRANSFER_MODE
IS_TRANSFER_REQUEST
I2C_HandleTypeDef
pI2C_AddrCallbackTypeDef
pI2C_CallbackTypeDef
HAL_I2C_CallbackIDTypeDef
HAL_I2C_ModeTypeDef
HAL_I2C_StateTypeDef
HAL_I2C_AbortCpltCallback
HAL_I2C_AddrCallback
HAL_I2C_DeInit
HAL_I2C_DisableListen_IT
HAL_I2C_EnableListen_IT
HAL_I2C_ER_IRQHandler
HAL_I2C_ErrorCallback
HAL_I2C_EV_IRQHandler
HAL_I2C_GetError
HAL_I2C_GetMode
HAL_I2C_GetState
HAL_I2C_Init
HAL_I2C_IsDeviceReady
HAL_I2C_ListenCpltCallback
HAL_I2C_Master_Abort_IT
HAL_I2C_Master_Receive
HAL_I2C_Master_Receive_DMA
HAL_I2C_Master_Receive_IT
HAL_I2C_Master_Seq_Receive_DMA
HAL_I2C_Master_Seq_Receive_IT
HAL_I2C_Master_Seq_Transmit_DMA
HAL_I2C_Master_Seq_Transmit_IT
HAL_I2C_Master_Transmit
HAL_I2C_Master_Transmit_DMA
HAL_I2C_Master_Transmit_IT
HAL_I2C_MasterRxCpltCallback
HAL_I2C_MasterTxCpltCallback
HAL_I2C_Mem_Read
HAL_I2C_Mem_Read_DMA
HAL_I2C_Mem_Read_IT
HAL_I2C_Mem_Write
HAL_I2C_Mem_Write_DMA
HAL_I2C_Mem_Write_IT
HAL_I2C_MemRxCpltCallback
HAL_I2C_MemTxCpltCallback
HAL_I2C_MspDeInit
HAL_I2C_MspInit
HAL_I2C_RegisterAddrCallback
HAL_I2C_RegisterCallback
HAL_I2C_Slave_Receive
HAL_I2C_Slave_Receive_DMA
HAL_I2C_Slave_Receive_IT
HAL_I2C_Slave_Seq_Receive_DMA
HAL_I2C_Slave_Seq_Receive_IT
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_I2C_Slave_Seq_Transmit_IT
HAL_I2C_Slave_Transmit
HAL_I2C_Slave_Transmit_DMA
HAL_I2C_Slave_Transmit_IT
HAL_I2C_SlaveRxCpltCallback
HAL_I2C_SlaveTxCpltCallback
HAL_I2C_UnRegisterAddrCallback
HAL_I2C_UnRegisterCallback
stm32g4xx_hal_i2c_ex.c
HAL_I2CEx_ConfigDigitalFilter
HAL_I2CEx_DisableFastModePlus
HAL_I2CEx_DisableWakeUp
HAL_I2CEx_EnableFastModePlus
HAL_I2CEx_EnableWakeUp
stm32g4xx_hal_i2c_ex.h
I2C_ANALOGFILTER_ENABLE
I2C_FASTMODEPLUS_I2C1
I2C_FASTMODEPLUS_I2C2
I2C_FASTMODEPLUS_I2C3
I2C_FASTMODEPLUS_I2C4
I2C_FASTMODEPLUS_PB6
I2C_FASTMODEPLUS_PB7
I2C_FASTMODEPLUS_PB8
I2C_FASTMODEPLUS_PB9
I2C_FMP_NOT_SUPPORTED
IS_I2C_ANALOG_FILTER
IS_I2C_DIGITAL_FILTER
IS_I2C_FASTMODEPLUS
HAL_I2CEx_ConfigAnalogFilter
HAL_I2CEx_ConfigDigitalFilter
HAL_I2CEx_DisableFastModePlus
HAL_I2CEx_DisableWakeUp
HAL_I2CEx_EnableFastModePlus
HAL_I2CEx_EnableWakeUp
stm32g4xx_hal_i2s.c
HAL_I2S_DeInit
HAL_I2S_DMAPause
HAL_I2S_DMAResume
HAL_I2S_DMAStop
HAL_I2S_ErrorCallback
HAL_I2S_GetError
HAL_I2S_GetState
HAL_I2S_Init
HAL_I2S_IRQHandler
HAL_I2S_MspDeInit
HAL_I2S_MspInit
HAL_I2S_Receive
HAL_I2S_Receive_DMA
HAL_I2S_Receive_IT
HAL_I2S_RegisterCallback
HAL_I2S_RxCpltCallback
HAL_I2S_RxHalfCpltCallback
HAL_I2S_Transmit
HAL_I2S_Transmit_DMA
HAL_I2S_Transmit_IT
HAL_I2S_TxCpltCallback
HAL_I2S_TxHalfCpltCallback
HAL_I2S_UnRegisterCallback
I2S_DMAError
I2S_DMARxCplt
I2S_DMARxHalfCplt
I2S_DMATxCplt
I2S_DMATxHalfCplt
I2S_Receive_IT
I2S_Transmit_IT
I2S_WaitFlagStateUntilTimeout
stm32g4xx_hal_i2s.h
__HAL_I2S_CLEAR_UDRFLAG
__HAL_I2S_DISABLE
__HAL_I2S_DISABLE_IT
__HAL_I2S_ENABLE
__HAL_I2S_ENABLE_IT
__HAL_I2S_FLUSH_RX_DR
__HAL_I2S_GET_FLAG
__HAL_I2S_GET_IT_SOURCE
__HAL_I2S_RESET_HANDLE_STATE
HAL_I2S_ERROR_BUSY_LINE_RX
HAL_I2S_ERROR_DMA
HAL_I2S_ERROR_INVALID_CALLBACK
HAL_I2S_ERROR_NONE
HAL_I2S_ERROR_OVR
HAL_I2S_ERROR_PRESCALER
HAL_I2S_ERROR_TIMEOUT
HAL_I2S_ERROR_UDR
I2S_AUDIOFREQ_11K
I2S_AUDIOFREQ_16K
I2S_AUDIOFREQ_192K
I2S_AUDIOFREQ_22K
I2S_AUDIOFREQ_32K
I2S_AUDIOFREQ_44K
I2S_AUDIOFREQ_48K
I2S_AUDIOFREQ_8K
I2S_AUDIOFREQ_96K
I2S_AUDIOFREQ_DEFAULT
I2S_CHECK_FLAG
I2S_CHECK_IT_SOURCE
I2S_CPOL_HIGH
I2S_CPOL_LOW
I2S_DATAFORMAT_16B
I2S_DATAFORMAT_16B_EXTENDED
I2S_DATAFORMAT_24B
I2S_DATAFORMAT_32B
I2S_FLAG_BSY
I2S_FLAG_CHSIDE
I2S_FLAG_FRE
I2S_FLAG_MASK
I2S_FLAG_OVR
I2S_FLAG_RXNE
I2S_FLAG_TXE
I2S_FLAG_UDR
I2S_IT_ERR
I2S_IT_RXNE
I2S_IT_TXE
I2S_MCLKOUTPUT_DISABLE
I2S_MCLKOUTPUT_ENABLE
I2S_MODE_MASTER_RX
I2S_MODE_MASTER_TX
I2S_MODE_SLAVE_RX
I2S_MODE_SLAVE_TX
I2S_STANDARD_LSB
I2S_STANDARD_MSB
I2S_STANDARD_PCM_LONG
I2S_STANDARD_PCM_SHORT
I2S_STANDARD_PHILIPS
IS_I2S_AUDIO_FREQ
IS_I2S_CPOL
IS_I2S_DATA_FORMAT
IS_I2S_MCLK_OUTPUT
IS_I2S_MODE
IS_I2S_STANDARD
I2S_HandleTypeDef
pI2S_CallbackTypeDef
HAL_I2S_CallbackIDTypeDef
HAL_I2S_StateTypeDef
HAL_I2S_DeInit
HAL_I2S_DMAPause
HAL_I2S_DMAResume
HAL_I2S_DMAStop
HAL_I2S_ErrorCallback
HAL_I2S_GetError
HAL_I2S_GetState
HAL_I2S_Init
HAL_I2S_IRQHandler
HAL_I2S_MspDeInit
HAL_I2S_MspInit
HAL_I2S_Receive
HAL_I2S_Receive_DMA
HAL_I2S_Receive_IT
HAL_I2S_RegisterCallback
HAL_I2S_RxCpltCallback
HAL_I2S_RxHalfCpltCallback
HAL_I2S_Transmit
HAL_I2S_Transmit_DMA
HAL_I2S_Transmit_IT
HAL_I2S_TxCpltCallback
HAL_I2S_TxHalfCpltCallback
HAL_I2S_UnRegisterCallback
stm32g4xx_hal_irda.c
IRDA_DIV_SAMPLING16
IRDA_TEACK_REACK_TIMEOUT
USART_BRR_MAX
USART_BRR_MIN
HAL_IRDA_Abort
HAL_IRDA_Abort_IT
HAL_IRDA_AbortCpltCallback
HAL_IRDA_AbortReceive
HAL_IRDA_AbortReceive_IT
HAL_IRDA_AbortReceiveCpltCallback
HAL_IRDA_AbortTransmit
HAL_IRDA_AbortTransmit_IT
HAL_IRDA_AbortTransmitCpltCallback
HAL_IRDA_DeInit
HAL_IRDA_DMAPause
HAL_IRDA_DMAResume
HAL_IRDA_DMAStop
HAL_IRDA_ErrorCallback
HAL_IRDA_GetError
HAL_IRDA_GetState
HAL_IRDA_Init
HAL_IRDA_IRQHandler
HAL_IRDA_MspDeInit
HAL_IRDA_MspInit
HAL_IRDA_Receive
HAL_IRDA_Receive_DMA
HAL_IRDA_Receive_IT
HAL_IRDA_RegisterCallback
HAL_IRDA_RxCpltCallback
HAL_IRDA_RxHalfCpltCallback
HAL_IRDA_Transmit
HAL_IRDA_Transmit_DMA
HAL_IRDA_Transmit_IT
HAL_IRDA_TxCpltCallback
HAL_IRDA_TxHalfCpltCallback
HAL_IRDA_UnRegisterCallback
IRDA_CheckIdleState
IRDA_DMAAbortOnError
IRDA_DMAError
IRDA_DMAReceiveCplt
IRDA_DMAReceiveHalfCplt
IRDA_DMARxAbortCallback
IRDA_DMARxOnlyAbortCallback
IRDA_DMATransmitCplt
IRDA_DMATransmitHalfCplt
IRDA_DMATxAbortCallback
IRDA_DMATxOnlyAbortCallback
IRDA_EndRxTransfer
IRDA_EndTransmit_IT
IRDA_EndTxTransfer
IRDA_InitCallbacksToDefault
IRDA_Receive_IT
IRDA_SetConfig
IRDA_Transmit_IT
IRDA_WaitOnFlagUntilTimeout
stm32g4xx_hal_irda.h
__HAL_IRDA_CLEAR_FLAG
__HAL_IRDA_CLEAR_IDLEFLAG
__HAL_IRDA_CLEAR_IT
__HAL_IRDA_CLEAR_NEFLAG
__HAL_IRDA_CLEAR_OREFLAG
__HAL_IRDA_CLEAR_PEFLAG
__HAL_IRDA_DISABLE
__HAL_IRDA_DISABLE_IT
__HAL_IRDA_ENABLE
__HAL_IRDA_ENABLE_IT
__HAL_IRDA_FLUSH_DRREGISTER
__HAL_IRDA_GET_FLAG
__HAL_IRDA_GET_IT
__HAL_IRDA_GET_IT_SOURCE
__HAL_IRDA_ONE_BIT_SAMPLE_DISABLE
__HAL_IRDA_ONE_BIT_SAMPLE_ENABLE
__HAL_IRDA_RESET_HANDLE_STATE
__HAL_IRDA_SEND_REQ
HAL_IRDA_ERROR_BUSY
HAL_IRDA_ERROR_DMA
HAL_IRDA_ERROR_FE
HAL_IRDA_ERROR_INVALID_CALLBACK
HAL_IRDA_ERROR_NE
HAL_IRDA_ERROR_NONE
HAL_IRDA_ERROR_ORE
HAL_IRDA_ERROR_PE
HAL_IRDA_STATE_BUSY
HAL_IRDA_STATE_BUSY_RX
HAL_IRDA_STATE_BUSY_TX
HAL_IRDA_STATE_BUSY_TX_RX
HAL_IRDA_STATE_ERROR
HAL_IRDA_STATE_READY
HAL_IRDA_STATE_RESET
HAL_IRDA_STATE_TIMEOUT
IRDA_AUTOBAUD_REQUEST
IRDA_CLEAR_FEF
IRDA_CLEAR_IDLEF
IRDA_CLEAR_NEF
IRDA_CLEAR_OREF
IRDA_CLEAR_PEF
IRDA_CLEAR_TCF
IRDA_CR_MASK
IRDA_CR_POS
IRDA_DMA_RX_DISABLE
IRDA_DMA_RX_ENABLE
IRDA_DMA_TX_DISABLE
IRDA_DMA_TX_ENABLE
IRDA_FLAG_ABRE
IRDA_FLAG_ABRF
IRDA_FLAG_BUSY
IRDA_FLAG_FE
IRDA_FLAG_NE
IRDA_FLAG_ORE
IRDA_FLAG_PE
IRDA_FLAG_REACK
IRDA_FLAG_RXNE
IRDA_FLAG_TC
IRDA_FLAG_TEACK
IRDA_FLAG_TXE
IRDA_ISR_MASK
IRDA_ISR_POS
IRDA_IT_ERR
IRDA_IT_FE
IRDA_IT_IDLE
IRDA_IT_MASK
IRDA_IT_NE
IRDA_IT_ORE
IRDA_IT_PE
IRDA_IT_RXNE
IRDA_IT_TC
IRDA_IT_TXE
IRDA_MODE_DISABLE
IRDA_MODE_ENABLE
IRDA_MODE_RX
IRDA_MODE_TX
IRDA_MODE_TX_RX
IRDA_ONE_BIT_SAMPLE_DISABLE
IRDA_ONE_BIT_SAMPLE_ENABLE
IRDA_PARITY_EVEN
IRDA_PARITY_NONE
IRDA_PARITY_ODD
IRDA_POWERMODE_LOWPOWER
IRDA_POWERMODE_NORMAL
IRDA_PRESCALER_DIV1
IRDA_PRESCALER_DIV10
IRDA_PRESCALER_DIV12
IRDA_PRESCALER_DIV128
IRDA_PRESCALER_DIV16
IRDA_PRESCALER_DIV2
IRDA_PRESCALER_DIV256
IRDA_PRESCALER_DIV32
IRDA_PRESCALER_DIV4
IRDA_PRESCALER_DIV6
IRDA_PRESCALER_DIV64
IRDA_PRESCALER_DIV8
IRDA_RXDATA_FLUSH_REQUEST
IRDA_STATE_DISABLE
IRDA_STATE_ENABLE
IRDA_TXDATA_FLUSH_REQUEST
IS_IRDA_BAUDRATE
IS_IRDA_CLOCKPRESCALER
IS_IRDA_DMA_RX
IS_IRDA_DMA_TX
IS_IRDA_MODE
IS_IRDA_ONE_BIT_SAMPLE
IS_IRDA_PARITY
IS_IRDA_POWERMODE
IS_IRDA_PRESCALER
IS_IRDA_REQUEST_PARAMETER
IS_IRDA_STATE
IS_IRDA_TX_RX_MODE
HAL_IRDA_StateTypeDef
IRDA_HandleTypeDef
pIRDA_CallbackTypeDef
HAL_IRDA_CallbackIDTypeDef
IRDA_ClockSourceTypeDef
HAL_IRDA_Abort
HAL_IRDA_Abort_IT
HAL_IRDA_AbortCpltCallback
HAL_IRDA_AbortReceive
HAL_IRDA_AbortReceive_IT
HAL_IRDA_AbortReceiveCpltCallback
HAL_IRDA_AbortTransmit
HAL_IRDA_AbortTransmit_IT
HAL_IRDA_AbortTransmitCpltCallback
HAL_IRDA_DeInit
HAL_IRDA_DMAPause
HAL_IRDA_DMAResume
HAL_IRDA_DMAStop
HAL_IRDA_ErrorCallback
HAL_IRDA_GetError
HAL_IRDA_GetState
HAL_IRDA_Init
HAL_IRDA_IRQHandler
HAL_IRDA_MspDeInit
HAL_IRDA_MspInit
HAL_IRDA_Receive
HAL_IRDA_Receive_DMA
HAL_IRDA_Receive_IT
HAL_IRDA_RegisterCallback
HAL_IRDA_RxCpltCallback
HAL_IRDA_RxHalfCpltCallback
HAL_IRDA_Transmit
HAL_IRDA_Transmit_DMA
HAL_IRDA_Transmit_IT
HAL_IRDA_TxCpltCallback
HAL_IRDA_TxHalfCpltCallback
HAL_IRDA_UnRegisterCallback
stm32g4xx_hal_irda_ex.h
IRDA_MASK_COMPUTATION
IRDA_WORDLENGTH_7B
IRDA_WORDLENGTH_8B
IRDA_WORDLENGTH_9B
IS_IRDA_WORD_LENGTH
stm32g4xx_hal_iwdg.c
IWDG_KERNEL_UPDATE_FLAGS
HAL_IWDG_Init
HAL_IWDG_Refresh
stm32g4xx_hal_iwdg.h
__HAL_IWDG_START
IS_IWDG_PRESCALER
IS_IWDG_RELOAD
IS_IWDG_WINDOW
IWDG_DISABLE_WRITE_ACCESS
IWDG_ENABLE_WRITE_ACCESS
IWDG_KEY_ENABLE
IWDG_KEY_RELOAD
IWDG_KEY_WRITE_ACCESS_DISABLE
IWDG_KEY_WRITE_ACCESS_ENABLE
IWDG_PRESCALER_128
IWDG_PRESCALER_16
IWDG_PRESCALER_256
IWDG_PRESCALER_32
IWDG_PRESCALER_4
IWDG_PRESCALER_64
IWDG_PRESCALER_8
IWDG_WINDOW_DISABLE
HAL_IWDG_Init
HAL_IWDG_Refresh
stm32g4xx_hal_lptim.c
HAL_LPTIM_AutoReloadMatchCallback
HAL_LPTIM_AutoReloadWriteCallback
HAL_LPTIM_CompareMatchCallback
HAL_LPTIM_CompareWriteCallback
HAL_LPTIM_Counter_Start
HAL_LPTIM_Counter_Start_IT
HAL_LPTIM_Counter_Stop
HAL_LPTIM_Counter_Stop_IT
HAL_LPTIM_DeInit
HAL_LPTIM_DirectionDownCallback
HAL_LPTIM_DirectionUpCallback
HAL_LPTIM_Encoder_Start
HAL_LPTIM_Encoder_Start_IT
HAL_LPTIM_Encoder_Stop
HAL_LPTIM_Encoder_Stop_IT
HAL_LPTIM_GetState
HAL_LPTIM_Init
HAL_LPTIM_IRQHandler
HAL_LPTIM_MspDeInit
HAL_LPTIM_MspInit
HAL_LPTIM_OnePulse_Start
HAL_LPTIM_OnePulse_Start_IT
HAL_LPTIM_OnePulse_Stop
HAL_LPTIM_OnePulse_Stop_IT
HAL_LPTIM_PWM_Start
HAL_LPTIM_PWM_Start_IT
HAL_LPTIM_PWM_Stop
HAL_LPTIM_PWM_Stop_IT
HAL_LPTIM_ReadAutoReload
HAL_LPTIM_ReadCompare
HAL_LPTIM_ReadCounter
HAL_LPTIM_RegisterCallback
HAL_LPTIM_SetOnce_Start
HAL_LPTIM_SetOnce_Start_IT
HAL_LPTIM_SetOnce_Stop
HAL_LPTIM_SetOnce_Stop_IT
HAL_LPTIM_TimeOut_Start
HAL_LPTIM_TimeOut_Start_IT
HAL_LPTIM_TimeOut_Stop
HAL_LPTIM_TimeOut_Stop_IT
HAL_LPTIM_TriggerCallback
HAL_LPTIM_UnRegisterCallback
LPTIM_Disable
LPTIM_ResetCallback
LPTIM_WaitForFlag
stm32g4xx_hal_lptim.h
__HAL_LPTIM_CLEAR_FLAG
__HAL_LPTIM_COMPARE_SET
__HAL_LPTIM_DISABLE
__HAL_LPTIM_DISABLE_IT
__HAL_LPTIM_ENABLE
__HAL_LPTIM_ENABLE_IT
__HAL_LPTIM_GET_FLAG
__HAL_LPTIM_GET_IT_SOURCE
__HAL_LPTIM_RESET_COUNTER
__HAL_LPTIM_RESET_COUNTER_AFTERREAD
__HAL_LPTIM_RESET_HANDLE_STATE
__HAL_LPTIM_START_CONTINUOUS
__HAL_LPTIM_START_SINGLE
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT
IS_LPTIM_CLOCK_POLARITY
IS_LPTIM_CLOCK_PRESCALER
IS_LPTIM_CLOCK_PRESCALERDIV1
IS_LPTIM_CLOCK_SAMPLE_TIME
IS_LPTIM_CLOCK_SOURCE
IS_LPTIM_COMPARE
IS_LPTIM_COUNTER_SOURCE
IS_LPTIM_EXT_TRG_POLARITY
IS_LPTIM_INPUT1_SOURCE
IS_LPTIM_INPUT2_SOURCE
IS_LPTIM_OUTPUT_POLARITY
IS_LPTIM_PERIOD
IS_LPTIM_PULSE
IS_LPTIM_TRG_SOURCE
IS_LPTIM_TRIG_SAMPLE_TIME
IS_LPTIM_UPDATE_MODE
LPTIM_ACTIVEEDGE_FALLING
LPTIM_ACTIVEEDGE_RISING
LPTIM_ACTIVEEDGE_RISING_FALLING
LPTIM_CLOCKPOLARITY_FALLING
LPTIM_CLOCKPOLARITY_RISING
LPTIM_CLOCKPOLARITY_RISING_FALLING
LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC
LPTIM_CLOCKSOURCE_ULPTIM
LPTIM_COUNTERSOURCE_EXTERNAL
LPTIM_COUNTERSOURCE_INTERNAL
LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT
LPTIM_FLAG_ARRM
LPTIM_FLAG_ARROK
LPTIM_FLAG_CMPM
LPTIM_FLAG_CMPOK
LPTIM_FLAG_DOWN
LPTIM_FLAG_EXTTRIG
LPTIM_FLAG_UP
LPTIM_INPUT1SOURCE_COMP1
LPTIM_INPUT1SOURCE_COMP3
LPTIM_INPUT1SOURCE_COMP5
LPTIM_INPUT1SOURCE_COMP7
LPTIM_INPUT1SOURCE_GPIO
LPTIM_INPUT2SOURCE_COMP2
LPTIM_INPUT2SOURCE_COMP4
LPTIM_INPUT2SOURCE_COMP6
LPTIM_INPUT2SOURCE_GPIO
LPTIM_IT_ARRM
LPTIM_IT_ARROK
LPTIM_IT_CMPM
LPTIM_IT_CMPOK
LPTIM_IT_DOWN
LPTIM_IT_EXTTRIG
LPTIM_IT_UP
LPTIM_OUTPUTPOLARITY_HIGH
LPTIM_OUTPUTPOLARITY_LOW
LPTIM_PRESCALER_DIV1
LPTIM_PRESCALER_DIV128
LPTIM_PRESCALER_DIV16
LPTIM_PRESCALER_DIV2
LPTIM_PRESCALER_DIV32
LPTIM_PRESCALER_DIV4
LPTIM_PRESCALER_DIV64
LPTIM_PRESCALER_DIV8
LPTIM_TRIGSAMPLETIME_2TRANSITIONS
LPTIM_TRIGSAMPLETIME_4TRANSITIONS
LPTIM_TRIGSAMPLETIME_8TRANSITIONS
LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
LPTIM_TRIGSOURCE_0
LPTIM_TRIGSOURCE_1
LPTIM_TRIGSOURCE_10
LPTIM_TRIGSOURCE_11
LPTIM_TRIGSOURCE_12
LPTIM_TRIGSOURCE_2
LPTIM_TRIGSOURCE_3
LPTIM_TRIGSOURCE_4
LPTIM_TRIGSOURCE_5
LPTIM_TRIGSOURCE_6
LPTIM_TRIGSOURCE_7
LPTIM_TRIGSOURCE_8
LPTIM_TRIGSOURCE_9
LPTIM_TRIGSOURCE_SOFTWARE
LPTIM_UPDATE_ENDOFPERIOD
LPTIM_UPDATE_IMMEDIATE
LPTIM_HandleTypeDef
pLPTIM_CallbackTypeDef
HAL_LPTIM_CallbackIDTypeDef
HAL_LPTIM_StateTypeDef
HAL_LPTIM_AutoReloadMatchCallback
HAL_LPTIM_AutoReloadWriteCallback
HAL_LPTIM_CompareMatchCallback
HAL_LPTIM_CompareWriteCallback
HAL_LPTIM_Counter_Start
HAL_LPTIM_Counter_Start_IT
HAL_LPTIM_Counter_Stop
HAL_LPTIM_Counter_Stop_IT
HAL_LPTIM_DeInit
HAL_LPTIM_DirectionDownCallback
HAL_LPTIM_DirectionUpCallback
HAL_LPTIM_Encoder_Start
HAL_LPTIM_Encoder_Start_IT
HAL_LPTIM_Encoder_Stop
HAL_LPTIM_Encoder_Stop_IT
HAL_LPTIM_GetState
HAL_LPTIM_Init
HAL_LPTIM_IRQHandler
HAL_LPTIM_MspDeInit
HAL_LPTIM_MspInit
HAL_LPTIM_OnePulse_Start
HAL_LPTIM_OnePulse_Start_IT
HAL_LPTIM_OnePulse_Stop
HAL_LPTIM_OnePulse_Stop_IT
HAL_LPTIM_PWM_Start
HAL_LPTIM_PWM_Start_IT
HAL_LPTIM_PWM_Stop
HAL_LPTIM_PWM_Stop_IT
HAL_LPTIM_ReadAutoReload
HAL_LPTIM_ReadCompare
HAL_LPTIM_ReadCounter
HAL_LPTIM_RegisterCallback
HAL_LPTIM_SetOnce_Start
HAL_LPTIM_SetOnce_Start_IT
HAL_LPTIM_SetOnce_Stop
HAL_LPTIM_SetOnce_Stop_IT
HAL_LPTIM_TimeOut_Start
HAL_LPTIM_TimeOut_Start_IT
HAL_LPTIM_TimeOut_Stop
HAL_LPTIM_TimeOut_Stop_IT
HAL_LPTIM_TriggerCallback
HAL_LPTIM_UnRegisterCallback
LPTIM_Disable
stm32g4xx_hal_nand.c
HAL_NAND_ConfigDevice
HAL_NAND_DeInit
HAL_NAND_ECC_Disable
HAL_NAND_ECC_Enable
HAL_NAND_Erase_Block
HAL_NAND_GetECC
HAL_NAND_GetState
HAL_NAND_Init
HAL_NAND_IRQHandler
HAL_NAND_ITCallback
HAL_NAND_MspDeInit
HAL_NAND_MspInit
HAL_NAND_Read_ID
HAL_NAND_Read_Page_16b
HAL_NAND_Read_Page_8b
HAL_NAND_Read_SpareArea_16b
HAL_NAND_Read_SpareArea_8b
HAL_NAND_Read_Status
HAL_NAND_RegisterCallback
HAL_NAND_Reset
HAL_NAND_UnRegisterCallback
HAL_NAND_Write_Page_16b
HAL_NAND_Write_Page_8b
HAL_NAND_Write_SpareArea_16b
HAL_NAND_Write_SpareArea_8b
stm32g4xx_hal_nand.h
stm32g4xx_hal_nor.c
NOR_AMD_FUJITSU_COMMAND_SET
NOR_AMD_FUJITSU_EXT_COMMAND_SET
NOR_CMD_ADDRESS_FIFTH
NOR_CMD_ADDRESS_FIRST
NOR_CMD_ADDRESS_FIRST_BYTE
NOR_CMD_ADDRESS_FIRST_CFI
NOR_CMD_ADDRESS_FIRST_CFI_BYTE
NOR_CMD_ADDRESS_FOURTH
NOR_CMD_ADDRESS_SECOND
NOR_CMD_ADDRESS_SECOND_BYTE
NOR_CMD_ADDRESS_SIXTH
NOR_CMD_ADDRESS_THIRD
NOR_CMD_ADDRESS_THIRD_BYTE
NOR_CMD_BLOCK_ERASE
NOR_CMD_BLOCK_UNLOCK
NOR_CMD_BUFFERED_PROGRAM
NOR_CMD_CLEAR_STATUS_REG
NOR_CMD_CONFIRM
NOR_CMD_DATA_AUTO_SELECT
NOR_CMD_DATA_BLOCK_ERASE
NOR_CMD_DATA_BUFFER_AND_PROG
NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
NOR_CMD_DATA_CFI
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
NOR_CMD_DATA_CHIP_ERASE
NOR_CMD_DATA_FIRST
NOR_CMD_DATA_PROGRAM
NOR_CMD_DATA_READ_RESET
NOR_CMD_DATA_SECOND
NOR_CMD_READ_ARRAY
NOR_CMD_READ_STATUS_REG
NOR_CMD_WORD_PROGRAM
NOR_INTEL_DATA_COMMAND_SET
NOR_INTEL_PERFORMANCE_COMMAND_SET
NOR_INTEL_SHARP_EXT_COMMAND_SET
NOR_INTEL_STANDARD_COMMAND_SET
NOR_MASK_STATUS_DQ4
NOR_MASK_STATUS_DQ5
NOR_MASK_STATUS_DQ6
NOR_MASK_STATUS_DQ7
NOR_MITSUBISHI_EXT_COMMAND_SET
NOR_MITSUBISHI_STANDARD_COMMAND_SET
NOR_PAGE_WRITE_COMMAND_SET
NOR_WINDBOND_STANDARD_COMMAND_SET
HAL_NOR_DeInit
HAL_NOR_Erase_Block
HAL_NOR_Erase_Chip
HAL_NOR_GetState
HAL_NOR_GetStatus
HAL_NOR_Init
HAL_NOR_MspDeInit
HAL_NOR_MspInit
HAL_NOR_MspWait
HAL_NOR_Program
HAL_NOR_ProgramBuffer
HAL_NOR_Read
HAL_NOR_Read_CFI
HAL_NOR_Read_ID
HAL_NOR_ReadBuffer
HAL_NOR_RegisterCallback
HAL_NOR_ReturnToReadMode
HAL_NOR_UnRegisterCallback
HAL_NOR_WriteOperation_Disable
HAL_NOR_WriteOperation_Enable
uwNORMemoryDataWidth
stm32g4xx_hal_nor.h
stm32g4xx_hal_opamp.c
OPAMP_CSR_RESET_VALUE
OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK
OPAMP_TCMR_UPDATE_PARAMETERS_INIT_MASK
HAL_OPAMP_DeInit
HAL_OPAMP_GetState
HAL_OPAMP_GetTrimOffset
HAL_OPAMP_Init
HAL_OPAMP_Lock
HAL_OPAMP_LockTimerMux
HAL_OPAMP_MspDeInit
HAL_OPAMP_MspInit
HAL_OPAMP_RegisterCallback
HAL_OPAMP_SelfCalibrate
HAL_OPAMP_Start
HAL_OPAMP_Stop
HAL_OPAMP_UnRegisterCallback
stm32g4xx_hal_opamp.h
IS_OPAMP_FACTORYTRIMMING
IS_OPAMP_FUNCTIONAL_NORMALMODE
IS_OPAMP_INPUT
IS_OPAMP_INVERTING_INPUT
IS_OPAMP_NONINVERTING_INPUT
IS_OPAMP_PGA_GAIN
IS_OPAMP_PGACONNECT
IS_OPAMP_POWERMODE
IS_OPAMP_SEC_INVERTING_INPUT
IS_OPAMP_SEC_NONINVERTING_INPUT
IS_OPAMP_TIMERCONTROLLED_MUXMODE
IS_OPAMP_TRIMMING
IS_OPAMP_TRIMMINGVALUE
IS_OPAMP_VREF
OPAMP_FACTORYTRIMMING_DUMMY
OPAMP_FACTORYTRIMMING_N
OPAMP_FACTORYTRIMMING_P
OPAMP_FOLLOWER_MODE
OPAMP_INPUT_INVERTING
OPAMP_INPUT_NONINVERTING
OPAMP_INVERTINGINPUT_IO0
OPAMP_INVERTINGINPUT_IO1
OPAMP_NONINVERTINGINPUT_DAC
OPAMP_NONINVERTINGINPUT_IO0
OPAMP_NONINVERTINGINPUT_IO1
OPAMP_NONINVERTINGINPUT_IO2
OPAMP_NONINVERTINGINPUT_IO3
OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS
OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS
OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
OPAMP_PGA_GAIN_16_OR_MINUS_15
OPAMP_PGA_GAIN_2_OR_MINUS_1
OPAMP_PGA_GAIN_32_OR_MINUS_31
OPAMP_PGA_GAIN_4_OR_MINUS_3
OPAMP_PGA_GAIN_64_OR_MINUS_63
OPAMP_PGA_GAIN_8_OR_MINUS_7
OPAMP_PGA_MODE
OPAMP_POWERMODE_HIGHSPEED
OPAMP_POWERMODE_NORMALSPEED
OPAMP_SEC_INVERTINGINPUT_FOLLOWER
OPAMP_SEC_INVERTINGINPUT_IO0
OPAMP_SEC_INVERTINGINPUT_IO1
OPAMP_SEC_INVERTINGINPUT_PGA
OPAMP_SEC_NONINVERTINGINPUT_DAC
OPAMP_SEC_NONINVERTINGINPUT_IO0
OPAMP_SEC_NONINVERTINGINPUT_IO1
OPAMP_SEC_NONINVERTINGINPUT_IO2
OPAMP_SEC_NONINVERTINGINPUT_IO3
OPAMP_STANDALONE_MODE
OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE
OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6
OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6
OPAMP_TRIMMING_FACTORY
OPAMP_TRIMMING_USER
OPAMP_VREF_10VDDA
OPAMP_VREF_3VDDA
OPAMP_VREF_50VDDA
OPAMP_VREF_90VDDA
OPAMP_HandleTypeDef
OPAMP_TrimmingValueTypeDef
pOPAMP_CallbackTypeDef
HAL_OPAMP_CallbackIDTypeDef
HAL_OPAMP_StateTypeDef
HAL_OPAMP_DeInit
HAL_OPAMP_GetState
HAL_OPAMP_GetTrimOffset
HAL_OPAMP_Init
HAL_OPAMP_Lock
HAL_OPAMP_LockTimerMux
HAL_OPAMP_MspDeInit
HAL_OPAMP_MspInit
HAL_OPAMP_RegisterCallback
HAL_OPAMP_SelfCalibrate
HAL_OPAMP_Start
HAL_OPAMP_Stop
HAL_OPAMP_UnRegisterCallback
stm32g4xx_hal_opamp_ex.c
HAL_OPAMPEx_SelfCalibrateAll
hopamp2
stm32g4xx_hal_opamp_ex.h
stm32g4xx_hal_pcd.c
PCD_MIN
HAL_PCD_ActivateRemoteWakeup
HAL_PCD_ConnectCallback
HAL_PCD_DataInStageCallback
HAL_PCD_DataOutStageCallback
HAL_PCD_DeActivateRemoteWakeup
HAL_PCD_DeInit
HAL_PCD_DevConnect
HAL_PCD_DevDisconnect
HAL_PCD_DisconnectCallback
HAL_PCD_EP_Abort
HAL_PCD_EP_Close
HAL_PCD_EP_ClrStall
HAL_PCD_EP_DB_Receive
HAL_PCD_EP_DB_Transmit
HAL_PCD_EP_Flush
HAL_PCD_EP_GetRxCount
HAL_PCD_EP_Open
HAL_PCD_EP_Receive
HAL_PCD_EP_SetStall
HAL_PCD_EP_Transmit
HAL_PCD_GetState
HAL_PCD_Init
HAL_PCD_IRQHandler
HAL_PCD_ISOINIncompleteCallback
HAL_PCD_ISOOUTIncompleteCallback
HAL_PCD_MspDeInit
HAL_PCD_MspInit
HAL_PCD_RegisterBcdCallback
HAL_PCD_RegisterCallback
HAL_PCD_RegisterDataInStageCallback
HAL_PCD_RegisterDataOutStageCallback
HAL_PCD_RegisterIsoInIncpltCallback
HAL_PCD_RegisterIsoOutIncpltCallback
HAL_PCD_RegisterLpmCallback
HAL_PCD_ResetCallback
HAL_PCD_ResumeCallback
HAL_PCD_SetAddress
HAL_PCD_SetupStageCallback
HAL_PCD_SOFCallback
HAL_PCD_Start
HAL_PCD_Stop
HAL_PCD_SuspendCallback
HAL_PCD_UnRegisterBcdCallback
HAL_PCD_UnRegisterCallback
HAL_PCD_UnRegisterDataInStageCallback
HAL_PCD_UnRegisterDataOutStageCallback
HAL_PCD_UnRegisterIsoInIncpltCallback
HAL_PCD_UnRegisterIsoOutIncpltCallback
HAL_PCD_UnRegisterLpmCallback
PCD_EP_ISR_Handler
stm32g4xx_hal_pcd.h
__HAL_PCD_DISABLE
__HAL_PCD_ENABLE
__HAL_PCD_GET_FLAG
__HAL_USB_WAKEUP_EXTI_DISABLE_IT
__HAL_USB_WAKEUP_EXTI_ENABLE_IT
HAL_PCD_ERROR_INVALID_CALLBACK
PCD_CALC_BLK2
PCD_CALC_BLK32
PCD_CLEAR_BULK_EP_DBUF
PCD_CLEAR_EP_KIND
PCD_CLEAR_OUT_STATUS
PCD_CLEAR_RX_DTOG
PCD_CLEAR_RX_EP_CTR
PCD_CLEAR_TX_DTOG
PCD_CLEAR_TX_EP_CTR
PCD_DBL_BUF
PCD_ENDP0
PCD_ENDP1
PCD_ENDP2
PCD_ENDP3
PCD_ENDP4
PCD_ENDP5
PCD_ENDP6
PCD_ENDP7
PCD_EP0MPS_08
PCD_EP0MPS_16
PCD_EP0MPS_32
PCD_EP0MPS_64
PCD_EP_RX_CNT
PCD_EP_TX_CNT
PCD_FREE_USER_BUFFER
PCD_GET_ENDPOINT
PCD_GET_EP_ADDRESS
PCD_GET_EP_DBUF0_ADDR
PCD_GET_EP_DBUF0_CNT
PCD_GET_EP_DBUF1_ADDR
PCD_GET_EP_DBUF1_CNT
PCD_GET_EP_RX_ADDRESS
PCD_GET_EP_RX_CNT
PCD_GET_EP_RX_STALL_STATUS
PCD_GET_EP_RX_STATUS
PCD_GET_EP_TX_ADDRESS
PCD_GET_EP_TX_CNT
PCD_GET_EP_TX_STALL_STATUS
PCD_GET_EP_TX_STATUS
PCD_GET_EPTYPE
PCD_HS_PHY_EMBEDDED
PCD_PHY_EMBEDDED
PCD_PHY_ULPI
PCD_PHY_UTMI
PCD_RX_DTOG
PCD_SET_BULK_EP_DBUF
PCD_SET_ENDPOINT
PCD_SET_EP_ADDRESS
PCD_SET_EP_CNT_RX_REG
PCD_SET_EP_DBUF0_ADDR
PCD_SET_EP_DBUF0_CNT
PCD_SET_EP_DBUF1_ADDR
PCD_SET_EP_DBUF1_CNT
PCD_SET_EP_DBUF_ADDR
PCD_SET_EP_DBUF_CNT
PCD_SET_EP_KIND
PCD_SET_EP_RX_ADDRESS
PCD_SET_EP_RX_CNT
PCD_SET_EP_RX_DBUF0_CNT
PCD_SET_EP_RX_STATUS
PCD_SET_EP_RX_VALID
PCD_SET_EP_TX_ADDRESS
PCD_SET_EP_TX_CNT
PCD_SET_EP_TX_STATUS
PCD_SET_EP_TX_VALID
PCD_SET_EP_TXRX_STATUS
PCD_SET_EPTYPE
PCD_SET_OUT_STATUS
PCD_SNG_BUF
PCD_SPEED_FULL
PCD_TX_DTOG
USB_CNTRX_BLSIZE
USB_CNTRX_NBLK_MSK
USB_WAKEUP_EXTI_LINE
PCD_EPTypeDef
PCD_HandleTypeDef
PCD_InitTypeDef
PCD_TypeDef
pPCD_BcdCallbackTypeDef
pPCD_CallbackTypeDef
pPCD_DataInStageCallbackTypeDef
pPCD_DataOutStageCallbackTypeDef
pPCD_IsoInIncpltCallbackTypeDef
pPCD_IsoOutIncpltCallbackTypeDef
pPCD_LpmCallbackTypeDef
HAL_PCD_CallbackIDTypeDef
PCD_BCD_MsgTypeDef
PCD_LPM_MsgTypeDef
PCD_LPM_StateTypeDef
PCD_StateTypeDef
HAL_PCD_ActivateRemoteWakeup
HAL_PCD_ConnectCallback
HAL_PCD_DataInStageCallback
HAL_PCD_DataOutStageCallback
HAL_PCD_DeActivateRemoteWakeup
HAL_PCD_DeInit
HAL_PCD_DevConnect
HAL_PCD_DevDisconnect
HAL_PCD_DisconnectCallback
HAL_PCD_EP_Abort
HAL_PCD_EP_Close
HAL_PCD_EP_ClrStall
HAL_PCD_EP_Flush
HAL_PCD_EP_GetRxCount
HAL_PCD_EP_Open
HAL_PCD_EP_Receive
HAL_PCD_EP_SetStall
HAL_PCD_EP_Transmit
HAL_PCD_GetState
HAL_PCD_Init
HAL_PCD_IRQHandler
HAL_PCD_ISOINIncompleteCallback
HAL_PCD_ISOOUTIncompleteCallback
HAL_PCD_MspDeInit
HAL_PCD_MspInit
HAL_PCD_RegisterBcdCallback
HAL_PCD_RegisterCallback
HAL_PCD_RegisterDataInStageCallback
HAL_PCD_RegisterDataOutStageCallback
HAL_PCD_RegisterIsoInIncpltCallback
HAL_PCD_RegisterIsoOutIncpltCallback
HAL_PCD_RegisterLpmCallback
HAL_PCD_ResetCallback
HAL_PCD_ResumeCallback
HAL_PCD_SetAddress
HAL_PCD_SetupStageCallback
HAL_PCD_SOFCallback
HAL_PCD_Start
HAL_PCD_Stop
HAL_PCD_SuspendCallback
HAL_PCD_UnRegisterBcdCallback
HAL_PCD_UnRegisterCallback
HAL_PCD_UnRegisterDataInStageCallback
HAL_PCD_UnRegisterDataOutStageCallback
HAL_PCD_UnRegisterIsoInIncpltCallback
HAL_PCD_UnRegisterIsoOutIncpltCallback
HAL_PCD_UnRegisterLpmCallback
stm32g4xx_hal_pcd_ex.c
HAL_PCDEx_ActivateLPM
HAL_PCDEx_BCD_Callback
HAL_PCDEx_BCD_VBUSDetect
HAL_PCDEx_DeActivateBCD
HAL_PCDEx_DeActivateLPM
HAL_PCDEx_LPM_Callback
HAL_PCDEx_PMAConfig
stm32g4xx_hal_pcd_ex.h
HAL_PCDEx_ActivateLPM
HAL_PCDEx_BCD_Callback
HAL_PCDEx_BCD_VBUSDetect
HAL_PCDEx_DeActivateBCD
HAL_PCDEx_DeActivateLPM
HAL_PCDEx_LPM_Callback
HAL_PCDEx_PMAConfig
stm32g4xx_hal_pwr.c
PVD_MODE_EVT
PVD_MODE_IT
PVD_RISING_EDGE
HAL_PWR_ConfigPVD
HAL_PWR_DeInit
HAL_PWR_DisableBkUpAccess
HAL_PWR_DisablePVD
HAL_PWR_DisableSEVOnPend
HAL_PWR_DisableSleepOnExit
HAL_PWR_DisableWakeUpPin
HAL_PWR_EnableBkUpAccess
HAL_PWR_EnablePVD
HAL_PWR_EnableSEVOnPend
HAL_PWR_EnableSleepOnExit
HAL_PWR_EnableWakeUpPin
HAL_PWR_EnterSLEEPMode
HAL_PWR_EnterSTANDBYMode
HAL_PWR_EnterSTOPMode
HAL_PWR_PVDCallback
stm32g4xx_hal_pwr.h
__HAL_PWR_GET_FLAG
__HAL_PWR_PVD_EXTI_CLEAR_FLAG
__HAL_PWR_PVD_EXTI_DISABLE_EVENT
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVD_EXTI_DISABLE_IT
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_EVENT
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_IT
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVD_EXTI_GENERATE_SWIT
__HAL_PWR_PVD_EXTI_GET_FLAG
IS_PWR_PVD_LEVEL
IS_PWR_PVD_MODE
IS_PWR_REGULATOR
IS_PWR_SLEEP_ENTRY
IS_PWR_STOP_ENTRY
PWR_EVENT_LINE_PVD
PWR_EXTI_LINE_PVD
PWR_LOWPOWERREGULATOR_ON
PWR_MAINREGULATOR_ON
PWR_PVD_MODE_EVENT_FALLING
PWR_PVD_MODE_EVENT_RISING
PWR_PVD_MODE_EVENT_RISING_FALLING
PWR_PVD_MODE_IT_FALLING
PWR_PVD_MODE_IT_RISING
PWR_PVD_MODE_IT_RISING_FALLING
PWR_PVD_MODE_NORMAL
PWR_PVDLEVEL_0
PWR_PVDLEVEL_1
PWR_PVDLEVEL_2
PWR_PVDLEVEL_3
PWR_PVDLEVEL_4
PWR_PVDLEVEL_5
PWR_PVDLEVEL_6
PWR_PVDLEVEL_7
PWR_SLEEPENTRY_WFE
PWR_SLEEPENTRY_WFI
PWR_STOPENTRY_WFE
PWR_STOPENTRY_WFI
HAL_PWR_ConfigPVD
HAL_PWR_DeInit
HAL_PWR_DisableBkUpAccess
HAL_PWR_DisablePVD
HAL_PWR_DisableSEVOnPend
HAL_PWR_DisableSleepOnExit
HAL_PWR_DisableWakeUpPin
HAL_PWR_EnableBkUpAccess
HAL_PWR_EnablePVD
HAL_PWR_EnableSEVOnPend
HAL_PWR_EnableSleepOnExit
HAL_PWR_EnableWakeUpPin
HAL_PWR_EnterSLEEPMode
HAL_PWR_EnterSTANDBYMode
HAL_PWR_EnterSTOPMode
HAL_PWR_PVDCallback
stm32g4xx_hal_pwr_ex.c
PVM_MODE_EVT
PVM_MODE_IT
PVM_RISING_EDGE
PWR_FLAG_SETTING_DELAY_US
PWR_PORTF_AVAILABLE_PINS
PWR_PORTG_AVAILABLE_PINS
HAL_PWREx_ConfigPVM
HAL_PWREx_ControlVoltageScaling
HAL_PWREx_DisableBatteryCharging
HAL_PWREx_DisableGPIOPullDown
HAL_PWREx_DisableGPIOPullUp
HAL_PWREx_DisableInternalWakeUpLine
HAL_PWREx_DisableLowPowerRunMode
HAL_PWREx_DisablePullUpPullDownConfig
HAL_PWREx_DisablePVM1
HAL_PWREx_DisablePVM2
HAL_PWREx_DisablePVM3
HAL_PWREx_DisablePVM4
HAL_PWREx_DisableSRAM2ContentRetention
HAL_PWREx_DisableUCPDDeadBattery
HAL_PWREx_DisableUCPDStandbyMode
HAL_PWREx_EnableBatteryCharging
HAL_PWREx_EnableGPIOPullDown
HAL_PWREx_EnableGPIOPullUp
HAL_PWREx_EnableInternalWakeUpLine
HAL_PWREx_EnableLowPowerRunMode
HAL_PWREx_EnablePullUpPullDownConfig
HAL_PWREx_EnablePVM1
HAL_PWREx_EnablePVM2
HAL_PWREx_EnablePVM3
HAL_PWREx_EnablePVM4
HAL_PWREx_EnableSRAM2ContentRetention
HAL_PWREx_EnableUCPDDeadBattery
HAL_PWREx_EnableUCPDStandbyMode
HAL_PWREx_EnterSHUTDOWNMode
HAL_PWREx_EnterSTOP0Mode
HAL_PWREx_EnterSTOP1Mode
HAL_PWREx_GetVoltageRange
HAL_PWREx_PVD_PVM_IRQHandler
HAL_PWREx_PVM1Callback
HAL_PWREx_PVM2Callback
HAL_PWREx_PVM3Callback
HAL_PWREx_PVM4Callback
stm32g4xx_hal_pwr_ex.h
__HAL_PWR_PVM1_EXTI_DISABLE_EVENT
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_DISABLE_IT
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_EVENT
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_IT
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM1_EXTI_GENERATE_SWIT
__HAL_PWR_PVM1_EXTI_GET_FLAG
__HAL_PWR_PVM2_EXTI_CLEAR_FLAG
__HAL_PWR_PVM2_EXTI_DISABLE_EVENT
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_DISABLE_IT
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_EVENT
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_IT
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM2_EXTI_GENERATE_SWIT
__HAL_PWR_PVM2_EXTI_GET_FLAG
__HAL_PWR_PVM3_EXTI_CLEAR_FLAG
__HAL_PWR_PVM3_EXTI_DISABLE_EVENT
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_DISABLE_IT
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_EVENT
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_IT
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM3_EXTI_GENERATE_SWIT
__HAL_PWR_PVM3_EXTI_GET_FLAG
__HAL_PWR_PVM4_EXTI_CLEAR_FLAG
__HAL_PWR_PVM4_EXTI_DISABLE_EVENT
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_DISABLE_IT
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_EVENT
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_IT
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_PWR_PVM4_EXTI_GENERATE_SWIT
__HAL_PWR_PVM4_EXTI_GET_FLAG
__HAL_PWR_VOLTAGESCALING_CONFIG
IS_PWR_BATTERY_CHARGING
IS_PWR_BATTERY_RESISTOR_SELECT
IS_PWR_GPIO
IS_PWR_GPIO_BIT_NUMBER
IS_PWR_PVM_MODE
IS_PWR_PVM_TYPE
IS_PWR_VOLTAGE_SCALING_RANGE
IS_PWR_WAKEUP_PIN
PWR_BATTERY_CHARGING_DISABLE
PWR_BATTERY_CHARGING_ENABLE
PWR_BATTERY_CHARGING_RESISTOR_1_5
PWR_BATTERY_CHARGING_RESISTOR_5
PWR_EVENT_LINE_PVM1
PWR_EVENT_LINE_PVM2
PWR_EVENT_LINE_PVM3
PWR_EVENT_LINE_PVM4
PWR_EXTI_LINE_PVM1
PWR_EXTI_LINE_PVM2
PWR_EXTI_LINE_PVM3
PWR_EXTI_LINE_PVM4
PWR_FLAG_PVDO
PWR_FLAG_PVMO1
PWR_FLAG_PVMO2
PWR_FLAG_PVMO3
PWR_FLAG_PVMO4
PWR_FLAG_REGLPF
PWR_FLAG_REGLPS
PWR_FLAG_SB
PWR_FLAG_VOSF
PWR_FLAG_WU
PWR_FLAG_WUF1
PWR_FLAG_WUF2
PWR_FLAG_WUF3
PWR_FLAG_WUF4
PWR_FLAG_WUF5
PWR_FLAG_WUFI
PWR_GPIO_A
PWR_GPIO_B
PWR_GPIO_BIT_0
PWR_GPIO_BIT_1
PWR_GPIO_BIT_10
PWR_GPIO_BIT_11
PWR_GPIO_BIT_12
PWR_GPIO_BIT_13
PWR_GPIO_BIT_14
PWR_GPIO_BIT_15
PWR_GPIO_BIT_2
PWR_GPIO_BIT_3
PWR_GPIO_BIT_4
PWR_GPIO_BIT_5
PWR_GPIO_BIT_6
PWR_GPIO_BIT_7
PWR_GPIO_BIT_8
PWR_GPIO_BIT_9
PWR_GPIO_C
PWR_GPIO_D
PWR_GPIO_E
PWR_GPIO_F
PWR_GPIO_G
PWR_PVM_1
PWR_PVM_2
PWR_PVM_3
PWR_PVM_4
PWR_PVM_MODE_EVENT_FALLING
PWR_PVM_MODE_EVENT_RISING
PWR_PVM_MODE_EVENT_RISING_FALLING
PWR_PVM_MODE_IT_FALLING
PWR_PVM_MODE_IT_RISING
PWR_PVM_MODE_IT_RISING_FALLING
PWR_PVM_MODE_NORMAL
PWR_REGULATOR_VOLTAGE_SCALE1
PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
PWR_REGULATOR_VOLTAGE_SCALE2
PWR_WAKEUP_PIN1
PWR_WAKEUP_PIN1_HIGH
PWR_WAKEUP_PIN1_LOW
PWR_WAKEUP_PIN2
PWR_WAKEUP_PIN2_HIGH
PWR_WAKEUP_PIN2_LOW
PWR_WAKEUP_PIN3
PWR_WAKEUP_PIN3_HIGH
PWR_WAKEUP_PIN3_LOW
PWR_WAKEUP_PIN4
PWR_WAKEUP_PIN4_HIGH
PWR_WAKEUP_PIN4_LOW
PWR_WAKEUP_PIN5
PWR_WAKEUP_PIN5_HIGH
PWR_WAKEUP_PIN5_LOW
PWR_WUP_POLARITY_SHIFT
HAL_PWREx_ConfigPVM
HAL_PWREx_ControlVoltageScaling
HAL_PWREx_DisableBatteryCharging
HAL_PWREx_DisableGPIOPullDown
HAL_PWREx_DisableGPIOPullUp
HAL_PWREx_DisableInternalWakeUpLine
HAL_PWREx_DisableLowPowerRunMode
HAL_PWREx_DisablePullUpPullDownConfig
HAL_PWREx_DisablePVM1
HAL_PWREx_DisablePVM2
HAL_PWREx_DisablePVM3
HAL_PWREx_DisablePVM4
HAL_PWREx_DisableSRAM2ContentRetention
HAL_PWREx_DisableUCPDDeadBattery
HAL_PWREx_DisableUCPDStandbyMode
HAL_PWREx_EnableBatteryCharging
HAL_PWREx_EnableGPIOPullDown
HAL_PWREx_EnableGPIOPullUp
HAL_PWREx_EnableInternalWakeUpLine
HAL_PWREx_EnableLowPowerRunMode
HAL_PWREx_EnablePullUpPullDownConfig
HAL_PWREx_EnablePVM1
HAL_PWREx_EnablePVM2
HAL_PWREx_EnablePVM3
HAL_PWREx_EnablePVM4
HAL_PWREx_EnableSRAM2ContentRetention
HAL_PWREx_EnableUCPDDeadBattery
HAL_PWREx_EnableUCPDStandbyMode
HAL_PWREx_EnterSHUTDOWNMode
HAL_PWREx_EnterSTOP0Mode
HAL_PWREx_EnterSTOP1Mode
HAL_PWREx_GetVoltageRange
HAL_PWREx_PVD_PVM_IRQHandler
HAL_PWREx_PVM1Callback
HAL_PWREx_PVM2Callback
HAL_PWREx_PVM3Callback
HAL_PWREx_PVM4Callback
stm32g4xx_hal_qspi.c
QSPI_FUNCTIONAL_MODE_AUTO_POLLING
QSPI_FUNCTIONAL_MODE_INDIRECT_READ
QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE
QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED
HAL_QSPI_Abort
HAL_QSPI_Abort_IT
HAL_QSPI_AbortCpltCallback
HAL_QSPI_AutoPolling
HAL_QSPI_AutoPolling_IT
HAL_QSPI_CmdCpltCallback
HAL_QSPI_Command
HAL_QSPI_Command_IT
HAL_QSPI_DeInit
HAL_QSPI_ErrorCallback
HAL_QSPI_FifoThresholdCallback
HAL_QSPI_GetError
HAL_QSPI_GetFifoThreshold
HAL_QSPI_GetState
HAL_QSPI_Init
HAL_QSPI_IRQHandler
HAL_QSPI_MemoryMapped
HAL_QSPI_MspDeInit
HAL_QSPI_MspInit
HAL_QSPI_Receive
HAL_QSPI_Receive_DMA
HAL_QSPI_Receive_IT
HAL_QSPI_RegisterCallback
HAL_QSPI_RxCpltCallback
HAL_QSPI_RxHalfCpltCallback
HAL_QSPI_SetFifoThreshold
HAL_QSPI_SetFlashID
HAL_QSPI_SetTimeout
HAL_QSPI_StatusMatchCallback
HAL_QSPI_TimeOutCallback
HAL_QSPI_Transmit
HAL_QSPI_Transmit_DMA
HAL_QSPI_Transmit_IT
HAL_QSPI_TxCpltCallback
HAL_QSPI_TxHalfCpltCallback
HAL_QSPI_UnRegisterCallback
QSPI_Config
QSPI_DMAAbortCplt
QSPI_DMAError
QSPI_DMARxCplt
QSPI_DMARxHalfCplt
QSPI_DMATxCplt
QSPI_DMATxHalfCplt
QSPI_WaitFlagStateUntilTimeout
stm32g4xx_hal_qspi.h
__HAL_QSPI_DISABLE
__HAL_QSPI_DISABLE_IT
__HAL_QSPI_ENABLE
__HAL_QSPI_ENABLE_IT
__HAL_QSPI_GET_FLAG
__HAL_QSPI_GET_IT_SOURCE
__HAL_QSPI_RESET_HANDLE_STATE
HAL_QSPI_ERROR_DMA
HAL_QSPI_ERROR_INVALID_CALLBACK
HAL_QSPI_ERROR_INVALID_PARAM
HAL_QSPI_ERROR_NONE
HAL_QSPI_ERROR_TIMEOUT
HAL_QSPI_ERROR_TRANSFER
HAL_QSPI_TIMEOUT_DEFAULT_VALUE
IS_QSPI_ADDRESS_MODE
IS_QSPI_ADDRESS_SIZE
IS_QSPI_ALTERNATE_BYTES_MODE
IS_QSPI_ALTERNATE_BYTES_SIZE
IS_QSPI_AUTOMATIC_STOP
IS_QSPI_CLOCK_MODE
IS_QSPI_CLOCK_PRESCALER
IS_QSPI_CS_HIGH_TIME
IS_QSPI_DATA_MODE
IS_QSPI_DDR_HHC
IS_QSPI_DDR_MODE
IS_QSPI_DUAL_FLASH_MODE
IS_QSPI_DUMMY_CYCLES
IS_QSPI_FIFO_THRESHOLD
IS_QSPI_FLASH_ID
IS_QSPI_FLASH_SIZE
IS_QSPI_INSTRUCTION
IS_QSPI_INSTRUCTION_MODE
IS_QSPI_INTERVAL
IS_QSPI_MATCH_MODE
IS_QSPI_SIOO_MODE
IS_QSPI_SSHIFT
IS_QSPI_STATUS_BYTES_SIZE
IS_QSPI_TIMEOUT_ACTIVATION
IS_QSPI_TIMEOUT_PERIOD
QSPI_ADDRESS_16_BITS
QSPI_ADDRESS_1_LINE
QSPI_ADDRESS_24_BITS
QSPI_ADDRESS_2_LINES
QSPI_ADDRESS_32_BITS
QSPI_ADDRESS_4_LINES
QSPI_ADDRESS_8_BITS
QSPI_ADDRESS_NONE
QSPI_ALTERNATE_BYTES_16_BITS
QSPI_ALTERNATE_BYTES_1_LINE
QSPI_ALTERNATE_BYTES_24_BITS
QSPI_ALTERNATE_BYTES_2_LINES
QSPI_ALTERNATE_BYTES_32_BITS
QSPI_ALTERNATE_BYTES_4_LINES
QSPI_ALTERNATE_BYTES_8_BITS
QSPI_ALTERNATE_BYTES_NONE
QSPI_AUTOMATIC_STOP_DISABLE
QSPI_AUTOMATIC_STOP_ENABLE
QSPI_CLOCK_MODE_0
QSPI_CLOCK_MODE_3
QSPI_CS_HIGH_TIME_1_CYCLE
QSPI_CS_HIGH_TIME_2_CYCLE
QSPI_CS_HIGH_TIME_3_CYCLE
QSPI_CS_HIGH_TIME_4_CYCLE
QSPI_CS_HIGH_TIME_5_CYCLE
QSPI_CS_HIGH_TIME_6_CYCLE
QSPI_CS_HIGH_TIME_7_CYCLE
QSPI_CS_HIGH_TIME_8_CYCLE
QSPI_DATA_1_LINE
QSPI_DATA_2_LINES
QSPI_DATA_4_LINES
QSPI_DATA_NONE
QSPI_DDR_HHC_ANALOG_DELAY
QSPI_DDR_HHC_HALF_CLK_DELAY
QSPI_DDR_MODE_DISABLE
QSPI_DDR_MODE_ENABLE
QSPI_DUALFLASH_DISABLE
QSPI_DUALFLASH_ENABLE
QSPI_FLAG_BUSY
QSPI_FLAG_FT
QSPI_FLAG_SM
QSPI_FLAG_TC
QSPI_FLAG_TE
QSPI_FLAG_TO
QSPI_FLASH_ID_1
QSPI_FLASH_ID_2
QSPI_INSTRUCTION_1_LINE
QSPI_INSTRUCTION_2_LINES
QSPI_INSTRUCTION_4_LINES
QSPI_INSTRUCTION_NONE
QSPI_IT_FT
QSPI_IT_SM
QSPI_IT_TC
QSPI_IT_TE
QSPI_IT_TO
QSPI_MATCH_MODE_AND
QSPI_MATCH_MODE_OR
QSPI_SAMPLE_SHIFTING_HALFCYCLE
QSPI_SAMPLE_SHIFTING_NONE
QSPI_SIOO_INST_EVERY_CMD
QSPI_SIOO_INST_ONLY_FIRST_CMD
QSPI_TIMEOUT_COUNTER_DISABLE
QSPI_TIMEOUT_COUNTER_ENABLE
pQSPI_CallbackTypeDef
QSPI_HandleTypeDef
HAL_QSPI_CallbackIDTypeDef
HAL_QSPI_StateTypeDef
HAL_QSPI_Abort
HAL_QSPI_Abort_IT
HAL_QSPI_AbortCpltCallback
HAL_QSPI_AutoPolling
HAL_QSPI_AutoPolling_IT
HAL_QSPI_CmdCpltCallback
HAL_QSPI_Command
HAL_QSPI_Command_IT
HAL_QSPI_DeInit
HAL_QSPI_ErrorCallback
HAL_QSPI_FifoThresholdCallback
HAL_QSPI_GetError
HAL_QSPI_GetFifoThreshold
HAL_QSPI_GetState
HAL_QSPI_Init
HAL_QSPI_IRQHandler
HAL_QSPI_MemoryMapped
HAL_QSPI_MspDeInit
HAL_QSPI_MspInit
HAL_QSPI_Receive
HAL_QSPI_Receive_DMA
HAL_QSPI_Receive_IT
HAL_QSPI_RegisterCallback
HAL_QSPI_RxCpltCallback
HAL_QSPI_RxHalfCpltCallback
HAL_QSPI_SetFifoThreshold
HAL_QSPI_SetFlashID
HAL_QSPI_SetTimeout
HAL_QSPI_StatusMatchCallback
HAL_QSPI_TimeOutCallback
HAL_QSPI_Transmit
HAL_QSPI_Transmit_DMA
HAL_QSPI_Transmit_IT
HAL_QSPI_TxCpltCallback
HAL_QSPI_TxHalfCpltCallback
HAL_QSPI_UnRegisterCallback
stm32g4xx_hal_rcc.c
HSE_TIMEOUT_VALUE
HSI48_TIMEOUT_VALUE
HSI_TIMEOUT_VALUE
LSI_TIMEOUT_VALUE
PLL_TIMEOUT_VALUE
RCC_GET_MCO_GPIO_AF
RCC_GET_MCO_GPIO_INDEX
RCC_GET_MCO_GPIO_PIN
RCC_GET_MCO_GPIO_PORT
RCC_PLL_OSCSOURCE_CONFIG
HAL_RCC_ClockConfig
HAL_RCC_CSSCallback
HAL_RCC_DeInit
HAL_RCC_DisableLSECSS
HAL_RCC_EnableCSS
HAL_RCC_EnableLSECSS
HAL_RCC_GetClockConfig
HAL_RCC_GetHCLKFreq
HAL_RCC_GetOscConfig
HAL_RCC_GetPCLK1Freq
HAL_RCC_GetPCLK2Freq
HAL_RCC_GetSysClockFreq
HAL_RCC_MCOConfig
HAL_RCC_NMI_IRQHandler
HAL_RCC_OscConfig
RCC_GetSysClockFreqFromPLLSource
stm32g4xx_hal_rcc.h
__HAL_RCC_ADC12_CLK_ENABLE
__HAL_RCC_ADC12_CLK_SLEEP_DISABLE
__HAL_RCC_ADC12_CLK_SLEEP_ENABLE
__HAL_RCC_ADC12_FORCE_RESET
__HAL_RCC_ADC12_IS_CLK_DISABLED
__HAL_RCC_ADC12_IS_CLK_ENABLED
__HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED
__HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED
__HAL_RCC_ADC12_RELEASE_RESET
__HAL_RCC_ADC345_CLK_DISABLE
__HAL_RCC_ADC345_CLK_ENABLE
__HAL_RCC_ADC345_CLK_SLEEP_DISABLE
__HAL_RCC_ADC345_CLK_SLEEP_ENABLE
__HAL_RCC_ADC345_FORCE_RESET
__HAL_RCC_ADC345_IS_CLK_DISABLED
__HAL_RCC_ADC345_IS_CLK_ENABLED
__HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED
__HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED
__HAL_RCC_ADC345_RELEASE_RESET
__HAL_RCC_AHB1_FORCE_RESET
__HAL_RCC_AHB1_RELEASE_RESET
__HAL_RCC_AHB2_FORCE_RESET
__HAL_RCC_AHB2_RELEASE_RESET
__HAL_RCC_AHB3_FORCE_RESET
__HAL_RCC_AHB3_RELEASE_RESET
__HAL_RCC_APB1_FORCE_RESET
__HAL_RCC_APB1_RELEASE_RESET
__HAL_RCC_APB2_FORCE_RESET
__HAL_RCC_APB2_RELEASE_RESET
__HAL_RCC_BACKUPRESET_FORCE
__HAL_RCC_BACKUPRESET_RELEASE
__HAL_RCC_CCM_CLK_SLEEP_DISABLE
__HAL_RCC_CCM_CLK_SLEEP_ENABLE
__HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CLEAR_IT
__HAL_RCC_CLEAR_RESET_FLAGS
__HAL_RCC_CORDIC_CLK_DISABLE
__HAL_RCC_CORDIC_CLK_ENABLE
__HAL_RCC_CORDIC_CLK_SLEEP_DISABLE
__HAL_RCC_CORDIC_CLK_SLEEP_ENABLE
__HAL_RCC_CORDIC_FORCE_RESET
__HAL_RCC_CORDIC_IS_CLK_DISABLED
__HAL_RCC_CORDIC_IS_CLK_ENABLED
__HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CORDIC_RELEASE_RESET
__HAL_RCC_CRC_CLK_DISABLE
__HAL_RCC_CRC_CLK_ENABLE
__HAL_RCC_CRC_CLK_SLEEP_DISABLE
__HAL_RCC_CRC_CLK_SLEEP_ENABLE
__HAL_RCC_CRC_FORCE_RESET
__HAL_RCC_CRC_IS_CLK_DISABLED
__HAL_RCC_CRC_IS_CLK_ENABLED
__HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CRC_RELEASE_RESET
__HAL_RCC_CRS_CLK_DISABLE
__HAL_RCC_CRS_CLK_ENABLE
__HAL_RCC_CRS_CLK_SLEEP_DISABLE
__HAL_RCC_CRS_CLK_SLEEP_ENABLE
__HAL_RCC_CRS_FORCE_RESET
__HAL_RCC_CRS_IS_CLK_DISABLED
__HAL_RCC_CRS_IS_CLK_ENABLED
__HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED
__HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED
__HAL_RCC_CRS_RELEASE_RESET
__HAL_RCC_DAC1_CLK_DISABLE
__HAL_RCC_DAC1_CLK_ENABLE
__HAL_RCC_DAC1_CLK_SLEEP_DISABLE
__HAL_RCC_DAC1_CLK_SLEEP_ENABLE
__HAL_RCC_DAC1_FORCE_RESET
__HAL_RCC_DAC1_IS_CLK_DISABLED
__HAL_RCC_DAC1_IS_CLK_ENABLED
__HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC1_RELEASE_RESET
__HAL_RCC_DAC2_CLK_DISABLE
__HAL_RCC_DAC2_CLK_ENABLE
__HAL_RCC_DAC2_CLK_SLEEP_DISABLE
__HAL_RCC_DAC2_CLK_SLEEP_ENABLE
__HAL_RCC_DAC2_FORCE_RESET
__HAL_RCC_DAC2_IS_CLK_DISABLED
__HAL_RCC_DAC2_IS_CLK_ENABLED
__HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC2_RELEASE_RESET
__HAL_RCC_DAC3_CLK_DISABLE
__HAL_RCC_DAC3_CLK_ENABLE
__HAL_RCC_DAC3_CLK_SLEEP_DISABLE
__HAL_RCC_DAC3_CLK_SLEEP_ENABLE
__HAL_RCC_DAC3_FORCE_RESET
__HAL_RCC_DAC3_IS_CLK_DISABLED
__HAL_RCC_DAC3_IS_CLK_ENABLED
__HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC3_RELEASE_RESET
__HAL_RCC_DAC4_CLK_DISABLE
__HAL_RCC_DAC4_CLK_ENABLE
__HAL_RCC_DAC4_CLK_SLEEP_DISABLE
__HAL_RCC_DAC4_CLK_SLEEP_ENABLE
__HAL_RCC_DAC4_FORCE_RESET
__HAL_RCC_DAC4_IS_CLK_DISABLED
__HAL_RCC_DAC4_IS_CLK_ENABLED
__HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DAC4_RELEASE_RESET
__HAL_RCC_DISABLE_IT
__HAL_RCC_DMA1_CLK_DISABLE
__HAL_RCC_DMA1_CLK_ENABLE
__HAL_RCC_DMA1_CLK_SLEEP_DISABLE
__HAL_RCC_DMA1_CLK_SLEEP_ENABLE
__HAL_RCC_DMA1_FORCE_RESET
__HAL_RCC_DMA1_IS_CLK_DISABLED
__HAL_RCC_DMA1_IS_CLK_ENABLED
__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMA1_RELEASE_RESET
__HAL_RCC_DMA2_CLK_DISABLE
__HAL_RCC_DMA2_CLK_ENABLE
__HAL_RCC_DMA2_CLK_SLEEP_DISABLE
__HAL_RCC_DMA2_CLK_SLEEP_ENABLE
__HAL_RCC_DMA2_FORCE_RESET
__HAL_RCC_DMA2_IS_CLK_DISABLED
__HAL_RCC_DMA2_IS_CLK_ENABLED
__HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMA2_RELEASE_RESET
__HAL_RCC_DMAMUX1_CLK_DISABLE
__HAL_RCC_DMAMUX1_CLK_ENABLE
__HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE
__HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE
__HAL_RCC_DMAMUX1_FORCE_RESET
__HAL_RCC_DMAMUX1_IS_CLK_DISABLED
__HAL_RCC_DMAMUX1_IS_CLK_ENABLED
__HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_DMAMUX1_RELEASE_RESET
__HAL_RCC_ENABLE_IT
__HAL_RCC_FDCAN_CLK_DISABLE
__HAL_RCC_FDCAN_CLK_ENABLE
__HAL_RCC_FDCAN_CLK_SLEEP_DISABLE
__HAL_RCC_FDCAN_CLK_SLEEP_ENABLE
__HAL_RCC_FDCAN_FORCE_RESET
__HAL_RCC_FDCAN_IS_CLK_DISABLED
__HAL_RCC_FDCAN_IS_CLK_ENABLED
__HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FDCAN_RELEASE_RESET
__HAL_RCC_FLASH_CLK_DISABLE
__HAL_RCC_FLASH_CLK_ENABLE
__HAL_RCC_FLASH_CLK_SLEEP_DISABLE
__HAL_RCC_FLASH_CLK_SLEEP_ENABLE
__HAL_RCC_FLASH_FORCE_RESET
__HAL_RCC_FLASH_IS_CLK_DISABLED
__HAL_RCC_FLASH_IS_CLK_ENABLED
__HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FLASH_RELEASE_RESET
__HAL_RCC_FMAC_CLK_DISABLE
__HAL_RCC_FMAC_CLK_ENABLE
__HAL_RCC_FMAC_CLK_SLEEP_DISABLE
__HAL_RCC_FMAC_CLK_SLEEP_ENABLE
__HAL_RCC_FMAC_FORCE_RESET
__HAL_RCC_FMAC_IS_CLK_DISABLED
__HAL_RCC_FMAC_IS_CLK_ENABLED
__HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FMAC_RELEASE_RESET
__HAL_RCC_FMC_CLK_DISABLE
__HAL_RCC_FMC_CLK_ENABLE
__HAL_RCC_FMC_CLK_SLEEP_DISABLE
__HAL_RCC_FMC_CLK_SLEEP_ENABLE
__HAL_RCC_FMC_FORCE_RESET
__HAL_RCC_FMC_IS_CLK_DISABLED
__HAL_RCC_FMC_IS_CLK_ENABLED
__HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_FMC_RELEASE_RESET
__HAL_RCC_GET_FLAG
__HAL_RCC_GET_IT
__HAL_RCC_GET_PLL_OSCSOURCE
__HAL_RCC_GET_PLLCLKOUT_CONFIG
__HAL_RCC_GET_RTC_SOURCE
__HAL_RCC_GET_SYSCLK_SOURCE
__HAL_RCC_GPIOA_CLK_DISABLE
__HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOA_FORCE_RESET
__HAL_RCC_GPIOA_IS_CLK_DISABLED
__HAL_RCC_GPIOA_IS_CLK_ENABLED
__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOA_RELEASE_RESET
__HAL_RCC_GPIOB_CLK_DISABLE
__HAL_RCC_GPIOB_CLK_ENABLE
__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOB_FORCE_RESET
__HAL_RCC_GPIOB_IS_CLK_DISABLED
__HAL_RCC_GPIOB_IS_CLK_ENABLED
__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOB_RELEASE_RESET
__HAL_RCC_GPIOC_CLK_DISABLE
__HAL_RCC_GPIOC_CLK_ENABLE
__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOC_FORCE_RESET
__HAL_RCC_GPIOC_IS_CLK_DISABLED
__HAL_RCC_GPIOC_IS_CLK_ENABLED
__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOC_RELEASE_RESET
__HAL_RCC_GPIOD_CLK_DISABLE
__HAL_RCC_GPIOD_CLK_ENABLE
__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOD_FORCE_RESET
__HAL_RCC_GPIOD_IS_CLK_DISABLED
__HAL_RCC_GPIOD_IS_CLK_ENABLED
__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOD_RELEASE_RESET
__HAL_RCC_GPIOE_CLK_DISABLE
__HAL_RCC_GPIOE_CLK_ENABLE
__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOE_FORCE_RESET
__HAL_RCC_GPIOE_IS_CLK_DISABLED
__HAL_RCC_GPIOE_IS_CLK_ENABLED
__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOE_RELEASE_RESET
__HAL_RCC_GPIOF_CLK_DISABLE
__HAL_RCC_GPIOF_CLK_ENABLE
__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOF_FORCE_RESET
__HAL_RCC_GPIOF_IS_CLK_DISABLED
__HAL_RCC_GPIOF_IS_CLK_ENABLED
__HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOF_RELEASE_RESET
__HAL_RCC_GPIOG_CLK_DISABLE
__HAL_RCC_GPIOG_CLK_ENABLE
__HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
__HAL_RCC_GPIOG_FORCE_RESET
__HAL_RCC_GPIOG_IS_CLK_DISABLED
__HAL_RCC_GPIOG_IS_CLK_ENABLED
__HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_GPIOG_RELEASE_RESET
__HAL_RCC_HRTIM1_CLK_DISABLE
__HAL_RCC_HRTIM1_CLK_ENABLE
__HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE
__HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE
__HAL_RCC_HRTIM1_FORCE_RESET
__HAL_RCC_HRTIM1_IS_CLK_DISABLED
__HAL_RCC_HRTIM1_IS_CLK_ENABLED
__HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_HRTIM1_RELEASE_RESET
__HAL_RCC_HSE_CONFIG
__HAL_RCC_HSI48_DISABLE
__HAL_RCC_HSI48_ENABLE
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST
__HAL_RCC_HSI_DISABLE
__HAL_RCC_HSI_ENABLE
__HAL_RCC_HSISTOP_DISABLE
__HAL_RCC_HSISTOP_ENABLE
__HAL_RCC_I2C1_CLK_DISABLE
__HAL_RCC_I2C1_CLK_ENABLE
__HAL_RCC_I2C1_CLK_SLEEP_DISABLE
__HAL_RCC_I2C1_CLK_SLEEP_ENABLE
__HAL_RCC_I2C1_FORCE_RESET
__HAL_RCC_I2C1_IS_CLK_DISABLED
__HAL_RCC_I2C1_IS_CLK_ENABLED
__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C1_RELEASE_RESET
__HAL_RCC_I2C2_CLK_DISABLE
__HAL_RCC_I2C2_CLK_ENABLE
__HAL_RCC_I2C2_CLK_SLEEP_DISABLE
__HAL_RCC_I2C2_CLK_SLEEP_ENABLE
__HAL_RCC_I2C2_FORCE_RESET
__HAL_RCC_I2C2_IS_CLK_DISABLED
__HAL_RCC_I2C2_IS_CLK_ENABLED
__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C2_RELEASE_RESET
__HAL_RCC_I2C3_CLK_DISABLE
__HAL_RCC_I2C3_CLK_ENABLE
__HAL_RCC_I2C3_CLK_SLEEP_DISABLE
__HAL_RCC_I2C3_CLK_SLEEP_ENABLE
__HAL_RCC_I2C3_FORCE_RESET
__HAL_RCC_I2C3_IS_CLK_DISABLED
__HAL_RCC_I2C3_IS_CLK_ENABLED
__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C3_RELEASE_RESET
__HAL_RCC_I2C4_CLK_DISABLE
__HAL_RCC_I2C4_CLK_ENABLE
__HAL_RCC_I2C4_CLK_SLEEP_DISABLE
__HAL_RCC_I2C4_CLK_SLEEP_ENABLE
__HAL_RCC_I2C4_FORCE_RESET
__HAL_RCC_I2C4_IS_CLK_DISABLED
__HAL_RCC_I2C4_IS_CLK_ENABLED
__HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_I2C4_RELEASE_RESET
__HAL_RCC_LPTIM1_CLK_DISABLE
__HAL_RCC_LPTIM1_CLK_ENABLE
__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
__HAL_RCC_LPTIM1_FORCE_RESET
__HAL_RCC_LPTIM1_IS_CLK_DISABLED
__HAL_RCC_LPTIM1_IS_CLK_ENABLED
__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_LPTIM1_RELEASE_RESET
__HAL_RCC_LPUART1_CLK_DISABLE
__HAL_RCC_LPUART1_CLK_ENABLE
__HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
__HAL_RCC_LPUART1_FORCE_RESET
__HAL_RCC_LPUART1_IS_CLK_DISABLED
__HAL_RCC_LPUART1_IS_CLK_ENABLED
__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_LPUART1_RELEASE_RESET
__HAL_RCC_LSE_CONFIG
__HAL_RCC_LSEDRIVE_CONFIG
__HAL_RCC_LSI_DISABLE
__HAL_RCC_LSI_ENABLE
__HAL_RCC_MCO1_CONFIG
__HAL_RCC_PLL_CONFIG
__HAL_RCC_PLL_DISABLE
__HAL_RCC_PLL_ENABLE
__HAL_RCC_PLL_PLLM_CONFIG
__HAL_RCC_PLL_PLLSOURCE_CONFIG
__HAL_RCC_PLLCLKOUT_DISABLE
__HAL_RCC_PLLCLKOUT_ENABLE
__HAL_RCC_PWR_CLK_DISABLE
__HAL_RCC_PWR_CLK_ENABLE
__HAL_RCC_PWR_CLK_SLEEP_DISABLE
__HAL_RCC_PWR_CLK_SLEEP_ENABLE
__HAL_RCC_PWR_FORCE_RESET
__HAL_RCC_PWR_IS_CLK_DISABLED
__HAL_RCC_PWR_IS_CLK_ENABLED
__HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED
__HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED
__HAL_RCC_PWR_RELEASE_RESET
__HAL_RCC_QSPI_CLK_DISABLE
__HAL_RCC_QSPI_CLK_ENABLE
__HAL_RCC_QSPI_CLK_SLEEP_DISABLE
__HAL_RCC_QSPI_CLK_SLEEP_ENABLE
__HAL_RCC_QSPI_FORCE_RESET
__HAL_RCC_QSPI_IS_CLK_DISABLED
__HAL_RCC_QSPI_IS_CLK_ENABLED
__HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED
__HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED
__HAL_RCC_QSPI_RELEASE_RESET
__HAL_RCC_RNG_CLK_DISABLE
__HAL_RCC_RNG_CLK_ENABLE
__HAL_RCC_RNG_CLK_SLEEP_DISABLE
__HAL_RCC_RNG_CLK_SLEEP_ENABLE
__HAL_RCC_RNG_FORCE_RESET
__HAL_RCC_RNG_IS_CLK_DISABLED
__HAL_RCC_RNG_IS_CLK_ENABLED
__HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_RNG_RELEASE_RESET
__HAL_RCC_RTC_CONFIG
__HAL_RCC_RTC_DISABLE
__HAL_RCC_RTC_ENABLE
__HAL_RCC_RTCAPB_CLK_DISABLE
__HAL_RCC_RTCAPB_CLK_ENABLE
__HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE
__HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE
__HAL_RCC_RTCAPB_IS_CLK_DISABLED
__HAL_RCC_RTCAPB_IS_CLK_ENABLED
__HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SAI1_CLK_DISABLE
__HAL_RCC_SAI1_CLK_ENABLE
__HAL_RCC_SAI1_CLK_SLEEP_DISABLE
__HAL_RCC_SAI1_CLK_SLEEP_ENABLE
__HAL_RCC_SAI1_FORCE_RESET
__HAL_RCC_SAI1_IS_CLK_DISABLED
__HAL_RCC_SAI1_IS_CLK_ENABLED
__HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SAI1_RELEASE_RESET
__HAL_RCC_SPI1_CLK_DISABLE
__HAL_RCC_SPI1_CLK_ENABLE
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE
__HAL_RCC_SPI1_CLK_SLEEP_ENABLE
__HAL_RCC_SPI1_FORCE_RESET
__HAL_RCC_SPI1_IS_CLK_DISABLED
__HAL_RCC_SPI1_IS_CLK_ENABLED
__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI1_RELEASE_RESET
__HAL_RCC_SPI2_CLK_DISABLE
__HAL_RCC_SPI2_CLK_ENABLE
__HAL_RCC_SPI2_CLK_SLEEP_DISABLE
__HAL_RCC_SPI2_CLK_SLEEP_ENABLE
__HAL_RCC_SPI2_FORCE_RESET
__HAL_RCC_SPI2_IS_CLK_DISABLED
__HAL_RCC_SPI2_IS_CLK_ENABLED
__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI2_RELEASE_RESET
__HAL_RCC_SPI3_CLK_DISABLE
__HAL_RCC_SPI3_CLK_ENABLE
__HAL_RCC_SPI3_CLK_SLEEP_DISABLE
__HAL_RCC_SPI3_CLK_SLEEP_ENABLE
__HAL_RCC_SPI3_FORCE_RESET
__HAL_RCC_SPI3_IS_CLK_DISABLED
__HAL_RCC_SPI3_IS_CLK_ENABLED
__HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI3_RELEASE_RESET
__HAL_RCC_SPI4_CLK_DISABLE
__HAL_RCC_SPI4_CLK_ENABLE
__HAL_RCC_SPI4_CLK_SLEEP_DISABLE
__HAL_RCC_SPI4_CLK_SLEEP_ENABLE
__HAL_RCC_SPI4_FORCE_RESET
__HAL_RCC_SPI4_IS_CLK_DISABLED
__HAL_RCC_SPI4_IS_CLK_ENABLED
__HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SPI4_RELEASE_RESET
__HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
__HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
__HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
__HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
__HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SYSCFG_CLK_DISABLE
__HAL_RCC_SYSCFG_CLK_ENABLE
__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
__HAL_RCC_SYSCFG_FORCE_RESET
__HAL_RCC_SYSCFG_IS_CLK_DISABLED
__HAL_RCC_SYSCFG_IS_CLK_ENABLED
__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED
__HAL_RCC_SYSCFG_RELEASE_RESET
__HAL_RCC_SYSCLK_CONFIG
__HAL_RCC_TIM15_CLK_DISABLE
__HAL_RCC_TIM15_CLK_ENABLE
__HAL_RCC_TIM15_CLK_SLEEP_DISABLE
__HAL_RCC_TIM15_CLK_SLEEP_ENABLE
__HAL_RCC_TIM15_FORCE_RESET
__HAL_RCC_TIM15_IS_CLK_DISABLED
__HAL_RCC_TIM15_IS_CLK_ENABLED
__HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM15_RELEASE_RESET
__HAL_RCC_TIM16_CLK_DISABLE
__HAL_RCC_TIM16_CLK_ENABLE
__HAL_RCC_TIM16_CLK_SLEEP_DISABLE
__HAL_RCC_TIM16_CLK_SLEEP_ENABLE
__HAL_RCC_TIM16_FORCE_RESET
__HAL_RCC_TIM16_IS_CLK_DISABLED
__HAL_RCC_TIM16_IS_CLK_ENABLED
__HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM16_RELEASE_RESET
__HAL_RCC_TIM17_CLK_DISABLE
__HAL_RCC_TIM17_CLK_ENABLE
__HAL_RCC_TIM17_CLK_SLEEP_DISABLE
__HAL_RCC_TIM17_CLK_SLEEP_ENABLE
__HAL_RCC_TIM17_FORCE_RESET
__HAL_RCC_TIM17_IS_CLK_DISABLED
__HAL_RCC_TIM17_IS_CLK_ENABLED
__HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM17_RELEASE_RESET
__HAL_RCC_TIM1_CLK_DISABLE
__HAL_RCC_TIM1_CLK_ENABLE
__HAL_RCC_TIM1_CLK_SLEEP_DISABLE
__HAL_RCC_TIM1_CLK_SLEEP_ENABLE
__HAL_RCC_TIM1_FORCE_RESET
__HAL_RCC_TIM1_IS_CLK_DISABLED
__HAL_RCC_TIM1_IS_CLK_ENABLED
__HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM1_RELEASE_RESET
__HAL_RCC_TIM20_CLK_DISABLE
__HAL_RCC_TIM20_CLK_ENABLE
__HAL_RCC_TIM20_CLK_SLEEP_DISABLE
__HAL_RCC_TIM20_CLK_SLEEP_ENABLE
__HAL_RCC_TIM20_FORCE_RESET
__HAL_RCC_TIM20_IS_CLK_DISABLED
__HAL_RCC_TIM20_IS_CLK_ENABLED
__HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM20_RELEASE_RESET
__HAL_RCC_TIM2_CLK_DISABLE
__HAL_RCC_TIM2_CLK_ENABLE
__HAL_RCC_TIM2_CLK_SLEEP_DISABLE
__HAL_RCC_TIM2_CLK_SLEEP_ENABLE
__HAL_RCC_TIM2_FORCE_RESET
__HAL_RCC_TIM2_IS_CLK_DISABLED
__HAL_RCC_TIM2_IS_CLK_ENABLED
__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM2_RELEASE_RESET
__HAL_RCC_TIM3_CLK_DISABLE
__HAL_RCC_TIM3_CLK_ENABLE
__HAL_RCC_TIM3_CLK_SLEEP_DISABLE
__HAL_RCC_TIM3_CLK_SLEEP_ENABLE
__HAL_RCC_TIM3_FORCE_RESET
__HAL_RCC_TIM3_IS_CLK_DISABLED
__HAL_RCC_TIM3_IS_CLK_ENABLED
__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM3_RELEASE_RESET
__HAL_RCC_TIM4_CLK_DISABLE
__HAL_RCC_TIM4_CLK_ENABLE
__HAL_RCC_TIM4_CLK_SLEEP_DISABLE
__HAL_RCC_TIM4_CLK_SLEEP_ENABLE
__HAL_RCC_TIM4_FORCE_RESET
__HAL_RCC_TIM4_IS_CLK_DISABLED
__HAL_RCC_TIM4_IS_CLK_ENABLED
__HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM4_RELEASE_RESET
__HAL_RCC_TIM5_CLK_DISABLE
__HAL_RCC_TIM5_CLK_ENABLE
__HAL_RCC_TIM5_CLK_SLEEP_DISABLE
__HAL_RCC_TIM5_CLK_SLEEP_ENABLE
__HAL_RCC_TIM5_FORCE_RESET
__HAL_RCC_TIM5_IS_CLK_DISABLED
__HAL_RCC_TIM5_IS_CLK_ENABLED
__HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM5_RELEASE_RESET
__HAL_RCC_TIM6_CLK_DISABLE
__HAL_RCC_TIM6_CLK_ENABLE
__HAL_RCC_TIM6_CLK_SLEEP_DISABLE
__HAL_RCC_TIM6_CLK_SLEEP_ENABLE
__HAL_RCC_TIM6_FORCE_RESET
__HAL_RCC_TIM6_IS_CLK_DISABLED
__HAL_RCC_TIM6_IS_CLK_ENABLED
__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM6_RELEASE_RESET
__HAL_RCC_TIM7_CLK_DISABLE
__HAL_RCC_TIM7_CLK_ENABLE
__HAL_RCC_TIM7_CLK_SLEEP_DISABLE
__HAL_RCC_TIM7_CLK_SLEEP_ENABLE
__HAL_RCC_TIM7_FORCE_RESET
__HAL_RCC_TIM7_IS_CLK_DISABLED
__HAL_RCC_TIM7_IS_CLK_ENABLED
__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM7_RELEASE_RESET
__HAL_RCC_TIM8_CLK_DISABLE
__HAL_RCC_TIM8_CLK_ENABLE
__HAL_RCC_TIM8_CLK_SLEEP_DISABLE
__HAL_RCC_TIM8_CLK_SLEEP_ENABLE
__HAL_RCC_TIM8_FORCE_RESET
__HAL_RCC_TIM8_IS_CLK_DISABLED
__HAL_RCC_TIM8_IS_CLK_ENABLED
__HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED
__HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED
__HAL_RCC_TIM8_RELEASE_RESET
__HAL_RCC_UART4_CLK_DISABLE
__HAL_RCC_UART4_CLK_ENABLE
__HAL_RCC_UART4_CLK_SLEEP_DISABLE
__HAL_RCC_UART4_CLK_SLEEP_ENABLE
__HAL_RCC_UART4_FORCE_RESET
__HAL_RCC_UART4_IS_CLK_DISABLED
__HAL_RCC_UART4_IS_CLK_ENABLED
__HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UART4_RELEASE_RESET
__HAL_RCC_UART5_CLK_DISABLE
__HAL_RCC_UART5_CLK_ENABLE
__HAL_RCC_UART5_CLK_SLEEP_DISABLE
__HAL_RCC_UART5_CLK_SLEEP_ENABLE
__HAL_RCC_UART5_FORCE_RESET
__HAL_RCC_UART5_IS_CLK_DISABLED
__HAL_RCC_UART5_IS_CLK_ENABLED
__HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UART5_RELEASE_RESET
__HAL_RCC_UCPD1_CLK_DISABLE
__HAL_RCC_UCPD1_CLK_ENABLE
__HAL_RCC_UCPD1_CLK_SLEEP_DISABLE
__HAL_RCC_UCPD1_CLK_SLEEP_ENABLE
__HAL_RCC_UCPD1_FORCE_RESET
__HAL_RCC_UCPD1_IS_CLK_DISABLED
__HAL_RCC_UCPD1_IS_CLK_ENABLED
__HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_UCPD1_RELEASE_RESET
__HAL_RCC_USART1_CLK_DISABLE
__HAL_RCC_USART1_CLK_ENABLE
__HAL_RCC_USART1_CLK_SLEEP_DISABLE
__HAL_RCC_USART1_CLK_SLEEP_ENABLE
__HAL_RCC_USART1_FORCE_RESET
__HAL_RCC_USART1_IS_CLK_DISABLED
__HAL_RCC_USART1_IS_CLK_ENABLED
__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART1_RELEASE_RESET
__HAL_RCC_USART2_CLK_DISABLE
__HAL_RCC_USART2_CLK_ENABLE
__HAL_RCC_USART2_CLK_SLEEP_DISABLE
__HAL_RCC_USART2_CLK_SLEEP_ENABLE
__HAL_RCC_USART2_FORCE_RESET
__HAL_RCC_USART2_IS_CLK_DISABLED
__HAL_RCC_USART2_IS_CLK_ENABLED
__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART2_RELEASE_RESET
__HAL_RCC_USART3_CLK_DISABLE
__HAL_RCC_USART3_CLK_ENABLE
__HAL_RCC_USART3_CLK_SLEEP_DISABLE
__HAL_RCC_USART3_CLK_SLEEP_ENABLE
__HAL_RCC_USART3_FORCE_RESET
__HAL_RCC_USART3_IS_CLK_DISABLED
__HAL_RCC_USART3_IS_CLK_ENABLED
__HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USART3_RELEASE_RESET
__HAL_RCC_USB_CLK_DISABLE
__HAL_RCC_USB_CLK_ENABLE
__HAL_RCC_USB_CLK_SLEEP_DISABLE
__HAL_RCC_USB_CLK_SLEEP_ENABLE
__HAL_RCC_USB_FORCE_RESET
__HAL_RCC_USB_IS_CLK_DISABLED
__HAL_RCC_USB_IS_CLK_ENABLED
__HAL_RCC_USB_IS_CLK_SLEEP_DISABLED
__HAL_RCC_USB_IS_CLK_SLEEP_ENABLED
__HAL_RCC_USB_RELEASE_RESET
__HAL_RCC_WWDG_CLK_DISABLE
__HAL_RCC_WWDG_CLK_ENABLE
__HAL_RCC_WWDG_CLK_SLEEP_DISABLE
__HAL_RCC_WWDG_CLK_SLEEP_ENABLE
__HAL_RCC_WWDG_IS_CLK_DISABLED
__HAL_RCC_WWDG_IS_CLK_ENABLED
__HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED
__HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED
BDCR_REG_INDEX
CR_REG_INDEX
CRRCR_REG_INDEX
CSR_REG_INDEX
IS_RCC_CLOCKTYPE
IS_RCC_HCLK
IS_RCC_HSE
IS_RCC_HSI
IS_RCC_HSI48
IS_RCC_HSI_CALIBRATION_VALUE
IS_RCC_LSE
IS_RCC_LSE_DRIVE
IS_RCC_LSI
IS_RCC_MCO
IS_RCC_MCO1SOURCE
IS_RCC_MCODIV
IS_RCC_OSCILLATORTYPE
IS_RCC_PCLK
IS_RCC_PLL
IS_RCC_PLLM_VALUE
IS_RCC_PLLN_VALUE
IS_RCC_PLLP_VALUE
IS_RCC_PLLQ_VALUE
IS_RCC_PLLR_VALUE
IS_RCC_PLLSOURCE
IS_RCC_RTCCLKSOURCE
IS_RCC_SYSCLKSOURCE
RCC_CLOCKTYPE_ALL
RCC_CLOCKTYPE_HCLK
RCC_CLOCKTYPE_PCLK1
RCC_CLOCKTYPE_PCLK2
RCC_CLOCKTYPE_SYSCLK
RCC_DBP_TIMEOUT_VALUE
RCC_FLAG_BORRST
RCC_FLAG_HSERDY
RCC_FLAG_HSI48RDY
RCC_FLAG_HSIRDY
RCC_FLAG_IWDGRST
RCC_FLAG_LPWRRST
RCC_FLAG_LSECSSD
RCC_FLAG_LSERDY
RCC_FLAG_LSIRDY
RCC_FLAG_MASK
RCC_FLAG_OBLRST
RCC_FLAG_PINRST
RCC_FLAG_PLLRDY
RCC_FLAG_SFTRST
RCC_FLAG_WWDGRST
RCC_HCLK_DIV1
RCC_HCLK_DIV16
RCC_HCLK_DIV2
RCC_HCLK_DIV4
RCC_HCLK_DIV8
RCC_HSE_BYPASS
RCC_HSE_OFF
RCC_HSE_ON
RCC_HSI48_OFF
RCC_HSI48_ON
RCC_HSI_OFF
RCC_HSI_ON
RCC_HSICALIBRATION_DEFAULT
RCC_IT_CSS
RCC_IT_HSERDY
RCC_IT_HSI48RDY
RCC_IT_HSIRDY
RCC_IT_LSECSS
RCC_IT_LSERDY
RCC_IT_LSIRDY
RCC_IT_PLLRDY
RCC_LSE_BYPASS
RCC_LSE_OFF
RCC_LSE_ON
RCC_LSE_TIMEOUT_VALUE
RCC_LSEDRIVE_HIGH
RCC_LSEDRIVE_LOW
RCC_LSEDRIVE_MEDIUMHIGH
RCC_LSEDRIVE_MEDIUMLOW
RCC_LSI_OFF
RCC_LSI_ON
RCC_MCO
RCC_MCO1
RCC_MCO1_INDEX
RCC_MCO1SOURCE_HSE
RCC_MCO1SOURCE_HSI
RCC_MCO1SOURCE_HSI48
RCC_MCO1SOURCE_LSE
RCC_MCO1SOURCE_LSI
RCC_MCO1SOURCE_NOCLOCK
RCC_MCO1SOURCE_PLLCLK
RCC_MCO1SOURCE_SYSCLK
RCC_MCO_GPIOAF_MASK
RCC_MCO_GPIOAF_POS
RCC_MCO_GPIOPORT_MASK
RCC_MCO_GPIOPORT_POS
RCC_MCO_INDEX_MASK
RCC_MCO_INDEX_POS
RCC_MCO_PA8
RCC_MCO_PG10
RCC_MCODIV_1
RCC_MCODIV_16
RCC_MCODIV_2
RCC_MCODIV_4
RCC_MCODIV_8
RCC_OSCILLATORTYPE_HSE
RCC_OSCILLATORTYPE_HSI
RCC_OSCILLATORTYPE_HSI48
RCC_OSCILLATORTYPE_LSE
RCC_OSCILLATORTYPE_LSI
RCC_OSCILLATORTYPE_NONE
RCC_PLL_48M1CLK
RCC_PLL_ADCCLK
RCC_PLL_NONE
RCC_PLL_OFF
RCC_PLL_ON
RCC_PLL_SYSCLK
RCC_PLLM_DIV1
RCC_PLLM_DIV10
RCC_PLLM_DIV11
RCC_PLLM_DIV12
RCC_PLLM_DIV13
RCC_PLLM_DIV14
RCC_PLLM_DIV15
RCC_PLLM_DIV16
RCC_PLLM_DIV2
RCC_PLLM_DIV3
RCC_PLLM_DIV4
RCC_PLLM_DIV5
RCC_PLLM_DIV6
RCC_PLLM_DIV7
RCC_PLLM_DIV8
RCC_PLLM_DIV9
RCC_PLLP_DIV10
RCC_PLLP_DIV11
RCC_PLLP_DIV12
RCC_PLLP_DIV13
RCC_PLLP_DIV14
RCC_PLLP_DIV15
RCC_PLLP_DIV16
RCC_PLLP_DIV17
RCC_PLLP_DIV18
RCC_PLLP_DIV19
RCC_PLLP_DIV2
RCC_PLLP_DIV20
RCC_PLLP_DIV21
RCC_PLLP_DIV22
RCC_PLLP_DIV23
RCC_PLLP_DIV24
RCC_PLLP_DIV25
RCC_PLLP_DIV26
RCC_PLLP_DIV27
RCC_PLLP_DIV28
RCC_PLLP_DIV29
RCC_PLLP_DIV3
RCC_PLLP_DIV30
RCC_PLLP_DIV31
RCC_PLLP_DIV4
RCC_PLLP_DIV5
RCC_PLLP_DIV6
RCC_PLLP_DIV7
RCC_PLLP_DIV8
RCC_PLLP_DIV9
RCC_PLLQ_DIV2
RCC_PLLQ_DIV4
RCC_PLLQ_DIV6
RCC_PLLQ_DIV8
RCC_PLLR_DIV2
RCC_PLLR_DIV4
RCC_PLLR_DIV6
RCC_PLLR_DIV8
RCC_PLLSOURCE_HSE
RCC_PLLSOURCE_HSI
RCC_PLLSOURCE_NONE
RCC_RTCCLKSOURCE_HSE_DIV32
RCC_RTCCLKSOURCE_LSE
RCC_RTCCLKSOURCE_LSI
RCC_RTCCLKSOURCE_NONE
RCC_SYSCLK_DIV1
RCC_SYSCLK_DIV128
RCC_SYSCLK_DIV16
RCC_SYSCLK_DIV2
RCC_SYSCLK_DIV256
RCC_SYSCLK_DIV4
RCC_SYSCLK_DIV512
RCC_SYSCLK_DIV64
RCC_SYSCLK_DIV8
RCC_SYSCLKSOURCE_HSE
RCC_SYSCLKSOURCE_HSI
RCC_SYSCLKSOURCE_PLLCLK
RCC_SYSCLKSOURCE_STATUS_HSE
RCC_SYSCLKSOURCE_STATUS_HSI
RCC_SYSCLKSOURCE_STATUS_PLLCLK
HAL_RCC_ClockConfig
HAL_RCC_CSSCallback
HAL_RCC_DeInit
HAL_RCC_DisableLSECSS
HAL_RCC_EnableCSS
HAL_RCC_EnableLSECSS
HAL_RCC_GetClockConfig
HAL_RCC_GetHCLKFreq
HAL_RCC_GetOscConfig
HAL_RCC_GetPCLK1Freq
HAL_RCC_GetPCLK2Freq
HAL_RCC_GetSysClockFreq
HAL_RCC_MCOConfig
HAL_RCC_NMI_IRQHandler
HAL_RCC_OscConfig
stm32g4xx_hal_rcc_ex.c
DIVIDER_P_UPDATE
DIVIDER_Q_UPDATE
DIVIDER_R_UPDATE
LSCO_GPIO_PORT
LSCO_PIN
PLL_TIMEOUT_VALUE
HAL_RCCEx_CRS_ErrorCallback
HAL_RCCEx_CRS_ExpectedSyncCallback
HAL_RCCEx_CRS_IRQHandler
HAL_RCCEx_CRS_SyncOkCallback
HAL_RCCEx_CRS_SyncWarnCallback
HAL_RCCEx_CRSConfig
HAL_RCCEx_CRSGetSynchronizationInfo
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
HAL_RCCEx_CRSWaitSynchronization
HAL_RCCEx_DisableLSCO
HAL_RCCEx_DisableLSECSS
HAL_RCCEx_EnableLSCO
HAL_RCCEx_EnableLSECSS
HAL_RCCEx_EnableLSECSS_IT
HAL_RCCEx_GetPeriphCLKConfig
HAL_RCCEx_GetPeriphCLKFreq
HAL_RCCEx_LSECSS_Callback
HAL_RCCEx_LSECSS_IRQHandler
HAL_RCCEx_PeriphCLKConfig
stm32g4xx_hal_rcc_ex.h
__HAL_RCC_ADC345_CONFIG
__HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
__HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
__HAL_RCC_CRS_CLEAR_FLAG
__HAL_RCC_CRS_CLEAR_IT
__HAL_RCC_CRS_DISABLE_IT
__HAL_RCC_CRS_ENABLE_IT
__HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
__HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
__HAL_RCC_CRS_GET_FLAG
__HAL_RCC_CRS_GET_IT_SOURCE
__HAL_RCC_CRS_RELOADVALUE_CALCULATE
__HAL_RCC_FDCAN_CONFIG
__HAL_RCC_GET_ADC12_SOURCE
__HAL_RCC_GET_ADC345_SOURCE
__HAL_RCC_GET_FDCAN_SOURCE
__HAL_RCC_GET_I2C1_SOURCE
__HAL_RCC_GET_I2C2_SOURCE
__HAL_RCC_GET_I2C3_SOURCE
__HAL_RCC_GET_I2C4_SOURCE
__HAL_RCC_GET_I2S_SOURCE
__HAL_RCC_GET_LPTIM1_SOURCE
__HAL_RCC_GET_LPUART1_SOURCE
__HAL_RCC_GET_QSPI_SOURCE
__HAL_RCC_GET_RNG_SOURCE
__HAL_RCC_GET_SAI1_SOURCE
__HAL_RCC_GET_UART4_SOURCE
__HAL_RCC_GET_UART5_SOURCE
__HAL_RCC_GET_USART1_SOURCE
__HAL_RCC_GET_USART2_SOURCE
__HAL_RCC_GET_USART3_SOURCE
__HAL_RCC_GET_USB_SOURCE
__HAL_RCC_I2C1_CONFIG
__HAL_RCC_I2C2_CONFIG
__HAL_RCC_I2C3_CONFIG
__HAL_RCC_I2C4_CONFIG
__HAL_RCC_I2S_CONFIG
__HAL_RCC_LPTIM1_CONFIG
__HAL_RCC_LPUART1_CONFIG
__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG
__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_DISABLE_IT
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_IT
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT
__HAL_RCC_LSECSS_EXTI_GET_FLAG
__HAL_RCC_QSPI_CONFIG
__HAL_RCC_RNG_CONFIG
__HAL_RCC_SAI1_CONFIG
__HAL_RCC_UART4_CONFIG
__HAL_RCC_UART5_CONFIG
__HAL_RCC_USART1_CONFIG
__HAL_RCC_USART2_CONFIG
__HAL_RCC_USART3_CONFIG
__HAL_RCC_USB_CONFIG
IS_RCC_ADC12CLKSOURCE
IS_RCC_ADC345CLKSOURCE
IS_RCC_CRS_ERRORLIMIT
IS_RCC_CRS_FREQERRORDIR
IS_RCC_CRS_HSI48CALIBRATION
IS_RCC_CRS_RELOADVALUE
IS_RCC_CRS_SYNC_DIV
IS_RCC_CRS_SYNC_POLARITY
IS_RCC_CRS_SYNC_SOURCE
IS_RCC_FDCANCLKSOURCE
IS_RCC_I2C1CLKSOURCE
IS_RCC_I2C2CLKSOURCE
IS_RCC_I2C3CLKSOURCE
IS_RCC_I2C4CLKSOURCE
IS_RCC_I2SCLKSOURCE
IS_RCC_LPTIM1CLKSOURCE
IS_RCC_LPUART1CLKSOURCE
IS_RCC_LSCOSOURCE
IS_RCC_PERIPHCLOCK
IS_RCC_QSPICLKSOURCE
IS_RCC_RNGCLKSOURCE
IS_RCC_SAI1CLKSOURCE
IS_RCC_UART4CLKSOURCE
IS_RCC_UART5CLKSOURCE
IS_RCC_USART1CLKSOURCE
IS_RCC_USART2CLKSOURCE
IS_RCC_USART3CLKSOURCE
IS_RCC_USBCLKSOURCE
RCC_ADC12CLKSOURCE_NONE
RCC_ADC12CLKSOURCE_PLL
RCC_ADC12CLKSOURCE_SYSCLK
RCC_ADC345CLKSOURCE_NONE
RCC_ADC345CLKSOURCE_PLL
RCC_ADC345CLKSOURCE_SYSCLK
RCC_CRS_ERRORLIMIT_DEFAULT
RCC_CRS_FLAG_ERR
RCC_CRS_FLAG_ERROR_MASK
RCC_CRS_FLAG_ESYNC
RCC_CRS_FLAG_SYNCERR
RCC_CRS_FLAG_SYNCMISS
RCC_CRS_FLAG_SYNCOK
RCC_CRS_FLAG_SYNCWARN
RCC_CRS_FLAG_TRIMOVF
RCC_CRS_FREQERRORDIR_DOWN
RCC_CRS_FREQERRORDIR_UP
RCC_CRS_HSI48CALIBRATION_DEFAULT
RCC_CRS_IT_ERR
RCC_CRS_IT_ERROR_MASK
RCC_CRS_IT_ESYNC
RCC_CRS_IT_SYNCERR
RCC_CRS_IT_SYNCMISS
RCC_CRS_IT_SYNCOK
RCC_CRS_IT_SYNCWARN
RCC_CRS_IT_TRIMOVF
RCC_CRS_NONE
RCC_CRS_RELOADVALUE_DEFAULT
RCC_CRS_SYNC_DIV1
RCC_CRS_SYNC_DIV128
RCC_CRS_SYNC_DIV16
RCC_CRS_SYNC_DIV2
RCC_CRS_SYNC_DIV32
RCC_CRS_SYNC_DIV4
RCC_CRS_SYNC_DIV64
RCC_CRS_SYNC_DIV8
RCC_CRS_SYNC_POLARITY_FALLING
RCC_CRS_SYNC_POLARITY_RISING
RCC_CRS_SYNC_SOURCE_GPIO
RCC_CRS_SYNC_SOURCE_LSE
RCC_CRS_SYNC_SOURCE_USB
RCC_CRS_SYNCERR
RCC_CRS_SYNCMISS
RCC_CRS_SYNCOK
RCC_CRS_SYNCWARN
RCC_CRS_TIMEOUT
RCC_CRS_TRIMOVF
RCC_EXTI_LINE_LSECSS
RCC_FDCANCLKSOURCE_HSE
RCC_FDCANCLKSOURCE_PCLK1
RCC_FDCANCLKSOURCE_PLL
RCC_I2C1CLKSOURCE_HSI
RCC_I2C1CLKSOURCE_PCLK1
RCC_I2C1CLKSOURCE_SYSCLK
RCC_I2C2CLKSOURCE_HSI
RCC_I2C2CLKSOURCE_PCLK1
RCC_I2C2CLKSOURCE_SYSCLK
RCC_I2C3CLKSOURCE_HSI
RCC_I2C3CLKSOURCE_PCLK1
RCC_I2C3CLKSOURCE_SYSCLK
RCC_I2C4CLKSOURCE_HSI
RCC_I2C4CLKSOURCE_PCLK1
RCC_I2C4CLKSOURCE_SYSCLK
RCC_I2SCLKSOURCE_EXT
RCC_I2SCLKSOURCE_HSI
RCC_I2SCLKSOURCE_PLL
RCC_I2SCLKSOURCE_SYSCLK
RCC_LPTIM1CLKSOURCE_HSI
RCC_LPTIM1CLKSOURCE_LSE
RCC_LPTIM1CLKSOURCE_LSI
RCC_LPTIM1CLKSOURCE_PCLK1
RCC_LPUART1CLKSOURCE_HSI
RCC_LPUART1CLKSOURCE_LSE
RCC_LPUART1CLKSOURCE_PCLK1
RCC_LPUART1CLKSOURCE_SYSCLK
RCC_LSCOSOURCE_LSE
RCC_LSCOSOURCE_LSI
RCC_PERIPHCLK_ADC12
RCC_PERIPHCLK_ADC345
RCC_PERIPHCLK_FDCAN
RCC_PERIPHCLK_I2C1
RCC_PERIPHCLK_I2C2
RCC_PERIPHCLK_I2C3
RCC_PERIPHCLK_I2C4
RCC_PERIPHCLK_I2S
RCC_PERIPHCLK_LPTIM1
RCC_PERIPHCLK_LPUART1
RCC_PERIPHCLK_QSPI
RCC_PERIPHCLK_RNG
RCC_PERIPHCLK_RTC
RCC_PERIPHCLK_SAI1
RCC_PERIPHCLK_UART4
RCC_PERIPHCLK_UART5
RCC_PERIPHCLK_USART1
RCC_PERIPHCLK_USART2
RCC_PERIPHCLK_USART3
RCC_PERIPHCLK_USB
RCC_QSPICLKSOURCE_HSI
RCC_QSPICLKSOURCE_PLL
RCC_QSPICLKSOURCE_SYSCLK
RCC_RNGCLKSOURCE_HSI48
RCC_RNGCLKSOURCE_PLL
RCC_SAI1CLKSOURCE_EXT
RCC_SAI1CLKSOURCE_HSI
RCC_SAI1CLKSOURCE_PLL
RCC_SAI1CLKSOURCE_SYSCLK
RCC_UART4CLKSOURCE_HSI
RCC_UART4CLKSOURCE_LSE
RCC_UART4CLKSOURCE_PCLK1
RCC_UART4CLKSOURCE_SYSCLK
RCC_UART5CLKSOURCE_HSI
RCC_UART5CLKSOURCE_LSE
RCC_UART5CLKSOURCE_PCLK1
RCC_UART5CLKSOURCE_SYSCLK
RCC_USART1CLKSOURCE_HSI
RCC_USART1CLKSOURCE_LSE
RCC_USART1CLKSOURCE_PCLK2
RCC_USART1CLKSOURCE_SYSCLK
RCC_USART2CLKSOURCE_HSI
RCC_USART2CLKSOURCE_LSE
RCC_USART2CLKSOURCE_PCLK1
RCC_USART2CLKSOURCE_SYSCLK
RCC_USART3CLKSOURCE_HSI
RCC_USART3CLKSOURCE_LSE
RCC_USART3CLKSOURCE_PCLK1
RCC_USART3CLKSOURCE_SYSCLK
RCC_USBCLKSOURCE_HSI48
RCC_USBCLKSOURCE_PLL
HAL_RCCEx_CRS_ErrorCallback
HAL_RCCEx_CRS_ExpectedSyncCallback
HAL_RCCEx_CRS_IRQHandler
HAL_RCCEx_CRS_SyncOkCallback
HAL_RCCEx_CRS_SyncWarnCallback
HAL_RCCEx_CRSConfig
HAL_RCCEx_CRSGetSynchronizationInfo
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
HAL_RCCEx_CRSWaitSynchronization
HAL_RCCEx_DisableLSCO
HAL_RCCEx_DisableLSECSS
HAL_RCCEx_EnableLSCO
HAL_RCCEx_EnableLSECSS
HAL_RCCEx_EnableLSECSS_IT
HAL_RCCEx_GetPeriphCLKConfig
HAL_RCCEx_GetPeriphCLKFreq
HAL_RCCEx_LSECSS_Callback
HAL_RCCEx_LSECSS_IRQHandler
HAL_RCCEx_PeriphCLKConfig
stm32g4xx_hal_rng.c
HAL_RNG_DeInit
HAL_RNG_ErrorCallback
HAL_RNG_GenerateRandomNumber
HAL_RNG_GenerateRandomNumber_IT
HAL_RNG_GetError
HAL_RNG_GetState
HAL_RNG_Init
HAL_RNG_IRQHandler
HAL_RNG_MspDeInit
HAL_RNG_MspInit
HAL_RNG_ReadLastRandomNumber
HAL_RNG_ReadyDataCallback
HAL_RNG_RegisterCallback
HAL_RNG_RegisterReadyDataCallback
HAL_RNG_UnRegisterCallback
HAL_RNG_UnRegisterReadyDataCallback
stm32g4xx_hal_rng.h
__HAL_RNG_CLEAR_IT
__HAL_RNG_DISABLE
__HAL_RNG_DISABLE_IT
__HAL_RNG_ENABLE
__HAL_RNG_ENABLE_IT
__HAL_RNG_GET_FLAG
__HAL_RNG_GET_IT
__HAL_RNG_RESET_HANDLE_STATE
HAL_RNG_ERROR_BUSY
HAL_RNG_ERROR_CLOCK
HAL_RNG_ERROR_INVALID_CALLBACK
HAL_RNG_ERROR_NONE
HAL_RNG_ERROR_SEED
HAL_RNG_ERROR_TIMEOUT
IS_RNG_CED
IS_RNG_FLAG
IS_RNG_IT
RNG_CED_DISABLE
RNG_CED_ENABLE
RNG_FLAG_CECS
RNG_FLAG_DRDY
RNG_FLAG_SECS
RNG_IT_CEI
RNG_IT_DRDY
RNG_IT_SEI
pRNG_CallbackTypeDef
pRNG_ReadyDataCallbackTypeDef
RNG_HandleTypeDef
HAL_RNG_CallbackIDTypeDef
HAL_RNG_StateTypeDef
HAL_RNG_DeInit
HAL_RNG_ErrorCallback
HAL_RNG_GenerateRandomNumber
HAL_RNG_GenerateRandomNumber_IT
HAL_RNG_GetError
HAL_RNG_GetState
HAL_RNG_Init
HAL_RNG_IRQHandler
HAL_RNG_MspDeInit
HAL_RNG_MspInit
HAL_RNG_ReadLastRandomNumber
HAL_RNG_ReadyDataCallback
HAL_RNG_RegisterCallback
HAL_RNG_RegisterReadyDataCallback
HAL_RNG_UnRegisterCallback
HAL_RNG_UnRegisterReadyDataCallback
stm32g4xx_hal_rtc.c
HAL_RTC_AlarmIRQHandler
HAL_RTC_DeactivateAlarm
HAL_RTC_DeInit
HAL_RTC_DST_Add1Hour
HAL_RTC_DST_ClearStoreOperation
HAL_RTC_DST_ReadStoreOperation
HAL_RTC_DST_SetStoreOperation
HAL_RTC_DST_Sub1Hour
HAL_RTC_GetAlarm
HAL_RTC_GetDate
HAL_RTC_GetState
HAL_RTC_GetTime
HAL_RTC_Init
HAL_RTC_MspDeInit
HAL_RTC_MspInit
HAL_RTC_PollForAlarmAEvent
HAL_RTC_RegisterCallback
HAL_RTC_SetAlarm
HAL_RTC_SetAlarm_IT
HAL_RTC_SetDate
HAL_RTC_SetTime
HAL_RTC_UnRegisterCallback
HAL_RTC_WaitForSynchro
RTC_Bcd2ToByte
RTC_ByteToBcd2
RTC_EnterInitMode
RTC_ExitInitMode
stm32g4xx_hal_rtc.h
__HAL_RTC_ALARM_DISABLE_IT
__HAL_RTC_ALARM_ENABLE_IT
__HAL_RTC_ALARM_EXTI_CLEAR_IT
__HAL_RTC_ALARM_EXTI_DISABLE_EVENT
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_DISABLE_IT
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_EVENT
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_IT
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE
__HAL_RTC_ALARM_EXTI_FALLING_IT
__HAL_RTC_ALARM_EXTI_RISING_IT
__HAL_RTC_ALARM_GET_FLAG
__HAL_RTC_ALARM_GET_IT
__HAL_RTC_ALARM_GET_IT_SOURCE
__HAL_RTC_ALARMA_DISABLE
__HAL_RTC_ALARMA_ENABLE
__HAL_RTC_ALARMB_DISABLE
__HAL_RTC_ALARMB_ENABLE
__HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H
__HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H
__HAL_RTC_IS_CALENDAR_INITIALIZED
__HAL_RTC_RESET_HANDLE_STATE
__HAL_RTC_WRITEPROTECTION_DISABLE
__HAL_RTC_WRITEPROTECTION_ENABLE
IS_RTC_ALARM
IS_RTC_ALARM_DATE_WEEKDAY_DATE
IS_RTC_ALARM_DATE_WEEKDAY_SEL
IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY
IS_RTC_ALARM_MASK
IS_RTC_ALARM_SUB_SECOND_MASK
IS_RTC_ALARM_SUB_SECOND_VALUE
IS_RTC_ASYNCH_PREDIV
IS_RTC_DATE
IS_RTC_DAYLIGHT_SAVING
IS_RTC_FORMAT
IS_RTC_HOUR12
IS_RTC_HOUR24
IS_RTC_HOUR_FORMAT
IS_RTC_HOURFORMAT12
IS_RTC_MINUTES
IS_RTC_MONTH
IS_RTC_OUTPUT
IS_RTC_OUTPUT_POL
IS_RTC_OUTPUT_PULLUP
IS_RTC_OUTPUT_REMAP
IS_RTC_OUTPUT_TYPE
IS_RTC_SECONDS
IS_RTC_STORE_OPERATION
IS_RTC_SYNCH_PREDIV
IS_RTC_WEEKDAY
IS_RTC_YEAR
RTC_ALARM_A
RTC_ALARM_B
RTC_ALARMDATEWEEKDAYSEL_DATE
RTC_ALARMDATEWEEKDAYSEL_WEEKDAY
RTC_ALARMMASK_ALL
RTC_ALARMMASK_DATEWEEKDAY
RTC_ALARMMASK_HOURS
RTC_ALARMMASK_MINUTES
RTC_ALARMMASK_NONE
RTC_ALARMMASK_SECONDS
RTC_ALARMSUBSECONDMASK_ALL
RTC_ALARMSUBSECONDMASK_NONE
RTC_ALARMSUBSECONDMASK_SS14
RTC_ALARMSUBSECONDMASK_SS14_1
RTC_ALARMSUBSECONDMASK_SS14_10
RTC_ALARMSUBSECONDMASK_SS14_11
RTC_ALARMSUBSECONDMASK_SS14_12
RTC_ALARMSUBSECONDMASK_SS14_13
RTC_ALARMSUBSECONDMASK_SS14_2
RTC_ALARMSUBSECONDMASK_SS14_3
RTC_ALARMSUBSECONDMASK_SS14_4
RTC_ALARMSUBSECONDMASK_SS14_5
RTC_ALARMSUBSECONDMASK_SS14_6
RTC_ALARMSUBSECONDMASK_SS14_7
RTC_ALARMSUBSECONDMASK_SS14_8
RTC_ALARMSUBSECONDMASK_SS14_9
RTC_CLEAR_ALRAF
RTC_CLEAR_ALRBF
RTC_CLEAR_ITSF
RTC_CLEAR_TSF
RTC_CLEAR_TSOVF
RTC_CLEAR_WUTF
RTC_DAYLIGHTSAVING_ADD1H
RTC_DAYLIGHTSAVING_NONE
RTC_DAYLIGHTSAVING_SUB1H
RTC_DR_RESERVED_MASK
RTC_FLAG_ALRAF
RTC_FLAG_ALRAWF
RTC_FLAG_ALRBF
RTC_FLAG_ALRBWF
RTC_FLAG_INITF
RTC_FLAG_INITS
RTC_FLAG_ITSF
RTC_FLAG_MASK
RTC_FLAG_RECALPF
RTC_FLAG_RSF
RTC_FLAG_SHPF
RTC_FLAG_TSF
RTC_FLAG_TSOVF
RTC_FLAG_WUTF
RTC_FLAG_WUTWF
RTC_FORMAT_BCD
RTC_FORMAT_BIN
RTC_HOURFORMAT12_AM
RTC_HOURFORMAT12_PM
RTC_HOURFORMAT_12
RTC_HOURFORMAT_24
RTC_ICSR_RESERVED_MASK
RTC_INIT_MASK
RTC_IT_ALRA
RTC_IT_ALRB
RTC_IT_TS
RTC_IT_WUT
RTC_MONTH_APRIL
RTC_MONTH_AUGUST
RTC_MONTH_DECEMBER
RTC_MONTH_FEBRUARY
RTC_MONTH_JANUARY
RTC_MONTH_JULY
RTC_MONTH_JUNE
RTC_MONTH_MARCH
RTC_MONTH_MAY
RTC_MONTH_NOVEMBER
RTC_MONTH_OCTOBER
RTC_MONTH_SEPTEMBER
RTC_OUTPUT_ALARMA
RTC_OUTPUT_ALARMB
RTC_OUTPUT_DISABLE
RTC_OUTPUT_POLARITY_HIGH
RTC_OUTPUT_POLARITY_LOW
RTC_OUTPUT_PULLUP_NONE
RTC_OUTPUT_PULLUP_ON
RTC_OUTPUT_REMAP_NONE
RTC_OUTPUT_REMAP_POS1
RTC_OUTPUT_TAMPER
RTC_OUTPUT_TYPE_OPENDRAIN
RTC_OUTPUT_TYPE_PUSHPULL
RTC_OUTPUT_WAKEUP
RTC_RSF_MASK
RTC_STOREOPERATION_RESET
RTC_STOREOPERATION_SET
RTC_TIMEOUT_VALUE
RTC_TR_RESERVED_MASK
RTC_WEEKDAY_FRIDAY
RTC_WEEKDAY_MONDAY
RTC_WEEKDAY_SATURDAY
RTC_WEEKDAY_SUNDAY
RTC_WEEKDAY_THURSDAY
RTC_WEEKDAY_TUESDAY
RTC_WEEKDAY_WEDNESDAY
pRTC_CallbackTypeDef
RTC_HandleTypeDef
HAL_RTC_CallbackIDTypeDef
HAL_RTCStateTypeDef
HAL_RTC_AlarmAEventCallback
HAL_RTC_AlarmIRQHandler
HAL_RTC_DeactivateAlarm
HAL_RTC_DeInit
HAL_RTC_DST_Add1Hour
HAL_RTC_DST_ClearStoreOperation
HAL_RTC_DST_ReadStoreOperation
HAL_RTC_DST_SetStoreOperation
HAL_RTC_DST_Sub1Hour
HAL_RTC_GetAlarm
HAL_RTC_GetDate
HAL_RTC_GetState
HAL_RTC_GetTime
HAL_RTC_Init
HAL_RTC_MspDeInit
HAL_RTC_MspInit
HAL_RTC_PollForAlarmAEvent
HAL_RTC_RegisterCallback
HAL_RTC_SetAlarm
HAL_RTC_SetAlarm_IT
HAL_RTC_SetDate
HAL_RTC_SetTime
HAL_RTC_UnRegisterCallback
HAL_RTC_WaitForSynchro
RTC_Bcd2ToByte
RTC_ByteToBcd2
RTC_EnterInitMode
RTC_ExitInitMode
stm32g4xx_hal_rtc_ex.c
HAL_RTCEx_BKUPRead
HAL_RTCEx_BKUPWrite
HAL_RTCEx_DeactivateCalibrationOutPut
HAL_RTCEx_DeactivateInternalTamper
HAL_RTCEx_DeactivateInternalTimeStamp
HAL_RTCEx_DeactivateRefClock
HAL_RTCEx_DeactivateTamper
HAL_RTCEx_DeactivateTimeStamp
HAL_RTCEx_DeactivateWakeUpTimer
HAL_RTCEx_DisableBypassShadow
HAL_RTCEx_EnableBypassShadow
HAL_RTCEx_GetTimeStamp
HAL_RTCEx_GetWakeUpTimer
HAL_RTCEx_InternalTamper3EventCallback
HAL_RTCEx_InternalTamper4EventCallback
HAL_RTCEx_InternalTamper5EventCallback
HAL_RTCEx_InternalTamper6EventCallback
HAL_RTCEx_PollForAlarmBEvent
HAL_RTCEx_PollForInternalTamperEvent
HAL_RTCEx_PollForTamperEvent
HAL_RTCEx_PollForTimeStampEvent
HAL_RTCEx_PollForWakeUpTimerEvent
HAL_RTCEx_SetCalibrationOutPut
HAL_RTCEx_SetInternalTamper
HAL_RTCEx_SetInternalTamper_IT
HAL_RTCEx_SetInternalTimeStamp
HAL_RTCEx_SetRefClock
HAL_RTCEx_SetSmoothCalib
HAL_RTCEx_SetSynchroShift
HAL_RTCEx_SetTamper
HAL_RTCEx_SetTamper_IT
HAL_RTCEx_SetTimeStamp
HAL_RTCEx_SetTimeStamp_IT
HAL_RTCEx_SetWakeUpTimer
HAL_RTCEx_SetWakeUpTimer_IT
HAL_RTCEx_Tamper1EventCallback
HAL_RTCEx_Tamper2EventCallback
HAL_RTCEx_Tamper3EventCallback
HAL_RTCEx_TamperIRQHandler
HAL_RTCEx_TimeStampEventCallback
HAL_RTCEx_TimeStampIRQHandler
HAL_RTCEx_WakeUpTimerEventCallback
HAL_RTCEx_WakeUpTimerIRQHandler
stm32g4xx_hal_rtc_ex.h
__HAL_RTC_CALIBRATION_OUTPUT_ENABLE
__HAL_RTC_CLEAR_FLAG
__HAL_RTC_CLOCKREF_DETECTION_DISABLE
__HAL_RTC_CLOCKREF_DETECTION_ENABLE
__HAL_RTC_GET_FLAG
__HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG
__HAL_RTC_INTERNAL_TIMESTAMP_DISABLE
__HAL_RTC_INTERNAL_TIMESTAMP_ENABLE
__HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG
__HAL_RTC_SHIFT_GET_FLAG
__HAL_RTC_TAMPER_CLEAR_FLAG
__HAL_RTC_TAMPER_DISABLE
__HAL_RTC_TAMPER_DISABLE_IT
__HAL_RTC_TAMPER_ENABLE
__HAL_RTC_TAMPER_ENABLE_IT
__HAL_RTC_TAMPER_EXTI_CLEAR_IT
__HAL_RTC_TAMPER_EXTI_DISABLE_EVENT
__HAL_RTC_TAMPER_EXTI_DISABLE_IT
__HAL_RTC_TAMPER_EXTI_ENABLE_EVENT
__HAL_RTC_TAMPER_EXTI_ENABLE_IT
__HAL_RTC_TAMPER_EXTI_FALLING_IT
__HAL_RTC_TAMPER_EXTI_RISING_IT
__HAL_RTC_TAMPER_GET_FLAG
__HAL_RTC_TAMPER_GET_IT
__HAL_RTC_TAMPER_GET_IT_SOURCE
__HAL_RTC_TAMPOE_DISABLE
__HAL_RTC_TAMPOE_ENABLE
__HAL_RTC_TAMPTS_DISABLE
__HAL_RTC_TAMPTS_ENABLE
__HAL_RTC_TIMESTAMP_CLEAR_FLAG
__HAL_RTC_TIMESTAMP_DISABLE
__HAL_RTC_TIMESTAMP_DISABLE_IT
__HAL_RTC_TIMESTAMP_ENABLE
__HAL_RTC_TIMESTAMP_ENABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG
__HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT
__HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT
__HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT
__HAL_RTC_TIMESTAMP_EXTI_FALLING_IT
__HAL_RTC_TIMESTAMP_EXTI_RISING_IT
__HAL_RTC_TIMESTAMP_GET_FLAG
__HAL_RTC_TIMESTAMP_GET_IT
__HAL_RTC_TIMESTAMP_GET_IT_SOURCE
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG
__HAL_RTC_WAKEUPTIMER_DISABLE
__HAL_RTC_WAKEUPTIMER_DISABLE_IT
__HAL_RTC_WAKEUPTIMER_ENABLE
__HAL_RTC_WAKEUPTIMER_ENABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT
__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT
__HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT
__HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT
__HAL_RTC_WAKEUPTIMER_GET_FLAG
__HAL_RTC_WAKEUPTIMER_GET_IT
__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE
IS_RTC_BKP
IS_RTC_CALIB_OUTPUT
IS_RTC_INTERNAL_TAMPER
IS_RTC_LOW_POWER_CALIB
IS_RTC_SHIFT_ADD1S
IS_RTC_SHIFT_SUBFS
IS_RTC_SMOOTH_CALIB_MINUS
IS_RTC_SMOOTH_CALIB_PERIOD
IS_RTC_SMOOTH_CALIB_PLUS
IS_RTC_TAMPER
IS_RTC_TAMPER_ERASE_MODE
IS_RTC_TAMPER_FILTER
IS_RTC_TAMPER_MASKFLAG_STATE
IS_RTC_TAMPER_PRECHARGE_DURATION
IS_RTC_TAMPER_PULLUP_STATE
IS_RTC_TAMPER_SAMPLING_FREQ
IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT
IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
IS_RTC_TAMPER_TRIGGER
IS_RTC_TIMESTAMP_PIN
IS_RTC_TIMESTAMPONTAMPER_DETECTION
IS_RTC_WAKEUP_CLOCK
IS_RTC_WAKEUP_COUNTER
IS_TIMESTAMP_EDGE
RTC_BKP_DR0
RTC_BKP_DR1
RTC_BKP_DR10
RTC_BKP_DR11
RTC_BKP_DR12
RTC_BKP_DR13
RTC_BKP_DR14
RTC_BKP_DR15
RTC_BKP_DR16
RTC_BKP_DR17
RTC_BKP_DR18
RTC_BKP_DR19
RTC_BKP_DR2
RTC_BKP_DR20
RTC_BKP_DR21
RTC_BKP_DR22
RTC_BKP_DR23
RTC_BKP_DR24
RTC_BKP_DR25
RTC_BKP_DR26
RTC_BKP_DR27
RTC_BKP_DR28
RTC_BKP_DR29
RTC_BKP_DR3
RTC_BKP_DR30
RTC_BKP_DR31
RTC_BKP_DR4
RTC_BKP_DR5
RTC_BKP_DR6
RTC_BKP_DR7
RTC_BKP_DR8
RTC_BKP_DR9
RTC_BKP_NUMBER
RTC_CALIBOUTPUT_1HZ
RTC_CALIBOUTPUT_512HZ
RTC_EXTI_LINE_ALARM_EVENT
RTC_EXTI_LINE_TAMPER_EVENT
RTC_EXTI_LINE_TIMESTAMP_EVENT
RTC_EXTI_LINE_WAKEUPTIMER_EVENT
RTC_FLAG_INT_TAMP_1
RTC_FLAG_INT_TAMP_2
RTC_FLAG_INT_TAMP_3
RTC_FLAG_INT_TAMP_4
RTC_FLAG_INT_TAMP_5
RTC_FLAG_INT_TAMP_6
RTC_FLAG_INT_TAMP_7
RTC_FLAG_INT_TAMP_8
RTC_FLAG_INT_TAMP_ALL
RTC_FLAG_TAMP_1
RTC_FLAG_TAMP_2
RTC_FLAG_TAMP_3
RTC_FLAG_TAMP_ALL
RTC_INT_TAMPER_1
RTC_INT_TAMPER_2
RTC_INT_TAMPER_3
RTC_INT_TAMPER_4
RTC_INT_TAMPER_5
RTC_INT_TAMPER_6
RTC_INT_TAMPER_7
RTC_INT_TAMPER_8
RTC_INT_TAMPER_ALL
RTC_IT_INT_TAMP_1
RTC_IT_INT_TAMP_2
RTC_IT_INT_TAMP_3
RTC_IT_INT_TAMP_4
RTC_IT_INT_TAMP_5
RTC_IT_INT_TAMP_6
RTC_IT_INT_TAMP_7
RTC_IT_INT_TAMP_8
RTC_IT_INT_TAMP_ALL
RTC_IT_TAMP_1
RTC_IT_TAMP_2
RTC_IT_TAMP_3
RTC_IT_TAMP_ALL
RTC_SHIFTADD1S_RESET
RTC_SHIFTADD1S_SET
RTC_SMOOTHCALIB_PERIOD_16SEC
RTC_SMOOTHCALIB_PERIOD_32SEC
RTC_SMOOTHCALIB_PERIOD_8SEC
RTC_SMOOTHCALIB_PLUSPULSES_RESET
RTC_SMOOTHCALIB_PLUSPULSES_SET
RTC_TAMPER_1
RTC_TAMPER_2
RTC_TAMPER_3
RTC_TAMPER_ALL
RTC_TAMPER_ERASE_BACKUP_DISABLE
RTC_TAMPER_ERASE_BACKUP_ENABLE
RTC_TAMPER_PULLUP_DISABLE
RTC_TAMPER_PULLUP_ENABLE
RTC_TAMPERFILTER_2SAMPLE
RTC_TAMPERFILTER_4SAMPLE
RTC_TAMPERFILTER_8SAMPLE
RTC_TAMPERFILTER_DISABLE
RTC_TAMPERMASK_FLAG_DISABLE
RTC_TAMPERMASK_FLAG_ENABLE
RTC_TAMPERPRECHARGEDURATION_1RTCCLK
RTC_TAMPERPRECHARGEDURATION_2RTCCLK
RTC_TAMPERPRECHARGEDURATION_4RTCCLK
RTC_TAMPERPRECHARGEDURATION_8RTCCLK
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512
RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192
RTC_TAMPERTRIGGER_FALLINGEDGE
RTC_TAMPERTRIGGER_HIGHLEVEL
RTC_TAMPERTRIGGER_LOWLEVEL
RTC_TAMPERTRIGGER_RISINGEDGE
RTC_TIMESTAMPEDGE_FALLING
RTC_TIMESTAMPEDGE_RISING
RTC_TIMESTAMPONTAMPERDETECTION_DISABLE
RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
RTC_TIMESTAMPPIN_DEFAULT
RTC_WAKEUPCLOCK_CK_SPRE_16BITS
RTC_WAKEUPCLOCK_CK_SPRE_17BITS
RTC_WAKEUPCLOCK_RTCCLK_DIV16
RTC_WAKEUPCLOCK_RTCCLK_DIV2
RTC_WAKEUPCLOCK_RTCCLK_DIV4
RTC_WAKEUPCLOCK_RTCCLK_DIV8
HAL_RTCEx_AlarmBEventCallback
HAL_RTCEx_BKUPRead
HAL_RTCEx_BKUPWrite
HAL_RTCEx_DeactivateCalibrationOutPut
HAL_RTCEx_DeactivateInternalTamper
HAL_RTCEx_DeactivateInternalTimeStamp
HAL_RTCEx_DeactivateRefClock
HAL_RTCEx_DeactivateTamper
HAL_RTCEx_DeactivateTimeStamp
HAL_RTCEx_DeactivateWakeUpTimer
HAL_RTCEx_DisableBypassShadow
HAL_RTCEx_EnableBypassShadow
HAL_RTCEx_GetTimeStamp
HAL_RTCEx_GetWakeUpTimer
HAL_RTCEx_InternalTamper3EventCallback
HAL_RTCEx_InternalTamper4EventCallback
HAL_RTCEx_InternalTamper5EventCallback
HAL_RTCEx_InternalTamper6EventCallback
HAL_RTCEx_PollForAlarmBEvent
HAL_RTCEx_PollForInternalTamperEvent
HAL_RTCEx_PollForTamperEvent
HAL_RTCEx_PollForTimeStampEvent
HAL_RTCEx_PollForWakeUpTimerEvent
HAL_RTCEx_SetCalibrationOutPut
HAL_RTCEx_SetInternalTamper
HAL_RTCEx_SetInternalTamper_IT
HAL_RTCEx_SetInternalTimeStamp
HAL_RTCEx_SetRefClock
HAL_RTCEx_SetSmoothCalib
HAL_RTCEx_SetSynchroShift
HAL_RTCEx_SetTamper
HAL_RTCEx_SetTamper_IT
HAL_RTCEx_SetTimeStamp
HAL_RTCEx_SetTimeStamp_IT
HAL_RTCEx_SetWakeUpTimer
HAL_RTCEx_SetWakeUpTimer_IT
HAL_RTCEx_Tamper1EventCallback
HAL_RTCEx_Tamper2EventCallback
HAL_RTCEx_Tamper3EventCallback
HAL_RTCEx_TamperIRQHandler
HAL_RTCEx_TimeStampEventCallback
HAL_RTCEx_TimeStampIRQHandler
HAL_RTCEx_WakeUpTimerEventCallback
HAL_RTCEx_WakeUpTimerIRQHandler
stm32g4xx_hal_sai.c
SAI_DEFAULT_TIMEOUT
SAI_LONG_TIMEOUT
SAI_SPDIF_FRAME_LENGTH
SAI_ModeTypedef
HAL_SAI_Abort
HAL_SAI_DeInit
HAL_SAI_DisableRxMuteMode
HAL_SAI_DisableTxMuteMode
HAL_SAI_DMAPause
HAL_SAI_DMAResume
HAL_SAI_DMAStop
HAL_SAI_EnableRxMuteMode
HAL_SAI_EnableTxMuteMode
HAL_SAI_ErrorCallback
HAL_SAI_GetError
HAL_SAI_GetState
HAL_SAI_Init
HAL_SAI_InitProtocol
HAL_SAI_IRQHandler
HAL_SAI_MspDeInit
HAL_SAI_MspInit
HAL_SAI_Receive
HAL_SAI_Receive_DMA
HAL_SAI_Receive_IT
HAL_SAI_RegisterCallback
HAL_SAI_RxCpltCallback
HAL_SAI_RxHalfCpltCallback
HAL_SAI_Transmit
HAL_SAI_Transmit_DMA
HAL_SAI_Transmit_IT
HAL_SAI_TxCpltCallback
HAL_SAI_TxHalfCpltCallback
HAL_SAI_UnRegisterCallback
SAI_Disable
SAI_DMAAbort
SAI_DMAError
SAI_DMARxCplt
SAI_DMARxHalfCplt
SAI_DMATxCplt
SAI_DMATxHalfCplt
SAI_FillFifo
SAI_InitI2S
SAI_InitPCM
SAI_InterruptFlag
SAI_Receive_IT16Bit
SAI_Receive_IT32Bit
SAI_Receive_IT8Bit
SAI_Transmit_IT16Bit
SAI_Transmit_IT32Bit
SAI_Transmit_IT8Bit
stm32g4xx_hal_sai.h
__HAL_SAI_DISABLE
__HAL_SAI_DISABLE_IT
__HAL_SAI_ENABLE
__HAL_SAI_ENABLE_IT
__HAL_SAI_GET_FLAG
__HAL_SAI_GET_IT_SOURCE
__HAL_SAI_RESET_HANDLE_STATE
HAL_SAI_ERROR_AFSDET
HAL_SAI_ERROR_CNREADY
HAL_SAI_ERROR_DMA
HAL_SAI_ERROR_INVALID_CALLBACK
HAL_SAI_ERROR_LFSDET
HAL_SAI_ERROR_NONE
HAL_SAI_ERROR_OVR
HAL_SAI_ERROR_TIMEOUT
HAL_SAI_ERROR_UDR
HAL_SAI_ERROR_WCKCFG
IS_SAI_AUDIO_FREQUENCY
IS_SAI_BLOCK_ACTIVE_FRAME
IS_SAI_BLOCK_CLOCK_STROBING
IS_SAI_BLOCK_COMPANDING_MODE
IS_SAI_BLOCK_DATASIZE
IS_SAI_BLOCK_FIFO_THRESHOLD
IS_SAI_BLOCK_FIRST_BIT
IS_SAI_BLOCK_FIRSTBIT_OFFSET
IS_SAI_BLOCK_FRAME_LENGTH
IS_SAI_BLOCK_FS_DEFINITION
IS_SAI_BLOCK_FS_OFFSET
IS_SAI_BLOCK_FS_POLARITY
IS_SAI_BLOCK_MASTER_DIVIDER
IS_SAI_BLOCK_MCK_OUTPUT
IS_SAI_BLOCK_MCK_OVERSAMPLING
IS_SAI_BLOCK_MODE
IS_SAI_BLOCK_MUTE_COUNTER
IS_SAI_BLOCK_MUTE_VALUE
IS_SAI_BLOCK_NODIVIDER
IS_SAI_BLOCK_OUTPUT_DRIVE
IS_SAI_BLOCK_PROTOCOL
IS_SAI_BLOCK_SLOT_NUMBER
IS_SAI_BLOCK_SLOT_SIZE
IS_SAI_BLOCK_SYNCEXT
IS_SAI_BLOCK_SYNCHRO
IS_SAI_BLOCK_TRISTATE_MANAGEMENT
IS_SAI_MONO_STEREO_MODE
IS_SAI_PDM_CLOCK_ENABLE
IS_SAI_PDM_MIC_PAIRS_NUMBER
IS_SAI_PROTOCOL_DATASIZE
IS_SAI_SLOT_ACTIVE
IS_SAI_SUPPORTED_PROTOCOL
SAI_AC97_PROTOCOL
SAI_ALAW_1CPL_COMPANDING
SAI_ALAW_2CPL_COMPANDING
SAI_ASYNCHRONOUS
SAI_AUDIO_FREQUENCY_11K
SAI_AUDIO_FREQUENCY_16K
SAI_AUDIO_FREQUENCY_192K
SAI_AUDIO_FREQUENCY_22K
SAI_AUDIO_FREQUENCY_32K
SAI_AUDIO_FREQUENCY_44K
SAI_AUDIO_FREQUENCY_48K
SAI_AUDIO_FREQUENCY_8K
SAI_AUDIO_FREQUENCY_96K
SAI_AUDIO_FREQUENCY_MCKDIV
SAI_CLOCKSTROBING_FALLINGEDGE
SAI_CLOCKSTROBING_RISINGEDGE
SAI_DATASIZE_10
SAI_DATASIZE_16
SAI_DATASIZE_20
SAI_DATASIZE_24
SAI_DATASIZE_32
SAI_DATASIZE_8
SAI_FIFOSTATUS_1QUARTERFULL
SAI_FIFOSTATUS_3QUARTERFULL
SAI_FIFOSTATUS_EMPTY
SAI_FIFOSTATUS_FULL
SAI_FIFOSTATUS_HALFFULL
SAI_FIFOSTATUS_LESS1QUARTERFULL
SAI_FIFOTHRESHOLD_1QF
SAI_FIFOTHRESHOLD_3QF
SAI_FIFOTHRESHOLD_EMPTY
SAI_FIFOTHRESHOLD_FULL
SAI_FIFOTHRESHOLD_HF
SAI_FIRSTBIT_LSB
SAI_FIRSTBIT_MSB
SAI_FLAG_AFSDET
SAI_FLAG_CNRDY
SAI_FLAG_FREQ
SAI_FLAG_LFSDET
SAI_FLAG_MUTEDET
SAI_FLAG_OVRUDR
SAI_FLAG_WCKCFG
SAI_FREE_PROTOCOL
SAI_FS_ACTIVE_HIGH
SAI_FS_ACTIVE_LOW
SAI_FS_BEFOREFIRSTBIT
SAI_FS_CHANNEL_IDENTIFICATION
SAI_FS_FIRSTBIT
SAI_FS_STARTFRAME
SAI_I2S_LSBJUSTIFIED
SAI_I2S_MSBJUSTIFIED
SAI_I2S_STANDARD
SAI_IT_AFSDET
SAI_IT_CNRDY
SAI_IT_FREQ
SAI_IT_LFSDET
SAI_IT_MUTEDET
SAI_IT_OVRUDR
SAI_IT_WCKCFG
SAI_LAST_SENT_VALUE
SAI_MASTERDIVIDER_DISABLE
SAI_MASTERDIVIDER_ENABLE
SAI_MCK_OUTPUT_DISABLE
SAI_MCK_OUTPUT_ENABLE
SAI_MCK_OVERSAMPLING_DISABLE
SAI_MCK_OVERSAMPLING_ENABLE
SAI_MODEMASTER_RX
SAI_MODEMASTER_TX
SAI_MODESLAVE_RX
SAI_MODESLAVE_TX
SAI_MONOMODE
SAI_NOCOMPANDING
SAI_OUTPUT_NOTRELEASED
SAI_OUTPUT_RELEASED
SAI_OUTPUTDRIVE_DISABLE
SAI_OUTPUTDRIVE_ENABLE
SAI_PCM_LONG
SAI_PCM_SHORT
SAI_PDM_CLOCK1_ENABLE
SAI_PDM_CLOCK2_ENABLE
SAI_PROTOCOL_DATASIZE_16BIT
SAI_PROTOCOL_DATASIZE_16BITEXTENDED
SAI_PROTOCOL_DATASIZE_24BIT
SAI_PROTOCOL_DATASIZE_32BIT
SAI_SLOT_NOTACTIVE
SAI_SLOTACTIVE_0
SAI_SLOTACTIVE_1
SAI_SLOTACTIVE_10
SAI_SLOTACTIVE_11
SAI_SLOTACTIVE_12
SAI_SLOTACTIVE_13
SAI_SLOTACTIVE_14
SAI_SLOTACTIVE_15
SAI_SLOTACTIVE_2
SAI_SLOTACTIVE_3
SAI_SLOTACTIVE_4
SAI_SLOTACTIVE_5
SAI_SLOTACTIVE_6
SAI_SLOTACTIVE_7
SAI_SLOTACTIVE_8
SAI_SLOTACTIVE_9
SAI_SLOTACTIVE_ALL
SAI_SLOTSIZE_16B
SAI_SLOTSIZE_32B
SAI_SLOTSIZE_DATASIZE
SAI_SPDIF_PROTOCOL
SAI_STEREOMODE
SAI_SYNCEXT_DISABLE
SAI_SYNCHRONOUS
SAI_ULAW_1CPL_COMPANDING
SAI_ULAW_2CPL_COMPANDING
SAI_ZERO_VALUE
pSAI_CallbackTypeDef
SAI_HandleTypeDef
SAIcallback
HAL_SAI_CallbackIDTypeDef
HAL_SAI_StateTypeDef
HAL_SAI_Abort
HAL_SAI_DeInit
HAL_SAI_DisableRxMuteMode
HAL_SAI_DisableTxMuteMode
HAL_SAI_DMAPause
HAL_SAI_DMAResume
HAL_SAI_DMAStop
HAL_SAI_EnableRxMuteMode
HAL_SAI_EnableTxMuteMode
HAL_SAI_ErrorCallback
HAL_SAI_GetError
HAL_SAI_GetState
HAL_SAI_Init
HAL_SAI_InitProtocol
HAL_SAI_IRQHandler
HAL_SAI_MspDeInit
HAL_SAI_MspInit
HAL_SAI_Receive
HAL_SAI_Receive_DMA
HAL_SAI_Receive_IT
HAL_SAI_RegisterCallback
HAL_SAI_RxCpltCallback
HAL_SAI_RxHalfCpltCallback
HAL_SAI_Transmit
HAL_SAI_Transmit_DMA
HAL_SAI_Transmit_IT
HAL_SAI_TxCpltCallback
HAL_SAI_TxHalfCpltCallback
HAL_SAI_UnRegisterCallback
stm32g4xx_hal_sai_ex.c
SAI_PDM_DELAY_OFFSET
SAI_PDM_RIGHT_DELAY_OFFSET
HAL_SAIEx_ConfigPdmMicDelay
stm32g4xx_hal_sai_ex.h
HAL_SAIEx_ConfigPdmMicDelay
stm32g4xx_hal_smartcard.c
USART_BRR_MAX
USART_BRR_MIN
USART_CR1_FIELDS
USART_CR2_CLK_FIELDS
USART_CR2_FIELDS
USART_CR3_FIELDS
HAL_SMARTCARD_Abort
HAL_SMARTCARD_Abort_IT
HAL_SMARTCARD_AbortCpltCallback
HAL_SMARTCARD_AbortReceive
HAL_SMARTCARD_AbortReceive_IT
HAL_SMARTCARD_AbortReceiveCpltCallback
HAL_SMARTCARD_AbortTransmit
HAL_SMARTCARD_AbortTransmit_IT
HAL_SMARTCARD_AbortTransmitCpltCallback
HAL_SMARTCARD_DeInit
HAL_SMARTCARD_ErrorCallback
HAL_SMARTCARD_GetError
HAL_SMARTCARD_GetState
HAL_SMARTCARD_Init
HAL_SMARTCARD_IRQHandler
HAL_SMARTCARD_MspDeInit
HAL_SMARTCARD_MspInit
HAL_SMARTCARD_Receive
HAL_SMARTCARD_Receive_DMA
HAL_SMARTCARD_Receive_IT
HAL_SMARTCARD_RegisterCallback
HAL_SMARTCARD_RxCpltCallback
HAL_SMARTCARD_Transmit
HAL_SMARTCARD_Transmit_DMA
HAL_SMARTCARD_Transmit_IT
HAL_SMARTCARD_TxCpltCallback
HAL_SMARTCARD_UnRegisterCallback
SMARTCARD_AdvFeatureConfig
SMARTCARD_CheckIdleState
SMARTCARD_DMAAbortOnError
SMARTCARD_DMAError
SMARTCARD_DMAReceiveCplt
SMARTCARD_DMARxAbortCallback
SMARTCARD_DMARxOnlyAbortCallback
SMARTCARD_DMATransmitCplt
SMARTCARD_DMATxAbortCallback
SMARTCARD_DMATxOnlyAbortCallback
SMARTCARD_EndRxTransfer
SMARTCARD_EndTransmit_IT
SMARTCARD_EndTxTransfer
SMARTCARD_InitCallbacksToDefault
SMARTCARD_RxISR
SMARTCARD_RxISR_FIFOEN
SMARTCARD_SetConfig
SMARTCARD_TxISR
SMARTCARD_TxISR_FIFOEN
SMARTCARD_WaitOnFlagUntilTimeout
stm32g4xx_hal_smartcard.h
__HAL_SMARTCARD_CLEAR_FLAG
__HAL_SMARTCARD_CLEAR_IDLEFLAG
__HAL_SMARTCARD_CLEAR_IT
__HAL_SMARTCARD_CLEAR_NEFLAG
__HAL_SMARTCARD_CLEAR_OREFLAG
__HAL_SMARTCARD_CLEAR_PEFLAG
__HAL_SMARTCARD_DISABLE
__HAL_SMARTCARD_DISABLE_IT
__HAL_SMARTCARD_ENABLE
__HAL_SMARTCARD_ENABLE_IT
__HAL_SMARTCARD_FLUSH_DRREGISTER
__HAL_SMARTCARD_GET_FLAG
__HAL_SMARTCARD_GET_IT
__HAL_SMARTCARD_GET_IT_SOURCE
__HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE
__HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE
__HAL_SMARTCARD_RESET_HANDLE_STATE
__HAL_SMARTCARD_SEND_REQ
HAL_SMARTCARD_ERROR_DMA
HAL_SMARTCARD_ERROR_FE
HAL_SMARTCARD_ERROR_INVALID_CALLBACK
HAL_SMARTCARD_ERROR_NE
HAL_SMARTCARD_ERROR_NONE
HAL_SMARTCARD_ERROR_ORE
HAL_SMARTCARD_ERROR_PE
HAL_SMARTCARD_ERROR_RTO
HAL_SMARTCARD_STATE_BUSY
HAL_SMARTCARD_STATE_BUSY_RX
HAL_SMARTCARD_STATE_BUSY_TX
HAL_SMARTCARD_STATE_BUSY_TX_RX
HAL_SMARTCARD_STATE_ERROR
HAL_SMARTCARD_STATE_READY
HAL_SMARTCARD_STATE_RESET
HAL_SMARTCARD_STATE_TIMEOUT
IS_SMARTCARD_ADVFEATURE_DATAINV
IS_SMARTCARD_ADVFEATURE_DMAONRXERROR
IS_SMARTCARD_ADVFEATURE_INIT
IS_SMARTCARD_ADVFEATURE_MSBFIRST
IS_SMARTCARD_ADVFEATURE_RXINV
IS_SMARTCARD_ADVFEATURE_SWAP
IS_SMARTCARD_ADVFEATURE_TXINV
IS_SMARTCARD_AUTORETRY_COUNT
IS_SMARTCARD_BAUDRATE
IS_SMARTCARD_BLOCKLENGTH
IS_SMARTCARD_CLOCKPRESCALER
IS_SMARTCARD_LASTBIT
IS_SMARTCARD_MODE
IS_SMARTCARD_NACK
IS_SMARTCARD_ONE_BIT_SAMPLE
IS_SMARTCARD_OVERRUN
IS_SMARTCARD_PARITY
IS_SMARTCARD_PHASE
IS_SMARTCARD_POLARITY
IS_SMARTCARD_REQUEST_PARAMETER
IS_SMARTCARD_STOPBITS
IS_SMARTCARD_TIMEOUT
IS_SMARTCARD_TIMEOUT_VALUE
IS_SMARTCARD_WORD_LENGTH
SMARTCARD_ADVFEATURE_DATAINV_DISABLE
SMARTCARD_ADVFEATURE_DATAINV_ENABLE
SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR
SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR
SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE
SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE
SMARTCARD_ADVFEATURE_OVERRUN_DISABLE
SMARTCARD_ADVFEATURE_OVERRUN_ENABLE
SMARTCARD_ADVFEATURE_RXINV_DISABLE
SMARTCARD_ADVFEATURE_RXINV_ENABLE
SMARTCARD_ADVFEATURE_SWAP_DISABLE
SMARTCARD_ADVFEATURE_SWAP_ENABLE
SMARTCARD_ADVFEATURE_TXINV_DISABLE
SMARTCARD_ADVFEATURE_TXINV_ENABLE
SMARTCARD_CR_MASK
SMARTCARD_CR_POS
SMARTCARD_GETCLOCKSOURCE
SMARTCARD_ISR_MASK
SMARTCARD_ISR_POS
SMARTCARD_IT_MASK
SMARTCARD_LASTBIT_DISABLE
SMARTCARD_LASTBIT_ENABLE
SMARTCARD_MODE_RX
SMARTCARD_MODE_TX
SMARTCARD_MODE_TX_RX
SMARTCARD_NACK_DISABLE
SMARTCARD_NACK_ENABLE
SMARTCARD_ONE_BIT_SAMPLE_DISABLE
SMARTCARD_ONE_BIT_SAMPLE_ENABLE
SMARTCARD_PARITY_EVEN
SMARTCARD_PARITY_ODD
SMARTCARD_PHASE_1EDGE
SMARTCARD_PHASE_2EDGE
SMARTCARD_POLARITY_HIGH
SMARTCARD_POLARITY_LOW
SMARTCARD_PRESCALER_DIV1
SMARTCARD_PRESCALER_DIV10
SMARTCARD_PRESCALER_DIV12
SMARTCARD_PRESCALER_DIV128
SMARTCARD_PRESCALER_DIV16
SMARTCARD_PRESCALER_DIV2
SMARTCARD_PRESCALER_DIV256
SMARTCARD_PRESCALER_DIV32
SMARTCARD_PRESCALER_DIV4
SMARTCARD_PRESCALER_DIV6
SMARTCARD_PRESCALER_DIV64
SMARTCARD_PRESCALER_DIV8
SMARTCARD_RXDATA_FLUSH_REQUEST
SMARTCARD_STOPBITS_0_5
SMARTCARD_STOPBITS_1_5
SMARTCARD_TIMEOUT_DISABLE
SMARTCARD_TIMEOUT_ENABLE
SMARTCARD_TXDATA_FLUSH_REQUEST
SMARTCARD_WORDLENGTH_9B
HAL_SMARTCARD_StateTypeDef
pSMARTCARD_CallbackTypeDef
SMARTCARD_HandleTypeDef
HAL_SMARTCARD_CallbackIDTypeDef
SMARTCARD_ClockSourceTypeDef
HAL_SMARTCARD_Abort
HAL_SMARTCARD_Abort_IT
HAL_SMARTCARD_AbortCpltCallback
HAL_SMARTCARD_AbortReceive
HAL_SMARTCARD_AbortReceive_IT
HAL_SMARTCARD_AbortReceiveCpltCallback
HAL_SMARTCARD_AbortTransmit
HAL_SMARTCARD_AbortTransmit_IT
HAL_SMARTCARD_AbortTransmitCpltCallback
HAL_SMARTCARD_DeInit
HAL_SMARTCARD_ErrorCallback
HAL_SMARTCARD_GetError
HAL_SMARTCARD_GetState
HAL_SMARTCARD_Init
HAL_SMARTCARD_IRQHandler
HAL_SMARTCARD_MspDeInit
HAL_SMARTCARD_MspInit
HAL_SMARTCARD_Receive
HAL_SMARTCARD_Receive_DMA
HAL_SMARTCARD_Receive_IT
HAL_SMARTCARD_RegisterCallback
HAL_SMARTCARD_RxCpltCallback
HAL_SMARTCARD_Transmit
HAL_SMARTCARD_Transmit_DMA
HAL_SMARTCARD_Transmit_IT
HAL_SMARTCARD_TxCpltCallback
HAL_SMARTCARD_UnRegisterCallback
stm32g4xx_hal_smartcard_ex.c
TX_FIFO_DEPTH
HAL_SMARTCARDEx_BlockLength_Config
HAL_SMARTCARDEx_DisableFifoMode
HAL_SMARTCARDEx_DisableReceiverTimeOut
HAL_SMARTCARDEx_EnableFifoMode
HAL_SMARTCARDEx_EnableReceiverTimeOut
HAL_SMARTCARDEx_RxFifoFullCallback
HAL_SMARTCARDEx_SetRxFifoThreshold
HAL_SMARTCARDEx_SetTxFifoThreshold
HAL_SMARTCARDEx_TimeOut_Config
HAL_SMARTCARDEx_TxFifoEmptyCallback
SMARTCARDEx_SetNbDataToProcess
stm32g4xx_hal_smartcard_ex.h
IS_SMARTCARD_RXFIFO_THRESHOLD
IS_SMARTCARD_TRANSMISSION_COMPLETION
IS_SMARTCARD_TXFIFO_THRESHOLD
SMARTCARD_ADVFEATURE_DATAINVERT_INIT
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT
SMARTCARD_ADVFEATURE_MSBFIRST_INIT
SMARTCARD_ADVFEATURE_NO_INIT
SMARTCARD_ADVFEATURE_RXINVERT_INIT
SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT
SMARTCARD_ADVFEATURE_SWAP_INIT
SMARTCARD_ADVFEATURE_TXCOMPLETION
SMARTCARD_ADVFEATURE_TXINVERT_INIT
SMARTCARD_CLEAR_EOBF
SMARTCARD_CLEAR_FEF
SMARTCARD_CLEAR_IDLEF
SMARTCARD_CLEAR_NEF
SMARTCARD_CLEAR_OREF
SMARTCARD_CLEAR_PEF
SMARTCARD_CLEAR_RTOF
SMARTCARD_CLEAR_TCBGTF
SMARTCARD_CLEAR_TCF
SMARTCARD_CLEAR_TXFECF
SMARTCARD_FIFOMODE_DISABLE
SMARTCARD_FIFOMODE_ENABLE
SMARTCARD_FLAG_BUSY
SMARTCARD_FLAG_EOBF
SMARTCARD_FLAG_FE
SMARTCARD_FLAG_IDLE
SMARTCARD_FLAG_NE
SMARTCARD_FLAG_ORE
SMARTCARD_FLAG_PE
SMARTCARD_FLAG_REACK
SMARTCARD_FLAG_RTOF
SMARTCARD_FLAG_RXFF
SMARTCARD_FLAG_RXFNE
SMARTCARD_FLAG_RXFT
SMARTCARD_FLAG_RXNE
SMARTCARD_FLAG_TC
SMARTCARD_FLAG_TCBGT
SMARTCARD_FLAG_TEACK
SMARTCARD_FLAG_TXE
SMARTCARD_FLAG_TXFE
SMARTCARD_FLAG_TXFNF
SMARTCARD_FLAG_TXFT
SMARTCARD_IT_EOB
SMARTCARD_IT_ERR
SMARTCARD_IT_FE
SMARTCARD_IT_IDLE
SMARTCARD_IT_NE
SMARTCARD_IT_ORE
SMARTCARD_IT_PE
SMARTCARD_IT_RTO
SMARTCARD_IT_RXFF
SMARTCARD_IT_RXFNE
SMARTCARD_IT_RXFT
SMARTCARD_IT_RXNE
SMARTCARD_IT_TC
SMARTCARD_IT_TCBGT
SMARTCARD_IT_TXE
SMARTCARD_IT_TXFE
SMARTCARD_IT_TXFNF
SMARTCARD_IT_TXFT
SMARTCARD_RXFIFO_THRESHOLD_1_2
SMARTCARD_RXFIFO_THRESHOLD_1_4
SMARTCARD_RXFIFO_THRESHOLD_1_8
SMARTCARD_RXFIFO_THRESHOLD_3_4
SMARTCARD_RXFIFO_THRESHOLD_7_8
SMARTCARD_RXFIFO_THRESHOLD_8_8
SMARTCARD_TC
SMARTCARD_TCBGT
SMARTCARD_TRANSMISSION_COMPLETION_FLAG
SMARTCARD_TRANSMISSION_COMPLETION_SETTING
SMARTCARD_TXFIFO_THRESHOLD_1_2
SMARTCARD_TXFIFO_THRESHOLD_1_4
SMARTCARD_TXFIFO_THRESHOLD_1_8
SMARTCARD_TXFIFO_THRESHOLD_3_4
SMARTCARD_TXFIFO_THRESHOLD_7_8
SMARTCARD_TXFIFO_THRESHOLD_8_8
HAL_SMARTCARDEx_BlockLength_Config
HAL_SMARTCARDEx_DisableFifoMode
HAL_SMARTCARDEx_DisableReceiverTimeOut
HAL_SMARTCARDEx_EnableFifoMode
HAL_SMARTCARDEx_EnableReceiverTimeOut
HAL_SMARTCARDEx_RxFifoFullCallback
HAL_SMARTCARDEx_SetRxFifoThreshold
HAL_SMARTCARDEx_SetTxFifoThreshold
HAL_SMARTCARDEx_TimeOut_Config
HAL_SMARTCARDEx_TxFifoEmptyCallback
stm32g4xx_hal_smbus.c
HAL_TIMEOUT_BUSY
HAL_TIMEOUT_DIR
HAL_TIMEOUT_RXNE
HAL_TIMEOUT_STOPF
HAL_TIMEOUT_TC
HAL_TIMEOUT_TCR
HAL_TIMEOUT_TXIS
MAX_NBYTE_SIZE
TIMING_CLEAR_MASK
HAL_SMBUS_AddrCallback
HAL_SMBUS_ConfigAnalogFilter
HAL_SMBUS_ConfigDigitalFilter
HAL_SMBUS_DeInit
HAL_SMBUS_DisableAlert_IT
HAL_SMBUS_DisableListen_IT
HAL_SMBUS_EnableAlert_IT
HAL_SMBUS_EnableListen_IT
HAL_SMBUS_ER_IRQHandler
HAL_SMBUS_ErrorCallback
HAL_SMBUS_EV_IRQHandler
HAL_SMBUS_GetError
HAL_SMBUS_GetState
HAL_SMBUS_Init
HAL_SMBUS_IsDeviceReady
HAL_SMBUS_ListenCpltCallback
HAL_SMBUS_Master_Abort_IT
HAL_SMBUS_Master_Receive_IT
HAL_SMBUS_Master_Transmit_IT
HAL_SMBUS_MasterRxCpltCallback
HAL_SMBUS_MasterTxCpltCallback
HAL_SMBUS_MspDeInit
HAL_SMBUS_MspInit
HAL_SMBUS_RegisterAddrCallback
HAL_SMBUS_RegisterCallback
HAL_SMBUS_Slave_Receive_IT
HAL_SMBUS_Slave_Transmit_IT
HAL_SMBUS_SlaveRxCpltCallback
HAL_SMBUS_SlaveTxCpltCallback
HAL_SMBUS_UnRegisterAddrCallback
HAL_SMBUS_UnRegisterCallback
SMBUS_ConvertOtherXferOptions
SMBUS_Disable_IRQ
SMBUS_Enable_IRQ
SMBUS_Flush_TXDR
SMBUS_ITErrorHandler
SMBUS_Master_ISR
SMBUS_Slave_ISR
SMBUS_TransferConfig
SMBUS_WaitOnFlagUntilTimeout
stm32g4xx_hal_smbus.h
__HAL_SMBUS_DISABLE
__HAL_SMBUS_DISABLE_IT
__HAL_SMBUS_ENABLE
__HAL_SMBUS_ENABLE_IT
__HAL_SMBUS_GENERATE_NACK
__HAL_SMBUS_GET_FLAG
__HAL_SMBUS_GET_IT_SOURCE
__HAL_SMBUS_RESET_HANDLE_STATE
HAL_SMBUS_ERROR_ACKF
HAL_SMBUS_ERROR_ALERT
HAL_SMBUS_ERROR_ARLO
HAL_SMBUS_ERROR_BERR
HAL_SMBUS_ERROR_BUSTIMEOUT
HAL_SMBUS_ERROR_HALTIMEOUT
HAL_SMBUS_ERROR_INVALID_CALLBACK
HAL_SMBUS_ERROR_INVALID_PARAM
HAL_SMBUS_ERROR_NONE
HAL_SMBUS_ERROR_OVR
HAL_SMBUS_ERROR_PECERR
HAL_SMBUS_STATE_BUSY
HAL_SMBUS_STATE_LISTEN
HAL_SMBUS_STATE_MASTER_BUSY_RX
HAL_SMBUS_STATE_MASTER_BUSY_TX
HAL_SMBUS_STATE_READY
HAL_SMBUS_STATE_RESET
HAL_SMBUS_STATE_SLAVE_BUSY_RX
HAL_SMBUS_STATE_SLAVE_BUSY_TX
IS_SMBUS_ADDRESSING_MODE
IS_SMBUS_ANALOG_FILTER
IS_SMBUS_DIGITAL_FILTER
IS_SMBUS_DUAL_ADDRESS
IS_SMBUS_GENERAL_CALL
IS_SMBUS_NO_STRETCH
IS_SMBUS_OWN_ADDRESS1
IS_SMBUS_OWN_ADDRESS2
IS_SMBUS_OWN_ADDRESS2_MASK
IS_SMBUS_PEC
IS_SMBUS_PERIPHERAL_MODE
IS_SMBUS_TRANSFER_MODE
IS_SMBUS_TRANSFER_OPTIONS_REQUEST
IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST
IS_SMBUS_TRANSFER_REQUEST
SMBUS_ADDRESSINGMODE_10BIT
SMBUS_ADDRESSINGMODE_7BIT
SMBUS_ANALOGFILTER_DISABLE
SMBUS_ANALOGFILTER_ENABLE
SMBUS_AUTOEND_MODE
SMBUS_CHECK_FLAG
SMBUS_CHECK_IT_SOURCE
SMBUS_DUALADDRESS_DISABLE
SMBUS_DUALADDRESS_ENABLE
SMBUS_FIRST_AND_LAST_FRAME_NO_PEC
SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC
SMBUS_FIRST_FRAME
SMBUS_FIRST_FRAME_WITH_PEC
SMBUS_FLAG_ADDR
SMBUS_FLAG_AF
SMBUS_FLAG_ALERT
SMBUS_FLAG_ARLO
SMBUS_FLAG_BERR
SMBUS_FLAG_BUSY
SMBUS_FLAG_DIR
SMBUS_FLAG_MASK
SMBUS_FLAG_OVR
SMBUS_FLAG_PECERR
SMBUS_FLAG_RXNE
SMBUS_FLAG_STOPF
SMBUS_FLAG_TC
SMBUS_FLAG_TCR
SMBUS_FLAG_TIMEOUT
SMBUS_FLAG_TXE
SMBUS_FLAG_TXIS
SMBUS_GENERALCALL_DISABLE
SMBUS_GENERALCALL_ENABLE
SMBUS_GENERATE_START
SMBUS_GENERATE_START_READ
SMBUS_GENERATE_START_WRITE
SMBUS_GENERATE_STOP
SMBUS_GET_ADDR_MATCH
SMBUS_GET_ALERT_ENABLED
SMBUS_GET_DIR
SMBUS_GET_PEC_MODE
SMBUS_GET_STOP_MODE
SMBUS_IT_ADDR
SMBUS_IT_ADDRI
SMBUS_IT_ALERT
SMBUS_IT_ERRI
SMBUS_IT_NACKI
SMBUS_IT_RX
SMBUS_IT_RXI
SMBUS_IT_STOPI
SMBUS_IT_TCI
SMBUS_IT_TX
SMBUS_IT_TXI
SMBUS_LAST_FRAME_NO_PEC
SMBUS_LAST_FRAME_WITH_PEC
SMBUS_NEXT_FRAME
SMBUS_NO_STARTSTOP
SMBUS_NOSTRETCH_DISABLE
SMBUS_NOSTRETCH_ENABLE
SMBUS_OA2_MASK01
SMBUS_OA2_MASK02
SMBUS_OA2_MASK03
SMBUS_OA2_MASK04
SMBUS_OA2_MASK05
SMBUS_OA2_MASK06
SMBUS_OA2_MASK07
SMBUS_OA2_NOMASK
SMBUS_OTHER_AND_LAST_FRAME_NO_PEC
SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC
SMBUS_OTHER_FRAME_NO_PEC
SMBUS_OTHER_FRAME_WITH_PEC
SMBUS_PEC_DISABLE
SMBUS_PEC_ENABLE
SMBUS_PERIPHERAL_MODE_SMBUS_HOST
SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE
SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP
SMBUS_RELOAD_MODE
SMBUS_RESET_CR1
SMBUS_RESET_CR2
SMBUS_SENDPEC_MODE
SMBUS_SOFTEND_MODE
pSMBUS_AddrCallbackTypeDef
pSMBUS_CallbackTypeDef
SMBUS_HandleTypeDef
HAL_SMBUS_CallbackIDTypeDef
HAL_SMBUS_AddrCallback
HAL_SMBUS_ConfigAnalogFilter
HAL_SMBUS_ConfigDigitalFilter
HAL_SMBUS_DeInit
HAL_SMBUS_DisableAlert_IT
HAL_SMBUS_DisableListen_IT
HAL_SMBUS_EnableAlert_IT
HAL_SMBUS_EnableListen_IT
HAL_SMBUS_ER_IRQHandler
HAL_SMBUS_ErrorCallback
HAL_SMBUS_EV_IRQHandler
HAL_SMBUS_GetError
HAL_SMBUS_GetState
HAL_SMBUS_Init
HAL_SMBUS_IsDeviceReady
HAL_SMBUS_ListenCpltCallback
HAL_SMBUS_Master_Abort_IT
HAL_SMBUS_Master_Receive_IT
HAL_SMBUS_Master_Transmit_IT
HAL_SMBUS_MasterRxCpltCallback
HAL_SMBUS_MasterTxCpltCallback
HAL_SMBUS_MspDeInit
HAL_SMBUS_MspInit
HAL_SMBUS_RegisterAddrCallback
HAL_SMBUS_RegisterCallback
HAL_SMBUS_Slave_Receive_IT
HAL_SMBUS_Slave_Transmit_IT
HAL_SMBUS_SlaveRxCpltCallback
HAL_SMBUS_SlaveTxCpltCallback
HAL_SMBUS_UnRegisterAddrCallback
HAL_SMBUS_UnRegisterCallback
stm32g4xx_hal_smbus_ex.c
HAL_SMBUSEx_DisableWakeUp
HAL_SMBUSEx_EnableFastModePlus
HAL_SMBUSEx_EnableWakeUp
stm32g4xx_hal_smbus_ex.h
SMBUS_FASTMODEPLUS_I2C1
SMBUS_FASTMODEPLUS_I2C2
SMBUS_FASTMODEPLUS_I2C3
SMBUS_FASTMODEPLUS_I2C4
SMBUS_FASTMODEPLUS_PB6
SMBUS_FASTMODEPLUS_PB7
SMBUS_FASTMODEPLUS_PB8
SMBUS_FASTMODEPLUS_PB9
SMBUS_FMP_NOT_SUPPORTED
HAL_SMBUSEx_DisableFastModePlus
HAL_SMBUSEx_DisableWakeUp
HAL_SMBUSEx_EnableFastModePlus
HAL_SMBUSEx_EnableWakeUp
stm32g4xx_hal_spi.c
HAL_SPI_Abort
HAL_SPI_Abort_IT
HAL_SPI_AbortCpltCallback
HAL_SPI_DeInit
HAL_SPI_DMAPause
HAL_SPI_DMAResume
HAL_SPI_DMAStop
HAL_SPI_ErrorCallback
HAL_SPI_GetError
HAL_SPI_GetState
HAL_SPI_Init
HAL_SPI_IRQHandler
HAL_SPI_MspDeInit
HAL_SPI_MspInit
HAL_SPI_Receive
HAL_SPI_Receive_DMA
HAL_SPI_Receive_IT
HAL_SPI_RegisterCallback
HAL_SPI_RxCpltCallback
HAL_SPI_RxHalfCpltCallback
HAL_SPI_Transmit
HAL_SPI_Transmit_DMA
HAL_SPI_Transmit_IT
HAL_SPI_TransmitReceive
HAL_SPI_TransmitReceive_DMA
HAL_SPI_TransmitReceive_IT
HAL_SPI_TxCpltCallback
HAL_SPI_TxHalfCpltCallback
HAL_SPI_TxRxCpltCallback
HAL_SPI_TxRxHalfCpltCallback
HAL_SPI_UnRegisterCallback
SPI_2linesRxISR_16BIT
SPI_2linesRxISR_16BITCRC
SPI_2linesRxISR_8BIT
SPI_2linesRxISR_8BITCRC
SPI_2linesTxISR_16BIT
SPI_2linesTxISR_8BIT
SPI_AbortRx_ISR
SPI_AbortTx_ISR
SPI_CloseRx_ISR
SPI_CloseRxTx_ISR
SPI_CloseTx_ISR
SPI_DMAAbortOnError
SPI_DMAError
SPI_DMAHalfReceiveCplt
SPI_DMAHalfTransmitCplt
SPI_DMAHalfTransmitReceiveCplt
SPI_DMAReceiveCplt
SPI_DMARxAbortCallback
SPI_DMATransmitCplt
SPI_DMATransmitReceiveCplt
SPI_DMATxAbortCallback
SPI_EndRxTransaction
SPI_EndRxTxTransaction
SPI_RxISR_16BIT
SPI_RxISR_16BITCRC
SPI_RxISR_8BIT
SPI_RxISR_8BITCRC
SPI_TxISR_16BIT
SPI_TxISR_8BIT
SPI_WaitFifoStateUntilTimeout
SPI_WaitFlagStateUntilTimeout
stm32g4xx_hal_spi.h
__HAL_SPI_CLEAR_FREFLAG
__HAL_SPI_CLEAR_MODFFLAG
__HAL_SPI_CLEAR_OVRFLAG
__HAL_SPI_DISABLE
__HAL_SPI_DISABLE_IT
__HAL_SPI_ENABLE
__HAL_SPI_ENABLE_IT
__HAL_SPI_GET_FLAG
__HAL_SPI_GET_IT_SOURCE
__HAL_SPI_RESET_HANDLE_STATE
HAL_SPI_ERROR_ABORT
HAL_SPI_ERROR_CRC
HAL_SPI_ERROR_DMA
HAL_SPI_ERROR_FLAG
HAL_SPI_ERROR_FRE
HAL_SPI_ERROR_INVALID_CALLBACK
HAL_SPI_ERROR_MODF
HAL_SPI_ERROR_NONE
HAL_SPI_ERROR_OVR
IS_SPI_BAUDRATE_PRESCALER
IS_SPI_CPHA
IS_SPI_CPOL
IS_SPI_CRC_CALCULATION
IS_SPI_CRC_LENGTH
IS_SPI_CRC_POLYNOMIAL
IS_SPI_DATASIZE
IS_SPI_DIRECTION
IS_SPI_DIRECTION_2LINES
IS_SPI_DIRECTION_2LINES_OR_1LINE
IS_SPI_DMA_HANDLE
IS_SPI_FIRST_BIT
IS_SPI_MODE
IS_SPI_NSS
IS_SPI_NSSP
IS_SPI_TIMODE
SPI_1LINE_RX
SPI_1LINE_TX
SPI_BAUDRATEPRESCALER_128
SPI_BAUDRATEPRESCALER_16
SPI_BAUDRATEPRESCALER_2
SPI_BAUDRATEPRESCALER_256
SPI_BAUDRATEPRESCALER_32
SPI_BAUDRATEPRESCALER_4
SPI_BAUDRATEPRESCALER_64
SPI_BAUDRATEPRESCALER_8
SPI_CHECK_FLAG
SPI_CHECK_IT_SOURCE
SPI_CRC_LENGTH_16BIT
SPI_CRC_LENGTH_8BIT
SPI_CRC_LENGTH_DATASIZE
SPI_CRCCALCULATION_DISABLE
SPI_CRCCALCULATION_ENABLE
SPI_DATASIZE_10BIT
SPI_DATASIZE_11BIT
SPI_DATASIZE_12BIT
SPI_DATASIZE_13BIT
SPI_DATASIZE_14BIT
SPI_DATASIZE_15BIT
SPI_DATASIZE_16BIT
SPI_DATASIZE_4BIT
SPI_DATASIZE_5BIT
SPI_DATASIZE_6BIT
SPI_DATASIZE_7BIT
SPI_DATASIZE_8BIT
SPI_DATASIZE_9BIT
SPI_DIRECTION_1LINE
SPI_DIRECTION_2LINES
SPI_DIRECTION_2LINES_RXONLY
SPI_FIRSTBIT_LSB
SPI_FIRSTBIT_MSB
SPI_FLAG_BSY
SPI_FLAG_CRCERR
SPI_FLAG_FRE
SPI_FLAG_FRLVL
SPI_FLAG_FTLVL
SPI_FLAG_MASK
SPI_FLAG_MODF
SPI_FLAG_OVR
SPI_FLAG_RXNE
SPI_FLAG_TXE
SPI_FRLVL_EMPTY
SPI_FRLVL_FULL
SPI_FRLVL_HALF_FULL
SPI_FRLVL_QUARTER_FULL
SPI_FTLVL_EMPTY
SPI_FTLVL_FULL
SPI_FTLVL_HALF_FULL
SPI_FTLVL_QUARTER_FULL
SPI_IT_ERR
SPI_IT_RXNE
SPI_IT_TXE
SPI_MODE_MASTER
SPI_MODE_SLAVE
SPI_NSS_HARD_INPUT
SPI_NSS_HARD_OUTPUT
SPI_NSS_PULSE_DISABLE
SPI_NSS_PULSE_ENABLE
SPI_NSS_SOFT
SPI_PHASE_1EDGE
SPI_PHASE_2EDGE
SPI_POLARITY_HIGH
SPI_POLARITY_LOW
SPI_RESET_CRC
SPI_RXFIFO_THRESHOLD
SPI_RXFIFO_THRESHOLD_HF
SPI_RXFIFO_THRESHOLD_QF
SPI_TIMODE_DISABLE
SPI_TIMODE_ENABLE
pSPI_CallbackTypeDef
SPI_HandleTypeDef
HAL_SPI_CallbackIDTypeDef
HAL_SPI_StateTypeDef
HAL_SPI_Abort
HAL_SPI_Abort_IT
HAL_SPI_AbortCpltCallback
HAL_SPI_DeInit
HAL_SPI_DMAPause
HAL_SPI_DMAResume
HAL_SPI_DMAStop
HAL_SPI_ErrorCallback
HAL_SPI_GetError
HAL_SPI_GetState
HAL_SPI_Init
HAL_SPI_IRQHandler
HAL_SPI_MspDeInit
HAL_SPI_MspInit
HAL_SPI_Receive
HAL_SPI_Receive_DMA
HAL_SPI_Receive_IT
HAL_SPI_RegisterCallback
HAL_SPI_RxCpltCallback
HAL_SPI_RxHalfCpltCallback
HAL_SPI_Transmit
HAL_SPI_Transmit_DMA
HAL_SPI_Transmit_IT
HAL_SPI_TransmitReceive
HAL_SPI_TransmitReceive_DMA
HAL_SPI_TransmitReceive_IT
HAL_SPI_TxCpltCallback
HAL_SPI_TxHalfCpltCallback
HAL_SPI_TxRxCpltCallback
HAL_SPI_TxRxHalfCpltCallback
HAL_SPI_UnRegisterCallback
stm32g4xx_hal_spi_ex.c
HAL_SPIEx_FlushRxFifo
stm32g4xx_hal_spi_ex.h
stm32g4xx_hal_sram.c
HAL_SRAM_DMA_XferCpltCallback
HAL_SRAM_DMA_XferErrorCallback
HAL_SRAM_GetState
HAL_SRAM_Init
HAL_SRAM_MspDeInit
HAL_SRAM_MspInit
HAL_SRAM_Read_16b
HAL_SRAM_Read_32b
HAL_SRAM_Read_8b
HAL_SRAM_Read_DMA
HAL_SRAM_RegisterCallback
HAL_SRAM_RegisterDmaCallback
HAL_SRAM_UnRegisterCallback
HAL_SRAM_Write_16b
HAL_SRAM_Write_32b
HAL_SRAM_Write_8b
HAL_SRAM_Write_DMA
HAL_SRAM_WriteOperation_Disable
HAL_SRAM_WriteOperation_Enable
SRAM_DMACplt
SRAM_DMACpltProt
SRAM_DMAError
stm32g4xx_hal_sram.h
stm32g4xx_hal_tim.c
HAL_TIM_Base_DeInit
HAL_TIM_Base_GetState
HAL_TIM_Base_Init
HAL_TIM_Base_MspDeInit
HAL_TIM_Base_MspInit
HAL_TIM_Base_Start
HAL_TIM_Base_Start_DMA
HAL_TIM_Base_Start_IT
HAL_TIM_Base_Stop
HAL_TIM_Base_Stop_DMA
HAL_TIM_Base_Stop_IT
HAL_TIM_ConfigClockSource
HAL_TIM_ConfigOCrefClear
HAL_TIM_ConfigTI1Input
HAL_TIM_DMABurst_MultiReadStart
HAL_TIM_DMABurst_MultiWriteStart
HAL_TIM_DMABurst_ReadStart
HAL_TIM_DMABurst_ReadStop
HAL_TIM_DMABurst_WriteStart
HAL_TIM_DMABurst_WriteStop
HAL_TIM_DMABurstState
HAL_TIM_Encoder_DeInit
HAL_TIM_Encoder_GetState
HAL_TIM_Encoder_Init
HAL_TIM_Encoder_MspDeInit
HAL_TIM_Encoder_MspInit
HAL_TIM_Encoder_Start
HAL_TIM_Encoder_Start_DMA
HAL_TIM_Encoder_Start_IT
HAL_TIM_Encoder_Stop
HAL_TIM_Encoder_Stop_DMA
HAL_TIM_Encoder_Stop_IT
HAL_TIM_ErrorCallback
HAL_TIM_GenerateEvent
HAL_TIM_GetActiveChannel
HAL_TIM_GetChannelState
HAL_TIM_IC_CaptureCallback
HAL_TIM_IC_CaptureHalfCpltCallback
HAL_TIM_IC_ConfigChannel
HAL_TIM_IC_DeInit
HAL_TIM_IC_GetState
HAL_TIM_IC_Init
HAL_TIM_IC_MspDeInit
HAL_TIM_IC_MspInit
HAL_TIM_IC_Start
HAL_TIM_IC_Start_DMA
HAL_TIM_IC_Start_IT
HAL_TIM_IC_Stop
HAL_TIM_IC_Stop_DMA
HAL_TIM_IC_Stop_IT
HAL_TIM_IRQHandler
HAL_TIM_OC_ConfigChannel
HAL_TIM_OC_DeInit
HAL_TIM_OC_DelayElapsedCallback
HAL_TIM_OC_GetState
HAL_TIM_OC_Init
HAL_TIM_OC_MspDeInit
HAL_TIM_OC_MspInit
HAL_TIM_OC_Start
HAL_TIM_OC_Start_DMA
HAL_TIM_OC_Start_IT
HAL_TIM_OC_Stop
HAL_TIM_OC_Stop_DMA
HAL_TIM_OC_Stop_IT
HAL_TIM_OnePulse_ConfigChannel
HAL_TIM_OnePulse_DeInit
HAL_TIM_OnePulse_GetState
HAL_TIM_OnePulse_Init
HAL_TIM_OnePulse_MspDeInit
HAL_TIM_OnePulse_MspInit
HAL_TIM_OnePulse_Start
HAL_TIM_OnePulse_Start_IT
HAL_TIM_OnePulse_Stop
HAL_TIM_OnePulse_Stop_IT
HAL_TIM_PeriodElapsedCallback
HAL_TIM_PeriodElapsedHalfCpltCallback
HAL_TIM_PWM_ConfigChannel
HAL_TIM_PWM_DeInit
HAL_TIM_PWM_GetState
HAL_TIM_PWM_Init
HAL_TIM_PWM_MspDeInit
HAL_TIM_PWM_MspInit
HAL_TIM_PWM_PulseFinishedCallback
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
HAL_TIM_PWM_Start
HAL_TIM_PWM_Start_DMA
HAL_TIM_PWM_Start_IT
HAL_TIM_PWM_Stop
HAL_TIM_PWM_Stop_DMA
HAL_TIM_PWM_Stop_IT
HAL_TIM_ReadCapturedValue
HAL_TIM_RegisterCallback
HAL_TIM_SlaveConfigSynchro
HAL_TIM_SlaveConfigSynchro_IT
HAL_TIM_TriggerCallback
HAL_TIM_TriggerHalfCpltCallback
HAL_TIM_UnRegisterCallback
TIM_Base_SetConfig
TIM_CCxChannelCmd
TIM_DMACaptureCplt
TIM_DMACaptureHalfCplt
TIM_DMADelayPulseCplt
TIM_DMADelayPulseHalfCplt
TIM_DMAError
TIM_DMAPeriodElapsedCplt
TIM_DMAPeriodElapsedHalfCplt
TIM_DMATriggerCplt
TIM_DMATriggerHalfCplt
TIM_ETR_SetConfig
TIM_ITRx_SetConfig
TIM_OC1_SetConfig
TIM_OC2_SetConfig
TIM_OC3_SetConfig
TIM_OC4_SetConfig
TIM_OC5_SetConfig
TIM_OC6_SetConfig
TIM_ResetCallback
TIM_SlaveTimer_SetConfig
TIM_TI1_ConfigInputStage
TIM_TI1_SetConfig
TIM_TI2_ConfigInputStage
TIM_TI2_SetConfig
TIM_TI3_SetConfig
TIM_TI4_SetConfig
stm32g4xx_hal_tim.h
__HAL_TIM_CLEAR_IT
__HAL_TIM_DISABLE
__HAL_TIM_DISABLE_DMA
__HAL_TIM_DISABLE_IT
__HAL_TIM_DISABLE_OCxFAST
__HAL_TIM_DISABLE_OCxPRELOAD
__HAL_TIM_ENABLE
__HAL_TIM_ENABLE_DMA
__HAL_TIM_ENABLE_IT
__HAL_TIM_ENABLE_OCxFAST
__HAL_TIM_ENABLE_OCxPRELOAD
__HAL_TIM_GET_AUTORELOAD
__HAL_TIM_GET_CLOCKDIVISION
__HAL_TIM_GET_COMPARE
__HAL_TIM_GET_COUNTER
__HAL_TIM_GET_FLAG
__HAL_TIM_GET_ICPRESCALER
__HAL_TIM_GET_IT_SOURCE
__HAL_TIM_GET_UIFCPY
__HAL_TIM_IS_TIM_COUNTING_DOWN
__HAL_TIM_MOE_DISABLE
__HAL_TIM_MOE_DISABLE_UNCONDITIONALLY
__HAL_TIM_MOE_ENABLE
__HAL_TIM_RESET_HANDLE_STATE
__HAL_TIM_SELECT_CCDMAREQUEST
__HAL_TIM_SET_AUTORELOAD
__HAL_TIM_SET_CAPTUREPOLARITY
__HAL_TIM_SET_CLOCKDIVISION
__HAL_TIM_SET_COMPARE
__HAL_TIM_SET_COUNTER
__HAL_TIM_SET_ICPRESCALER
__HAL_TIM_SET_PRESCALER
__HAL_TIM_UIFREMAP_DISABLE
__HAL_TIM_UIFREMAP_ENABLE
__HAL_TIM_URS_DISABLE
__HAL_TIM_URS_ENABLE
IS_TIM_AUTOMATIC_OUTPUT_STATE
IS_TIM_AUTORELOAD_PRELOAD
IS_TIM_BREAK2_AFMODE
IS_TIM_BREAK2_POLARITY
IS_TIM_BREAK2_STATE
IS_TIM_BREAK_AFMODE
IS_TIM_BREAK_FILTER
IS_TIM_BREAK_POLARITY
IS_TIM_BREAK_STATE
IS_TIM_BREAK_SYSTEM
IS_TIM_CCX_CHANNEL
IS_TIM_CHANNELS
IS_TIM_CLEARINPUT_FILTER
IS_TIM_CLEARINPUT_POLARITY
IS_TIM_CLEARINPUT_PRESCALER
IS_TIM_CLEARINPUT_SOURCE
IS_TIM_CLOCKDIVISION_DIV
IS_TIM_CLOCKFILTER
IS_TIM_CLOCKPOLARITY
IS_TIM_CLOCKPRESCALER
IS_TIM_CLOCKSOURCE
IS_TIM_COMPLEMENTARY_CHANNELS
IS_TIM_COUNTER_MODE
IS_TIM_DEADTIME
IS_TIM_DMA_BASE
IS_TIM_DMA_DATA_LENGTH
IS_TIM_DMA_LENGTH
IS_TIM_DMA_SOURCE
IS_TIM_ENCODER_MODE
IS_TIM_ENCODERINPUT_POLARITY
IS_TIM_EVENT_SOURCE
IS_TIM_FAST_STATE
IS_TIM_GROUPCH5
IS_TIM_IC_FILTER
IS_TIM_IC_POLARITY
IS_TIM_IC_PRESCALER
IS_TIM_IC_SELECTION
IS_TIM_LOCK_LEVEL
IS_TIM_MSM_STATE
IS_TIM_OC_MODE
IS_TIM_OC_POLARITY
IS_TIM_OCIDLE_STATE
IS_TIM_OCN_POLARITY
IS_TIM_OCNIDLE_STATE
IS_TIM_OPM_CHANNELS
IS_TIM_OPM_MODE
IS_TIM_OSSI_STATE
IS_TIM_OSSR_STATE
IS_TIM_PERIOD
IS_TIM_PWM_MODE
IS_TIM_SLAVE_MODE
IS_TIM_SLAVEMODE_TRIGGER_ENABLED
IS_TIM_TI1SELECTION
IS_TIM_TRGO2_SOURCE
IS_TIM_TRGO_SOURCE
IS_TIM_TRIGGERFILTER
IS_TIM_TRIGGERPOLARITY
IS_TIM_TRIGGERPRESCALER
IS_TIM_UIFREMAP_MODE
TIM_AUTOMATICOUTPUT_DISABLE
TIM_AUTOMATICOUTPUT_ENABLE
TIM_AUTORELOAD_PRELOAD_DISABLE
TIM_AUTORELOAD_PRELOAD_ENABLE
TIM_BREAK2_AFMODE_BIDIRECTIONAL
TIM_BREAK2_AFMODE_INPUT
TIM_BREAK2_DISABLE
TIM_BREAK2_ENABLE
TIM_BREAK2POLARITY_HIGH
TIM_BREAK2POLARITY_LOW
TIM_BREAK_AFMODE_BIDIRECTIONAL
TIM_BREAK_AFMODE_INPUT
TIM_BREAK_DISABLE
TIM_BREAK_ENABLE
TIM_BREAK_SYSTEM_ECC
TIM_BREAK_SYSTEM_LOCKUP
TIM_BREAK_SYSTEM_PVD
TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR
TIM_BREAKPOLARITY_HIGH
TIM_BREAKPOLARITY_LOW
TIM_CCDMAREQUEST_CC
TIM_CCDMAREQUEST_UPDATE
TIM_CCER_CCxE_MASK
TIM_CCER_CCxNE_MASK
TIM_CCx_DISABLE
TIM_CCx_ENABLE
TIM_CCxN_DISABLE
TIM_CCxN_ENABLE
TIM_CHANNEL_1
TIM_CHANNEL_2
TIM_CHANNEL_3
TIM_CHANNEL_4
TIM_CHANNEL_5
TIM_CHANNEL_6
TIM_CHANNEL_ALL
TIM_CHANNEL_N_STATE_GET
TIM_CHANNEL_N_STATE_SET
TIM_CHANNEL_N_STATE_SET_ALL
TIM_CHANNEL_STATE_GET
TIM_CHANNEL_STATE_SET
TIM_CHANNEL_STATE_SET_ALL
TIM_CLEARINPUTPOLARITY_INVERTED
TIM_CLEARINPUTPOLARITY_NONINVERTED
TIM_CLEARINPUTPRESCALER_DIV1
TIM_CLEARINPUTPRESCALER_DIV2
TIM_CLEARINPUTPRESCALER_DIV4
TIM_CLEARINPUTPRESCALER_DIV8
TIM_CLEARINPUTSOURCE_COMP1
TIM_CLEARINPUTSOURCE_COMP2
TIM_CLEARINPUTSOURCE_COMP3
TIM_CLEARINPUTSOURCE_COMP4
TIM_CLEARINPUTSOURCE_COMP5
TIM_CLEARINPUTSOURCE_COMP6
TIM_CLEARINPUTSOURCE_COMP7
TIM_CLEARINPUTSOURCE_ETR
TIM_CLEARINPUTSOURCE_NONE
TIM_CLOCKDIVISION_DIV1
TIM_CLOCKDIVISION_DIV2
TIM_CLOCKDIVISION_DIV4
TIM_CLOCKPOLARITY_BOTHEDGE
TIM_CLOCKPOLARITY_FALLING
TIM_CLOCKPOLARITY_INVERTED
TIM_CLOCKPOLARITY_NONINVERTED
TIM_CLOCKPOLARITY_RISING
TIM_CLOCKPRESCALER_DIV1
TIM_CLOCKPRESCALER_DIV2
TIM_CLOCKPRESCALER_DIV4
TIM_CLOCKPRESCALER_DIV8
TIM_CLOCKSOURCE_ETRMODE1
TIM_CLOCKSOURCE_ETRMODE2
TIM_CLOCKSOURCE_INTERNAL
TIM_CLOCKSOURCE_ITR0
TIM_CLOCKSOURCE_ITR1
TIM_CLOCKSOURCE_ITR10
TIM_CLOCKSOURCE_ITR11
TIM_CLOCKSOURCE_ITR2
TIM_CLOCKSOURCE_ITR3
TIM_CLOCKSOURCE_ITR4
TIM_CLOCKSOURCE_ITR5
TIM_CLOCKSOURCE_ITR6
TIM_CLOCKSOURCE_ITR7
TIM_CLOCKSOURCE_ITR8
TIM_CLOCKSOURCE_ITR9
TIM_CLOCKSOURCE_TI1
TIM_CLOCKSOURCE_TI1ED
TIM_CLOCKSOURCE_TI2
TIM_COMMUTATION_SOFTWARE
TIM_COMMUTATION_TRGI
TIM_COUNTERMODE_CENTERALIGNED1
TIM_COUNTERMODE_CENTERALIGNED2
TIM_COUNTERMODE_CENTERALIGNED3
TIM_COUNTERMODE_DOWN
TIM_COUNTERMODE_UP
TIM_DMA_CC1
TIM_DMA_CC2
TIM_DMA_CC3
TIM_DMA_CC4
TIM_DMA_COM
TIM_DMA_ID_CC1
TIM_DMA_ID_CC2
TIM_DMA_ID_CC3
TIM_DMA_ID_CC4
TIM_DMA_ID_COMMUTATION
TIM_DMA_ID_TRIGGER
TIM_DMA_ID_UPDATE
TIM_DMA_TRIGGER
TIM_DMA_UPDATE
TIM_DMABASE_AF1
TIM_DMABASE_AF2
TIM_DMABASE_ARR
TIM_DMABASE_BDTR
TIM_DMABASE_CCER
TIM_DMABASE_CCMR1
TIM_DMABASE_CCMR2
TIM_DMABASE_CCMR3
TIM_DMABASE_CCR1
TIM_DMABASE_CCR2
TIM_DMABASE_CCR3
TIM_DMABASE_CCR4
TIM_DMABASE_CCR5
TIM_DMABASE_CCR6
TIM_DMABASE_CNT
TIM_DMABASE_CR1
TIM_DMABASE_CR2
TIM_DMABASE_DIER
TIM_DMABASE_DTR2
TIM_DMABASE_ECR
TIM_DMABASE_EGR
TIM_DMABASE_OR
TIM_DMABASE_PSC
TIM_DMABASE_RCR
TIM_DMABASE_SMCR
TIM_DMABASE_SR
TIM_DMABASE_TISEL
TIM_DMABURSTLENGTH_10TRANSFERS
TIM_DMABURSTLENGTH_11TRANSFERS
TIM_DMABURSTLENGTH_12TRANSFERS
TIM_DMABURSTLENGTH_13TRANSFERS
TIM_DMABURSTLENGTH_14TRANSFERS
TIM_DMABURSTLENGTH_15TRANSFERS
TIM_DMABURSTLENGTH_16TRANSFERS
TIM_DMABURSTLENGTH_17TRANSFERS
TIM_DMABURSTLENGTH_18TRANSFERS
TIM_DMABURSTLENGTH_19TRANSFERS
TIM_DMABURSTLENGTH_1TRANSFER
TIM_DMABURSTLENGTH_20TRANSFERS
TIM_DMABURSTLENGTH_21TRANSFERS
TIM_DMABURSTLENGTH_22TRANSFERS
TIM_DMABURSTLENGTH_23TRANSFERS
TIM_DMABURSTLENGTH_24TRANSFERS
TIM_DMABURSTLENGTH_25TRANSFERS
TIM_DMABURSTLENGTH_26TRANSFERS
TIM_DMABURSTLENGTH_2TRANSFERS
TIM_DMABURSTLENGTH_3TRANSFERS
TIM_DMABURSTLENGTH_4TRANSFERS
TIM_DMABURSTLENGTH_5TRANSFERS
TIM_DMABURSTLENGTH_6TRANSFERS
TIM_DMABURSTLENGTH_7TRANSFERS
TIM_DMABURSTLENGTH_8TRANSFERS
TIM_DMABURSTLENGTH_9TRANSFERS
TIM_ENCODERINPUTPOLARITY_FALLING
TIM_ENCODERINPUTPOLARITY_RISING
TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
TIM_ENCODERMODE_TI1
TIM_ENCODERMODE_TI12
TIM_ENCODERMODE_TI2
TIM_ENCODERMODE_X1_TI1
TIM_ENCODERMODE_X1_TI2
TIM_ETRPOLARITY_INVERTED
TIM_ETRPOLARITY_NONINVERTED
TIM_ETRPRESCALER_DIV1
TIM_ETRPRESCALER_DIV2
TIM_ETRPRESCALER_DIV4
TIM_ETRPRESCALER_DIV8
TIM_EVENTSOURCE_BREAK
TIM_EVENTSOURCE_BREAK2
TIM_EVENTSOURCE_CC1
TIM_EVENTSOURCE_CC2
TIM_EVENTSOURCE_CC3
TIM_EVENTSOURCE_CC4
TIM_EVENTSOURCE_COM
TIM_EVENTSOURCE_TRIGGER
TIM_EVENTSOURCE_UPDATE
TIM_FLAG_BREAK
TIM_FLAG_BREAK2
TIM_FLAG_CC1
TIM_FLAG_CC1OF
TIM_FLAG_CC2
TIM_FLAG_CC2OF
TIM_FLAG_CC3
TIM_FLAG_CC3OF
TIM_FLAG_CC4
TIM_FLAG_CC4OF
TIM_FLAG_CC5
TIM_FLAG_CC6
TIM_FLAG_COM
TIM_FLAG_DIR
TIM_FLAG_IDX
TIM_FLAG_IERR
TIM_FLAG_SYSTEM_BREAK
TIM_FLAG_TERR
TIM_FLAG_TRIGGER
TIM_FLAG_UPDATE
TIM_GROUPCH5_NONE
TIM_GROUPCH5_OC1REFC
TIM_GROUPCH5_OC2REFC
TIM_GROUPCH5_OC3REFC
TIM_ICPOLARITY_BOTHEDGE
TIM_ICPOLARITY_FALLING
TIM_ICPOLARITY_RISING
TIM_ICPSC_DIV1
TIM_ICPSC_DIV2
TIM_ICPSC_DIV4
TIM_ICPSC_DIV8
TIM_ICSELECTION_DIRECTTI
TIM_ICSELECTION_INDIRECTTI
TIM_ICSELECTION_TRC
TIM_INPUTCHANNELPOLARITY_BOTHEDGE
TIM_INPUTCHANNELPOLARITY_FALLING
TIM_INPUTCHANNELPOLARITY_RISING
TIM_IT_BREAK
TIM_IT_CC1
TIM_IT_CC2
TIM_IT_CC3
TIM_IT_CC4
TIM_IT_COM
TIM_IT_DIR
TIM_IT_IDX
TIM_IT_IERR
TIM_IT_TERR
TIM_IT_TRIGGER
TIM_IT_UPDATE
TIM_LOCKLEVEL_1
TIM_LOCKLEVEL_2
TIM_LOCKLEVEL_3
TIM_LOCKLEVEL_OFF
TIM_MASTERSLAVEMODE_DISABLE
TIM_MASTERSLAVEMODE_ENABLE
TIM_OCFAST_DISABLE
TIM_OCFAST_ENABLE
TIM_OCIDLESTATE_RESET
TIM_OCIDLESTATE_SET
TIM_OCMODE_ACTIVE
TIM_OCMODE_ASYMMETRIC_PWM1
TIM_OCMODE_ASYMMETRIC_PWM2
TIM_OCMODE_COMBINED_PWM1
TIM_OCMODE_COMBINED_PWM2
TIM_OCMODE_DIRECTION_OUTPUT
TIM_OCMODE_FORCED_ACTIVE
TIM_OCMODE_FORCED_INACTIVE
TIM_OCMODE_INACTIVE
TIM_OCMODE_PULSE_ON_COMPARE
TIM_OCMODE_PWM1
TIM_OCMODE_PWM2
TIM_OCMODE_RETRIGERRABLE_OPM1
TIM_OCMODE_RETRIGERRABLE_OPM2
TIM_OCMODE_TIMING
TIM_OCMODE_TOGGLE
TIM_OCNIDLESTATE_RESET
TIM_OCNIDLESTATE_SET
TIM_OCNPOLARITY_HIGH
TIM_OCNPOLARITY_LOW
TIM_OCPOLARITY_HIGH
TIM_OCPOLARITY_LOW
TIM_OPMODE_REPETITIVE
TIM_OPMODE_SINGLE
TIM_OSSI_DISABLE
TIM_OSSI_ENABLE
TIM_OSSR_DISABLE
TIM_OSSR_ENABLE
TIM_OUTPUTNSTATE_DISABLE
TIM_OUTPUTNSTATE_ENABLE
TIM_OUTPUTSTATE_DISABLE
TIM_OUTPUTSTATE_ENABLE
TIM_RESET_CAPTUREPOLARITY
TIM_RESET_ICPRESCALERVALUE
TIM_SET_CAPTUREPOLARITY
TIM_SET_ICPRESCALERVALUE
TIM_SLAVEMODE_COMBINED_GATEDRESET
TIM_SLAVEMODE_COMBINED_RESETTRIGGER
TIM_SLAVEMODE_DISABLE
TIM_SLAVEMODE_EXTERNAL1
TIM_SLAVEMODE_GATED
TIM_SLAVEMODE_RESET
TIM_SLAVEMODE_TRIGGER
TIM_TI1SELECTION_CH1
TIM_TI1SELECTION_XORCOMBINATION
TIM_TRGO2_ENABLE
TIM_TRGO2_OC1
TIM_TRGO2_OC1REF
TIM_TRGO2_OC2REF
TIM_TRGO2_OC3REF
TIM_TRGO2_OC4REF
TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING
TIM_TRGO2_OC4REF_RISING_OC6REF_RISING
TIM_TRGO2_OC4REF_RISINGFALLING
TIM_TRGO2_OC5REF
TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING
TIM_TRGO2_OC5REF_RISING_OC6REF_RISING
TIM_TRGO2_OC6REF
TIM_TRGO2_OC6REF_RISINGFALLING
TIM_TRGO2_RESET
TIM_TRGO2_UPDATE
TIM_TRGO_ENABLE
TIM_TRGO_ENCODER_CLK
TIM_TRGO_OC1
TIM_TRGO_OC1REF
TIM_TRGO_OC2REF
TIM_TRGO_OC3REF
TIM_TRGO_OC4REF
TIM_TRGO_RESET
TIM_TRGO_UPDATE
TIM_TRIGGERPOLARITY_BOTHEDGE
TIM_TRIGGERPOLARITY_FALLING
TIM_TRIGGERPOLARITY_INVERTED
TIM_TRIGGERPOLARITY_NONINVERTED
TIM_TRIGGERPOLARITY_RISING
TIM_TRIGGERPRESCALER_DIV1
TIM_TRIGGERPRESCALER_DIV2
TIM_TRIGGERPRESCALER_DIV4
TIM_TRIGGERPRESCALER_DIV8
TIM_TS_ETRF
TIM_TS_ITR0
TIM_TS_ITR1
TIM_TS_ITR10
TIM_TS_ITR11
TIM_TS_ITR2
TIM_TS_ITR3
TIM_TS_ITR4
TIM_TS_ITR5
TIM_TS_ITR6
TIM_TS_ITR7
TIM_TS_ITR8
TIM_TS_ITR9
TIM_TS_NONE
TIM_TS_TI1F_ED
TIM_TS_TI1FP1
TIM_TS_TI2FP2
TIM_UIFREMAP_DISABLE
TIM_UIFREMAP_ENABLE
pTIM_CallbackTypeDef
TIM_HandleTypeDef
HAL_TIM_ActiveChannel
HAL_TIM_CallbackIDTypeDef
HAL_TIM_ChannelStateTypeDef
HAL_TIM_DMABurstStateTypeDef
HAL_TIM_StateTypeDef
HAL_TIM_Base_DeInit
HAL_TIM_Base_GetState
HAL_TIM_Base_Init
HAL_TIM_Base_MspDeInit
HAL_TIM_Base_MspInit
HAL_TIM_Base_Start
HAL_TIM_Base_Start_DMA
HAL_TIM_Base_Start_IT
HAL_TIM_Base_Stop
HAL_TIM_Base_Stop_DMA
HAL_TIM_Base_Stop_IT
HAL_TIM_ConfigClockSource
HAL_TIM_ConfigOCrefClear
HAL_TIM_ConfigTI1Input
HAL_TIM_DMABurst_MultiReadStart
HAL_TIM_DMABurst_MultiWriteStart
HAL_TIM_DMABurst_ReadStart
HAL_TIM_DMABurst_ReadStop
HAL_TIM_DMABurst_WriteStart
HAL_TIM_DMABurst_WriteStop
HAL_TIM_DMABurstState
HAL_TIM_Encoder_DeInit
HAL_TIM_Encoder_GetState
HAL_TIM_Encoder_Init
HAL_TIM_Encoder_MspDeInit
HAL_TIM_Encoder_MspInit
HAL_TIM_Encoder_Start
HAL_TIM_Encoder_Start_DMA
HAL_TIM_Encoder_Start_IT
HAL_TIM_Encoder_Stop
HAL_TIM_Encoder_Stop_DMA
HAL_TIM_Encoder_Stop_IT
HAL_TIM_ErrorCallback
HAL_TIM_GenerateEvent
HAL_TIM_GetActiveChannel
HAL_TIM_GetChannelState
HAL_TIM_IC_CaptureCallback
HAL_TIM_IC_CaptureHalfCpltCallback
HAL_TIM_IC_ConfigChannel
HAL_TIM_IC_DeInit
HAL_TIM_IC_GetState
HAL_TIM_IC_Init
HAL_TIM_IC_MspDeInit
HAL_TIM_IC_MspInit
HAL_TIM_IC_Start
HAL_TIM_IC_Start_DMA
HAL_TIM_IC_Start_IT
HAL_TIM_IC_Stop
HAL_TIM_IC_Stop_DMA
HAL_TIM_IC_Stop_IT
HAL_TIM_IRQHandler
HAL_TIM_OC_ConfigChannel
HAL_TIM_OC_DeInit
HAL_TIM_OC_DelayElapsedCallback
HAL_TIM_OC_GetState
HAL_TIM_OC_Init
HAL_TIM_OC_MspDeInit
HAL_TIM_OC_MspInit
HAL_TIM_OC_Start
HAL_TIM_OC_Start_DMA
HAL_TIM_OC_Start_IT
HAL_TIM_OC_Stop
HAL_TIM_OC_Stop_DMA
HAL_TIM_OC_Stop_IT
HAL_TIM_OnePulse_ConfigChannel
HAL_TIM_OnePulse_DeInit
HAL_TIM_OnePulse_GetState
HAL_TIM_OnePulse_Init
HAL_TIM_OnePulse_MspDeInit
HAL_TIM_OnePulse_MspInit
HAL_TIM_OnePulse_Start
HAL_TIM_OnePulse_Start_IT
HAL_TIM_OnePulse_Stop
HAL_TIM_OnePulse_Stop_IT
HAL_TIM_PeriodElapsedCallback
HAL_TIM_PeriodElapsedHalfCpltCallback
HAL_TIM_PWM_ConfigChannel
HAL_TIM_PWM_DeInit
HAL_TIM_PWM_GetState
HAL_TIM_PWM_Init
HAL_TIM_PWM_MspDeInit
HAL_TIM_PWM_MspInit
HAL_TIM_PWM_PulseFinishedCallback
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
HAL_TIM_PWM_Start
HAL_TIM_PWM_Start_DMA
HAL_TIM_PWM_Start_IT
HAL_TIM_PWM_Stop
HAL_TIM_PWM_Stop_DMA
HAL_TIM_PWM_Stop_IT
HAL_TIM_ReadCapturedValue
HAL_TIM_RegisterCallback
HAL_TIM_SlaveConfigSynchro
HAL_TIM_SlaveConfigSynchro_IT
HAL_TIM_TriggerCallback
HAL_TIM_TriggerHalfCpltCallback
HAL_TIM_UnRegisterCallback
TIM_Base_SetConfig
TIM_CCxChannelCmd
TIM_DMACaptureCplt
TIM_DMACaptureHalfCplt
TIM_DMADelayPulseHalfCplt
TIM_DMAError
TIM_ETR_SetConfig
TIM_OC2_SetConfig
TIM_ResetCallback
TIM_TI1_SetConfig
stm32g4xx_hal_tim_ex.c
HAL_TIMEx_Break2Callback
HAL_TIMEx_BreakCallback
HAL_TIMEx_CommutCallback
HAL_TIMEx_CommutHalfCpltCallback
HAL_TIMEx_ConfigAsymmetricalDeadTime
HAL_TIMEx_ConfigBreakDeadTime
HAL_TIMEx_ConfigBreakInput
HAL_TIMEx_ConfigCommutEvent
HAL_TIMEx_ConfigCommutEvent_DMA
HAL_TIMEx_ConfigCommutEvent_IT
HAL_TIMEx_ConfigDeadTime
HAL_TIMEx_ConfigEncoderIndex
HAL_TIMEx_ConfigSlaveModePreload
HAL_TIMEx_DirectionChangeCallback
HAL_TIMEx_DisableAsymmetricalDeadTime
HAL_TIMEx_DisableDeadTimePreload
HAL_TIMEx_DisableEncoderFirstIndex
HAL_TIMEx_DisableEncoderIndex
HAL_TIMEx_DisableSlaveModePreload
HAL_TIMEx_DisarmBreakInput
HAL_TIMEx_DitheringDisable
HAL_TIMEx_DitheringEnable
HAL_TIMEx_EnableAsymmetricalDeadTime
HAL_TIMEx_EnableDeadTimePreload
HAL_TIMEx_EnableEncoderFirstIndex
HAL_TIMEx_EnableEncoderIndex
HAL_TIMEx_EnableSlaveModePreload
HAL_TIMEx_EncoderIndexCallback
HAL_TIMEx_GetChannelNState
HAL_TIMEx_GroupChannel5
HAL_TIMEx_HallSensor_DeInit
HAL_TIMEx_HallSensor_GetState
HAL_TIMEx_HallSensor_Init
HAL_TIMEx_HallSensor_MspDeInit
HAL_TIMEx_HallSensor_MspInit
HAL_TIMEx_HallSensor_Start
HAL_TIMEx_HallSensor_Start_DMA
HAL_TIMEx_HallSensor_Start_IT
HAL_TIMEx_HallSensor_Stop
HAL_TIMEx_HallSensor_Stop_DMA
HAL_TIMEx_HallSensor_Stop_IT
HAL_TIMEx_IndexErrorCallback
HAL_TIMEx_MasterConfigSynchronization
HAL_TIMEx_OC_ConfigPulseOnCompare
HAL_TIMEx_OCN_Start
HAL_TIMEx_OCN_Start_DMA
HAL_TIMEx_OCN_Start_IT
HAL_TIMEx_OCN_Stop
HAL_TIMEx_OCN_Stop_DMA
HAL_TIMEx_OCN_Stop_IT
HAL_TIMEx_OnePulseN_Start
HAL_TIMEx_OnePulseN_Start_IT
HAL_TIMEx_OnePulseN_Stop
HAL_TIMEx_OnePulseN_Stop_IT
HAL_TIMEx_PWMN_Start
HAL_TIMEx_PWMN_Start_DMA
HAL_TIMEx_PWMN_Start_IT
HAL_TIMEx_PWMN_Stop
HAL_TIMEx_PWMN_Stop_DMA
HAL_TIMEx_PWMN_Stop_IT
HAL_TIMEx_ReArmBreakInput
HAL_TIMEx_RemapConfig
HAL_TIMEx_TISelection
HAL_TIMEx_TransitionErrorCallback
TIM_CCxNChannelCmd
TIM_DMADelayPulseNCplt
TIM_DMAErrorCCxN
TIMEx_DMACommutationCplt
TIMEx_DMACommutationHalfCplt
stm32g4xx_hal_tim_ex.h
__HAL_TIM_CALC_PERIOD_BY_DELAY
__HAL_TIM_CALC_PERIOD_DITHER
__HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY
__HAL_TIM_CALC_PSC
__HAL_TIM_CALC_PULSE
__HAL_TIM_CALC_PULSE_DITHER
IS_TIM_BREAKINPUT
IS_TIM_BREAKINPUTSOURCE
IS_TIM_BREAKINPUTSOURCE_POLARITY
IS_TIM_BREAKINPUTSOURCE_STATE
IS_TIM_CLOCKSOURCE_INSTANCE
IS_TIM_ENCODERINDEX_DIRECTION
IS_TIM_ENCODERINDEX_FILTER
IS_TIM_ENCODERINDEX_POLARITY
IS_TIM_ENCODERINDEX_POSITION
IS_TIM_ENCODERINDEX_PRESCALER
IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE
IS_TIM_OC_CHANNEL_MODE
IS_TIM_PULSEONCOMPARE_CHANNEL
IS_TIM_PULSEONCOMPARE_INSTANCE
IS_TIM_PULSEONCOMPARE_WIDTH
IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER
IS_TIM_REMAP
IS_TIM_SLAVE_PRELOAD_SOURCE
IS_TIM_TISEL
IS_TIM_TISEL_TIX_INSTANCE
IS_TIM_TRIGGER_INSTANCE
TIM_BREAKINPUT_BRK
TIM_BREAKINPUT_BRK2
TIM_BREAKINPUTSOURCE_BKIN
TIM_BREAKINPUTSOURCE_COMP1
TIM_BREAKINPUTSOURCE_COMP2
TIM_BREAKINPUTSOURCE_COMP3
TIM_BREAKINPUTSOURCE_COMP4
TIM_BREAKINPUTSOURCE_COMP5
TIM_BREAKINPUTSOURCE_COMP6
TIM_BREAKINPUTSOURCE_COMP7
TIM_BREAKINPUTSOURCE_DISABLE
TIM_BREAKINPUTSOURCE_ENABLE
TIM_BREAKINPUTSOURCE_POLARITY_HIGH
TIM_BREAKINPUTSOURCE_POLARITY_LOW
TIM_ENCODERINDEX_DIRECTION_DOWN
TIM_ENCODERINDEX_DIRECTION_UP
TIM_ENCODERINDEX_DIRECTION_UP_DOWN
TIM_ENCODERINDEX_POLARITY_INVERTED
TIM_ENCODERINDEX_POLARITY_NONINVERTED
TIM_ENCODERINDEX_POSITION_0
TIM_ENCODERINDEX_POSITION_00
TIM_ENCODERINDEX_POSITION_01
TIM_ENCODERINDEX_POSITION_1
TIM_ENCODERINDEX_POSITION_10
TIM_ENCODERINDEX_POSITION_11
TIM_ENCODERINDEX_PRESCALER_DIV1
TIM_ENCODERINDEX_PRESCALER_DIV2
TIM_ENCODERINDEX_PRESCALER_DIV4
TIM_ENCODERINDEX_PRESCALER_DIV8
TIM_SMS_PRELOAD_SOURCE_INDEX
TIM_SMS_PRELOAD_SOURCE_UPDATE
TIM_TIM15_TI1_COMP1
TIM_TIM15_TI1_COMP2
TIM_TIM15_TI1_COMP5
TIM_TIM15_TI1_COMP7
TIM_TIM15_TI1_GPIO
TIM_TIM15_TI1_LSE
TIM_TIM15_TI2_COMP2
TIM_TIM15_TI2_COMP3
TIM_TIM15_TI2_COMP6
TIM_TIM15_TI2_COMP7
TIM_TIM15_TI2_GPIO
TIM_TIM16_TI1_COMP6
TIM_TIM16_TI1_GPIO
TIM_TIM16_TI1_HSE_32
TIM_TIM16_TI1_LSE
TIM_TIM16_TI1_LSI
TIM_TIM16_TI1_MCO
TIM_TIM16_TI1_RTC_WK
TIM_TIM17_TI1_COMP5
TIM_TIM17_TI1_GPIO
TIM_TIM17_TI1_HSE_32
TIM_TIM17_TI1_LSE
TIM_TIM17_TI1_LSI
TIM_TIM17_TI1_MCO
TIM_TIM17_TI1_RTC_WK
TIM_TIM1_ETR_ADC1_AWD1
TIM_TIM1_ETR_ADC1_AWD2
TIM_TIM1_ETR_ADC1_AWD3
TIM_TIM1_ETR_ADC4_AWD1
TIM_TIM1_ETR_ADC4_AWD2
TIM_TIM1_ETR_ADC4_AWD3
TIM_TIM1_ETR_COMP1
TIM_TIM1_ETR_COMP2
TIM_TIM1_ETR_COMP3
TIM_TIM1_ETR_COMP4
TIM_TIM1_ETR_COMP5
TIM_TIM1_ETR_COMP6
TIM_TIM1_ETR_COMP7
TIM_TIM1_ETR_GPIO
TIM_TIM1_TI1_COMP1
TIM_TIM1_TI1_COMP2
TIM_TIM1_TI1_COMP3
TIM_TIM1_TI1_COMP4
TIM_TIM1_TI1_GPIO
TIM_TIM20_ETR_ADC3_AWD1
TIM_TIM20_ETR_ADC3_AWD2
TIM_TIM20_ETR_ADC3_AWD3
TIM_TIM20_ETR_ADC5_AWD1
TIM_TIM20_ETR_ADC5_AWD2
TIM_TIM20_ETR_ADC5_AWD3
TIM_TIM20_ETR_COMP1
TIM_TIM20_ETR_COMP2
TIM_TIM20_ETR_COMP3
TIM_TIM20_ETR_COMP4
TIM_TIM20_ETR_COMP5
TIM_TIM20_ETR_COMP6
TIM_TIM20_ETR_COMP7
TIM_TIM20_ETR_GPIO
TIM_TIM20_TI1_COMP1
TIM_TIM20_TI1_COMP2
TIM_TIM20_TI1_COMP3
TIM_TIM20_TI1_COMP4
TIM_TIM20_TI1_GPIO
TIM_TIM2_ETR_COMP1
TIM_TIM2_ETR_COMP2
TIM_TIM2_ETR_COMP3
TIM_TIM2_ETR_COMP4
TIM_TIM2_ETR_COMP5
TIM_TIM2_ETR_COMP6
TIM_TIM2_ETR_COMP7
TIM_TIM2_ETR_GPIO
TIM_TIM2_ETR_LSE
TIM_TIM2_ETR_TIM3_ETR
TIM_TIM2_ETR_TIM4_ETR
TIM_TIM2_ETR_TIM5_ETR
TIM_TIM2_TI1_COMP1
TIM_TIM2_TI1_COMP2
TIM_TIM2_TI1_COMP3
TIM_TIM2_TI1_COMP4
TIM_TIM2_TI1_COMP5
TIM_TIM2_TI1_GPIO
TIM_TIM2_TI2_COMP1
TIM_TIM2_TI2_COMP2
TIM_TIM2_TI2_COMP3
TIM_TIM2_TI2_COMP4
TIM_TIM2_TI2_COMP6
TIM_TIM2_TI2_GPIO
TIM_TIM2_TI3_COMP4
TIM_TIM2_TI3_GPIO
TIM_TIM2_TI4_COMP1
TIM_TIM2_TI4_COMP2
TIM_TIM2_TI4_GPIO
TIM_TIM3_ETR_ADC2_AWD1
TIM_TIM3_ETR_ADC2_AWD2
TIM_TIM3_ETR_ADC2_AWD3
TIM_TIM3_ETR_COMP1
TIM_TIM3_ETR_COMP2
TIM_TIM3_ETR_COMP3
TIM_TIM3_ETR_COMP4
TIM_TIM3_ETR_COMP5
TIM_TIM3_ETR_COMP6
TIM_TIM3_ETR_COMP7
TIM_TIM3_ETR_GPIO
TIM_TIM3_ETR_TIM2_ETR
TIM_TIM3_ETR_TIM4_ETR
TIM_TIM3_TI1_COMP1
TIM_TIM3_TI1_COMP2
TIM_TIM3_TI1_COMP3
TIM_TIM3_TI1_COMP4
TIM_TIM3_TI1_COMP5
TIM_TIM3_TI1_COMP6
TIM_TIM3_TI1_COMP7
TIM_TIM3_TI1_GPIO
TIM_TIM3_TI2_COMP1
TIM_TIM3_TI2_COMP2
TIM_TIM3_TI2_COMP3
TIM_TIM3_TI2_COMP4
TIM_TIM3_TI2_COMP5
TIM_TIM3_TI2_COMP6
TIM_TIM3_TI2_COMP7
TIM_TIM3_TI2_GPIO
TIM_TIM3_TI3_COMP3
TIM_TIM3_TI3_GPIO
TIM_TIM4_ETR_COMP1
TIM_TIM4_ETR_COMP2
TIM_TIM4_ETR_COMP3
TIM_TIM4_ETR_COMP4
TIM_TIM4_ETR_COMP5
TIM_TIM4_ETR_COMP6
TIM_TIM4_ETR_COMP7
TIM_TIM4_ETR_GPIO
TIM_TIM4_ETR_TIM3_ETR
TIM_TIM4_ETR_TIM5_ETR
TIM_TIM4_TI1_COMP1
TIM_TIM4_TI1_COMP2
TIM_TIM4_TI1_COMP3
TIM_TIM4_TI1_COMP4
TIM_TIM4_TI1_COMP5
TIM_TIM4_TI1_COMP6
TIM_TIM4_TI1_COMP7
TIM_TIM4_TI1_GPIO
TIM_TIM4_TI2_COMP1
TIM_TIM4_TI2_COMP2
TIM_TIM4_TI2_COMP3
TIM_TIM4_TI2_COMP4
TIM_TIM4_TI2_COMP5
TIM_TIM4_TI2_COMP6
TIM_TIM4_TI2_COMP7
TIM_TIM4_TI2_GPIO
TIM_TIM4_TI3_COMP5
TIM_TIM4_TI3_GPIO
TIM_TIM4_TI4_COMP6
TIM_TIM4_TI4_GPIO
TIM_TIM5_ETR_COMP1
TIM_TIM5_ETR_COMP2
TIM_TIM5_ETR_COMP3
TIM_TIM5_ETR_COMP4
TIM_TIM5_ETR_COMP5
TIM_TIM5_ETR_COMP6
TIM_TIM5_ETR_COMP7
TIM_TIM5_ETR_GPIO
TIM_TIM5_ETR_TIM2_ETR
TIM_TIM5_ETR_TIM3_ETR
TIM_TIM5_TI1_COMP1
TIM_TIM5_TI1_COMP2
TIM_TIM5_TI1_COMP3
TIM_TIM5_TI1_COMP4
TIM_TIM5_TI1_COMP5
TIM_TIM5_TI1_COMP6
TIM_TIM5_TI1_COMP7
TIM_TIM5_TI1_GPIO
TIM_TIM5_TI1_LSE
TIM_TIM5_TI1_LSI
TIM_TIM5_TI1_RTC_WK
TIM_TIM5_TI2_COMP1
TIM_TIM5_TI2_COMP2
TIM_TIM5_TI2_COMP3
TIM_TIM5_TI2_COMP4
TIM_TIM5_TI2_COMP5
TIM_TIM5_TI2_COMP6
TIM_TIM5_TI2_COMP7
TIM_TIM5_TI2_GPIO
TIM_TIM8_ETR_ADC2_AWD1
TIM_TIM8_ETR_ADC2_AWD2
TIM_TIM8_ETR_ADC2_AWD3
TIM_TIM8_ETR_ADC3_AWD1
TIM_TIM8_ETR_ADC3_AWD2
TIM_TIM8_ETR_ADC3_AWD3
TIM_TIM8_ETR_COMP1
TIM_TIM8_ETR_COMP2
TIM_TIM8_ETR_COMP3
TIM_TIM8_ETR_COMP4
TIM_TIM8_ETR_COMP5
TIM_TIM8_ETR_COMP6
TIM_TIM8_ETR_COMP7
TIM_TIM8_ETR_GPIO
TIM_TIM8_TI1_COMP1
TIM_TIM8_TI1_COMP2
TIM_TIM8_TI1_COMP3
TIM_TIM8_TI1_COMP4
TIM_TIM8_TI1_GPIO
HAL_TIMEx_Break2Callback
HAL_TIMEx_BreakCallback
HAL_TIMEx_CommutCallback
HAL_TIMEx_CommutHalfCpltCallback
HAL_TIMEx_ConfigAsymmetricalDeadTime
HAL_TIMEx_ConfigBreakDeadTime
HAL_TIMEx_ConfigBreakInput
HAL_TIMEx_ConfigCommutEvent
HAL_TIMEx_ConfigCommutEvent_DMA
HAL_TIMEx_ConfigCommutEvent_IT
HAL_TIMEx_ConfigDeadTime
HAL_TIMEx_ConfigEncoderIndex
HAL_TIMEx_ConfigSlaveModePreload
HAL_TIMEx_DirectionChangeCallback
HAL_TIMEx_DisableAsymmetricalDeadTime
HAL_TIMEx_DisableDeadTimePreload
HAL_TIMEx_DisableEncoderFirstIndex
HAL_TIMEx_DisableEncoderIndex
HAL_TIMEx_DisableSlaveModePreload
HAL_TIMEx_DisarmBreakInput
HAL_TIMEx_DitheringDisable
HAL_TIMEx_DitheringEnable
HAL_TIMEx_EnableAsymmetricalDeadTime
HAL_TIMEx_EnableDeadTimePreload
HAL_TIMEx_EnableEncoderFirstIndex
HAL_TIMEx_EnableEncoderIndex
HAL_TIMEx_EnableSlaveModePreload
HAL_TIMEx_EncoderIndexCallback
HAL_TIMEx_GetChannelNState
HAL_TIMEx_GroupChannel5
HAL_TIMEx_HallSensor_DeInit
HAL_TIMEx_HallSensor_GetState
HAL_TIMEx_HallSensor_Init
HAL_TIMEx_HallSensor_MspDeInit
HAL_TIMEx_HallSensor_MspInit
HAL_TIMEx_HallSensor_Start
HAL_TIMEx_HallSensor_Start_DMA
HAL_TIMEx_HallSensor_Start_IT
HAL_TIMEx_HallSensor_Stop
HAL_TIMEx_HallSensor_Stop_DMA
HAL_TIMEx_HallSensor_Stop_IT
HAL_TIMEx_IndexErrorCallback
HAL_TIMEx_MasterConfigSynchronization
HAL_TIMEx_OC_ConfigPulseOnCompare
HAL_TIMEx_OCN_Start
HAL_TIMEx_OCN_Start_DMA
HAL_TIMEx_OCN_Start_IT
HAL_TIMEx_OCN_Stop
HAL_TIMEx_OCN_Stop_DMA
HAL_TIMEx_OCN_Stop_IT
HAL_TIMEx_OnePulseN_Start
HAL_TIMEx_OnePulseN_Start_IT
HAL_TIMEx_OnePulseN_Stop
HAL_TIMEx_OnePulseN_Stop_IT
HAL_TIMEx_PWMN_Start
HAL_TIMEx_PWMN_Start_DMA
HAL_TIMEx_PWMN_Start_IT
HAL_TIMEx_PWMN_Stop
HAL_TIMEx_PWMN_Stop_DMA
HAL_TIMEx_PWMN_Stop_IT
HAL_TIMEx_ReArmBreakInput
HAL_TIMEx_RemapConfig
HAL_TIMEx_TISelection
HAL_TIMEx_TransitionErrorCallback
TIMEx_DMACommutationCplt
TIMEx_DMACommutationHalfCplt
stm32g4xx_hal_uart.c
LPUART_BRR_MIN
UART_BRR_MAX
UART_BRR_MIN
USART_CR1_FIELDS
USART_CR3_FIELDS
HAL_HalfDuplex_EnableReceiver
HAL_HalfDuplex_EnableTransmitter
HAL_HalfDuplex_Init
HAL_LIN_Init
HAL_LIN_SendBreak
HAL_MultiProcessor_DisableMuteMode
HAL_MultiProcessor_EnableMuteMode
HAL_MultiProcessor_EnterMuteMode
HAL_MultiProcessor_Init
HAL_UART_Abort
HAL_UART_Abort_IT
HAL_UART_AbortCpltCallback
HAL_UART_AbortReceive
HAL_UART_AbortReceive_IT
HAL_UART_AbortReceiveCpltCallback
HAL_UART_AbortTransmit
HAL_UART_AbortTransmit_IT
HAL_UART_AbortTransmitCpltCallback
HAL_UART_DeInit
HAL_UART_DisableReceiverTimeout
HAL_UART_DMAPause
HAL_UART_DMAResume
HAL_UART_DMAStop
HAL_UART_EnableReceiverTimeout
HAL_UART_ErrorCallback
HAL_UART_GetError
HAL_UART_GetState
HAL_UART_Init
HAL_UART_IRQHandler
HAL_UART_MspDeInit
HAL_UART_MspInit
HAL_UART_Receive
HAL_UART_Receive_DMA
HAL_UART_Receive_IT
HAL_UART_ReceiverTimeout_Config
HAL_UART_RegisterCallback
HAL_UART_RegisterRxEventCallback
HAL_UART_RxCpltCallback
HAL_UART_RxHalfCpltCallback
HAL_UART_Transmit
HAL_UART_Transmit_DMA
HAL_UART_Transmit_IT
HAL_UART_TxCpltCallback
HAL_UART_TxHalfCpltCallback
HAL_UART_UnRegisterCallback
HAL_UART_UnRegisterRxEventCallback
HAL_UARTEx_RxEventCallback
UART_AdvFeatureConfig
UART_CheckIdleState
UART_DMAAbortOnError
UART_DMAError
UART_DMAReceiveCplt
UART_DMARxAbortCallback
UART_DMARxHalfCplt
UART_DMARxOnlyAbortCallback
UART_DMATransmitCplt
UART_DMATxAbortCallback
UART_DMATxHalfCplt
UART_DMATxOnlyAbortCallback
UART_EndRxTransfer
UART_EndTransmit_IT
UART_EndTxTransfer
UART_InitCallbacksToDefault
UART_RxISR_16BIT
UART_RxISR_16BIT_FIFOEN
UART_RxISR_8BIT
UART_RxISR_8BIT_FIFOEN
UART_SetConfig
UART_Start_Receive_DMA
UART_Start_Receive_IT
UART_TxISR_16BIT
UART_TxISR_16BIT_FIFOEN
UART_TxISR_8BIT
UART_TxISR_8BIT_FIFOEN
UART_WaitOnFlagUntilTimeout
UARTPrescTable
stm32g4xx_hal_uart.h
__HAL_UART_CLEAR_FLAG
__HAL_UART_CLEAR_IDLEFLAG
__HAL_UART_CLEAR_IT
__HAL_UART_CLEAR_NEFLAG
__HAL_UART_CLEAR_OREFLAG
__HAL_UART_CLEAR_PEFLAG
__HAL_UART_CLEAR_TXFECF
__HAL_UART_DISABLE
__HAL_UART_DISABLE_IT
__HAL_UART_ENABLE
__HAL_UART_ENABLE_IT
__HAL_UART_FLUSH_DRREGISTER
__HAL_UART_GET_FLAG
__HAL_UART_GET_IT
__HAL_UART_GET_IT_SOURCE
__HAL_UART_HWCONTROL_CTS_DISABLE
__HAL_UART_HWCONTROL_CTS_ENABLE
__HAL_UART_HWCONTROL_RTS_DISABLE
__HAL_UART_HWCONTROL_RTS_ENABLE
__HAL_UART_ONE_BIT_SAMPLE_DISABLE
__HAL_UART_ONE_BIT_SAMPLE_ENABLE
__HAL_UART_RESET_HANDLE_STATE
__HAL_UART_SEND_REQ
HAL_UART_ERROR_DMA
HAL_UART_ERROR_FE
HAL_UART_ERROR_INVALID_CALLBACK
HAL_UART_ERROR_NE
HAL_UART_ERROR_NONE
HAL_UART_ERROR_ORE
HAL_UART_ERROR_PE
HAL_UART_ERROR_RTO
HAL_UART_RECEPTION_STANDARD
HAL_UART_RECEPTION_TOCHARMATCH
HAL_UART_RECEPTION_TOIDLE
HAL_UART_RECEPTION_TORTO
HAL_UART_RXEVENT_HT
HAL_UART_RXEVENT_IDLE
HAL_UART_RXEVENT_TC
HAL_UART_STATE_BUSY
HAL_UART_STATE_BUSY_RX
HAL_UART_STATE_BUSY_TX
HAL_UART_STATE_BUSY_TX_RX
HAL_UART_STATE_ERROR
HAL_UART_STATE_READY
HAL_UART_STATE_RESET
HAL_UART_STATE_TIMEOUT
HAL_UART_TIMEOUT_VALUE
IS_LPUART_STOPBITS
IS_UART_ADVFEATURE_AUTOBAUDRATE
IS_UART_ADVFEATURE_AUTOBAUDRATEMODE
IS_UART_ADVFEATURE_DATAINV
IS_UART_ADVFEATURE_DMAONRXERROR
IS_UART_ADVFEATURE_INIT
IS_UART_ADVFEATURE_MSBFIRST
IS_UART_ADVFEATURE_RXINV
IS_UART_ADVFEATURE_STOPMODE
IS_UART_ADVFEATURE_SWAP
IS_UART_ADVFEATURE_TXINV
IS_UART_ASSERTIONTIME
IS_UART_BAUDRATE
IS_UART_DE_POLARITY
IS_UART_DEASSERTIONTIME
IS_UART_DMA_RX
IS_UART_DMA_TX
IS_UART_HALF_DUPLEX
IS_UART_HARDWARE_FLOW_CONTROL
IS_UART_LIN
IS_UART_LIN_BREAK_DETECT_LENGTH
IS_UART_MODE
IS_UART_MUTE_MODE
IS_UART_ONE_BIT_SAMPLE
IS_UART_OVERRUN
IS_UART_OVERSAMPLING
IS_UART_PARITY
IS_UART_PRESCALER
IS_UART_RECEIVER_TIMEOUT
IS_UART_RECEIVER_TIMEOUT_VALUE
IS_UART_REQUEST_PARAMETER
IS_UART_STATE
IS_UART_STOPBITS
IS_UART_WAKEUP_SELECTION
IS_UART_WAKEUPMETHOD
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
UART_ADVFEATURE_AUTOBAUDRATE_ENABLE
UART_ADVFEATURE_AUTOBAUDRATE_INIT
UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME
UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME
UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE
UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT
UART_ADVFEATURE_DATAINV_DISABLE
UART_ADVFEATURE_DATAINV_ENABLE
UART_ADVFEATURE_DATAINVERT_INIT
UART_ADVFEATURE_DMA_DISABLEONRXERROR
UART_ADVFEATURE_DMA_ENABLEONRXERROR
UART_ADVFEATURE_DMADISABLEONERROR_INIT
UART_ADVFEATURE_MSBFIRST_DISABLE
UART_ADVFEATURE_MSBFIRST_ENABLE
UART_ADVFEATURE_MSBFIRST_INIT
UART_ADVFEATURE_MUTEMODE_DISABLE
UART_ADVFEATURE_MUTEMODE_ENABLE
UART_ADVFEATURE_NO_INIT
UART_ADVFEATURE_OVERRUN_DISABLE
UART_ADVFEATURE_OVERRUN_ENABLE
UART_ADVFEATURE_RXINV_DISABLE
UART_ADVFEATURE_RXINV_ENABLE
UART_ADVFEATURE_RXINVERT_INIT
UART_ADVFEATURE_RXOVERRUNDISABLE_INIT
UART_ADVFEATURE_STOPMODE_DISABLE
UART_ADVFEATURE_STOPMODE_ENABLE
UART_ADVFEATURE_SWAP_DISABLE
UART_ADVFEATURE_SWAP_ENABLE
UART_ADVFEATURE_SWAP_INIT
UART_ADVFEATURE_TXINV_DISABLE
UART_ADVFEATURE_TXINV_ENABLE
UART_ADVFEATURE_TXINVERT_INIT
UART_AUTOBAUD_REQUEST
UART_CLEAR_CMF
UART_CLEAR_CTSF
UART_CLEAR_FEF
UART_CLEAR_IDLEF
UART_CLEAR_LBDF
UART_CLEAR_NEF
UART_CLEAR_OREF
UART_CLEAR_PEF
UART_CLEAR_RTOF
UART_CLEAR_TCF
UART_CLEAR_TXFECF
UART_CLEAR_WUF
UART_CR1_DEAT_ADDRESS_LSB_POS
UART_CR1_DEDT_ADDRESS_LSB_POS
UART_CR2_ADDRESS_LSB_POS
UART_DE_POLARITY_HIGH
UART_DE_POLARITY_LOW
UART_DIV_LPUART
UART_DIV_SAMPLING16
UART_DIV_SAMPLING8
UART_DMA_RX_DISABLE
UART_DMA_RX_ENABLE
UART_DMA_TX_DISABLE
UART_DMA_TX_ENABLE
UART_FLAG_ABRE
UART_FLAG_ABRF
UART_FLAG_BUSY
UART_FLAG_CMF
UART_FLAG_CTS
UART_FLAG_CTSIF
UART_FLAG_FE
UART_FLAG_IDLE
UART_FLAG_LBDF
UART_FLAG_NE
UART_FLAG_ORE
UART_FLAG_PE
UART_FLAG_REACK
UART_FLAG_RTOF
UART_FLAG_RWU
UART_FLAG_RXFF
UART_FLAG_RXFNE
UART_FLAG_RXFT
UART_FLAG_RXNE
UART_FLAG_SBKF
UART_FLAG_TC
UART_FLAG_TEACK
UART_FLAG_TXE
UART_FLAG_TXFE
UART_FLAG_TXFNF
UART_FLAG_TXFT
UART_FLAG_WUF
UART_GET_DIV_FACTOR
UART_HALF_DUPLEX_DISABLE
UART_HALF_DUPLEX_ENABLE
UART_HWCONTROL_CTS
UART_HWCONTROL_NONE
UART_HWCONTROL_RTS
UART_HWCONTROL_RTS_CTS
UART_INSTANCE_LOWPOWER
UART_IT_CM
UART_IT_CTS
UART_IT_ERR
UART_IT_FE
UART_IT_IDLE
UART_IT_LBD
UART_IT_MASK
UART_IT_NE
UART_IT_ORE
UART_IT_PE
UART_IT_RTO
UART_IT_RXFF
UART_IT_RXFNE
UART_IT_RXFT
UART_IT_RXNE
UART_IT_TC
UART_IT_TXE
UART_IT_TXFE
UART_IT_TXFNF
UART_IT_TXFT
UART_IT_WUF
UART_LIN_DISABLE
UART_LIN_ENABLE
UART_LINBREAKDETECTLENGTH_10B
UART_LINBREAKDETECTLENGTH_11B
UART_MODE_RX
UART_MODE_TX
UART_MODE_TX_RX
UART_MUTE_MODE_REQUEST
UART_ONE_BIT_SAMPLE_DISABLE
UART_ONE_BIT_SAMPLE_ENABLE
UART_OVERSAMPLING_16
UART_OVERSAMPLING_8
UART_PARITY_EVEN
UART_PARITY_NONE
UART_PARITY_ODD
UART_PRESCALER_DIV1
UART_PRESCALER_DIV10
UART_PRESCALER_DIV12
UART_PRESCALER_DIV128
UART_PRESCALER_DIV16
UART_PRESCALER_DIV2
UART_PRESCALER_DIV256
UART_PRESCALER_DIV32
UART_PRESCALER_DIV4
UART_PRESCALER_DIV6
UART_PRESCALER_DIV64
UART_PRESCALER_DIV8
UART_RECEIVER_TIMEOUT_DISABLE
UART_RECEIVER_TIMEOUT_ENABLE
UART_RXDATA_FLUSH_REQUEST
UART_SENDBREAK_REQUEST
UART_STATE_DISABLE
UART_STATE_ENABLE
UART_STOPBITS_0_5
UART_STOPBITS_1
UART_STOPBITS_1_5
UART_STOPBITS_2
UART_TXDATA_FLUSH_REQUEST
UART_WAKEUP_ON_ADDRESS
UART_WAKEUP_ON_READDATA_NONEMPTY
UART_WAKEUP_ON_STARTBIT
UART_WAKEUPMETHOD_ADDRESSMARK
UART_WAKEUPMETHOD_IDLELINE
HAL_UART_RxEventTypeTypeDef
HAL_UART_RxTypeTypeDef
HAL_UART_StateTypeDef
pUART_CallbackTypeDef
pUART_RxEventCallbackTypeDef
UART_HandleTypeDef
HAL_UART_CallbackIDTypeDef
UART_ClockSourceTypeDef
HAL_HalfDuplex_EnableReceiver
HAL_HalfDuplex_EnableTransmitter
HAL_HalfDuplex_Init
HAL_LIN_Init
HAL_LIN_SendBreak
HAL_MultiProcessor_DisableMuteMode
HAL_MultiProcessor_EnableMuteMode
HAL_MultiProcessor_EnterMuteMode
HAL_MultiProcessor_Init
HAL_UART_Abort
HAL_UART_Abort_IT
HAL_UART_AbortCpltCallback
HAL_UART_AbortReceive
HAL_UART_AbortReceive_IT
HAL_UART_AbortReceiveCpltCallback
HAL_UART_AbortTransmit
HAL_UART_AbortTransmit_IT
HAL_UART_AbortTransmitCpltCallback
HAL_UART_DeInit
HAL_UART_DisableReceiverTimeout
HAL_UART_DMAPause
HAL_UART_DMAResume
HAL_UART_DMAStop
HAL_UART_EnableReceiverTimeout
HAL_UART_ErrorCallback
HAL_UART_GetError
HAL_UART_GetState
HAL_UART_Init
HAL_UART_IRQHandler
HAL_UART_MspDeInit
HAL_UART_MspInit
HAL_UART_Receive
HAL_UART_Receive_DMA
HAL_UART_Receive_IT
HAL_UART_ReceiverTimeout_Config
HAL_UART_RegisterCallback
HAL_UART_RegisterRxEventCallback
HAL_UART_RxCpltCallback
HAL_UART_RxHalfCpltCallback
HAL_UART_Transmit
HAL_UART_Transmit_DMA
HAL_UART_Transmit_IT
HAL_UART_TxCpltCallback
HAL_UART_TxHalfCpltCallback
HAL_UART_UnRegisterCallback
HAL_UART_UnRegisterRxEventCallback
HAL_UARTEx_RxEventCallback
UART_AdvFeatureConfig
UART_CheckIdleState
UART_InitCallbacksToDefault
UART_SetConfig
UART_Start_Receive_DMA
UART_Start_Receive_IT
UART_WaitOnFlagUntilTimeout
UARTPrescTable
stm32g4xx_hal_uart_ex.c
TX_FIFO_DEPTH
HAL_MultiProcessorEx_AddressLength_Set
HAL_RS485Ex_Init
HAL_UARTEx_DisableFifoMode
HAL_UARTEx_DisableStopMode
HAL_UARTEx_EnableFifoMode
HAL_UARTEx_EnableStopMode
HAL_UARTEx_GetRxEventType
HAL_UARTEx_ReceiveToIdle
HAL_UARTEx_ReceiveToIdle_DMA
HAL_UARTEx_ReceiveToIdle_IT
HAL_UARTEx_RxFifoFullCallback
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_StopModeWakeUpSourceConfig
HAL_UARTEx_TxFifoEmptyCallback
HAL_UARTEx_WakeupCallback
UARTEx_SetNbDataToProcess
UARTEx_Wakeup_AddressConfig
stm32g4xx_hal_uart_ex.h
IS_UART_RXFIFO_THRESHOLD
IS_UART_TXFIFO_THRESHOLD
IS_UART_WORD_LENGTH
UART_ADDRESS_DETECT_4B
UART_ADDRESS_DETECT_7B
UART_FIFOMODE_DISABLE
UART_FIFOMODE_ENABLE
UART_GETCLOCKSOURCE
UART_MASK_COMPUTATION
UART_RXFIFO_THRESHOLD_1_2
UART_RXFIFO_THRESHOLD_1_4
UART_RXFIFO_THRESHOLD_1_8
UART_RXFIFO_THRESHOLD_3_4
UART_RXFIFO_THRESHOLD_7_8
UART_RXFIFO_THRESHOLD_8_8
UART_TXFIFO_THRESHOLD_1_2
UART_TXFIFO_THRESHOLD_1_4
UART_TXFIFO_THRESHOLD_1_8
UART_TXFIFO_THRESHOLD_3_4
UART_TXFIFO_THRESHOLD_7_8
UART_TXFIFO_THRESHOLD_8_8
UART_WORDLENGTH_7B
UART_WORDLENGTH_8B
UART_WORDLENGTH_9B
HAL_MultiProcessorEx_AddressLength_Set
HAL_RS485Ex_Init
HAL_UARTEx_DisableFifoMode
HAL_UARTEx_DisableStopMode
HAL_UARTEx_EnableFifoMode
HAL_UARTEx_EnableStopMode
HAL_UARTEx_GetRxEventType
HAL_UARTEx_ReceiveToIdle
HAL_UARTEx_ReceiveToIdle_DMA
HAL_UARTEx_ReceiveToIdle_IT
HAL_UARTEx_RxFifoFullCallback
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_StopModeWakeUpSourceConfig
HAL_UARTEx_TxFifoEmptyCallback
HAL_UARTEx_WakeupCallback
stm32g4xx_hal_usart.c
USART_BRR_MIN
USART_CR1_FIELDS
USART_CR2_FIELDS
USART_CR3_FIELDS
USART_DUMMY_DATA
USART_TEACK_REACK_TIMEOUT
HAL_USART_Abort
HAL_USART_Abort_IT
HAL_USART_AbortCpltCallback
HAL_USART_DeInit
HAL_USART_DMAPause
HAL_USART_DMAResume
HAL_USART_DMAStop
HAL_USART_ErrorCallback
HAL_USART_GetError
HAL_USART_GetState
HAL_USART_Init
HAL_USART_IRQHandler
HAL_USART_MspDeInit
HAL_USART_MspInit
HAL_USART_Receive
HAL_USART_Receive_DMA
HAL_USART_Receive_IT
HAL_USART_RegisterCallback
HAL_USART_RxCpltCallback
HAL_USART_RxHalfCpltCallback
HAL_USART_Transmit
HAL_USART_Transmit_DMA
HAL_USART_Transmit_IT
HAL_USART_TransmitReceive
HAL_USART_TransmitReceive_DMA
HAL_USART_TransmitReceive_IT
HAL_USART_TxCpltCallback
HAL_USART_TxHalfCpltCallback
HAL_USART_TxRxCpltCallback
HAL_USART_UnRegisterCallback
USART_CheckIdleState
USART_DMAAbortOnError
USART_DMAError
USART_DMAReceiveCplt
USART_DMARxAbortCallback
USART_DMARxHalfCplt
USART_DMATransmitCplt
USART_DMATxAbortCallback
USART_DMATxHalfCplt
USART_EndTransfer
USART_EndTransmit_IT
USART_InitCallbacksToDefault
USART_RxISR_16BIT
USART_RxISR_16BIT_FIFOEN
USART_RxISR_8BIT
USART_RxISR_8BIT_FIFOEN
USART_SetConfig
USART_TxISR_16BIT
USART_TxISR_16BIT_FIFOEN
USART_TxISR_8BIT
USART_TxISR_8BIT_FIFOEN
USART_WaitOnFlagUntilTimeout
stm32g4xx_hal_usart.h
__HAL_USART_CLEAR_FLAG
__HAL_USART_CLEAR_IDLEFLAG
__HAL_USART_CLEAR_IT
__HAL_USART_CLEAR_NEFLAG
__HAL_USART_CLEAR_OREFLAG
__HAL_USART_CLEAR_PEFLAG
__HAL_USART_CLEAR_TXFECF
__HAL_USART_CLEAR_UDRFLAG
__HAL_USART_DISABLE
__HAL_USART_DISABLE_IT
__HAL_USART_ENABLE
__HAL_USART_ENABLE_IT
__HAL_USART_GET_FLAG
__HAL_USART_GET_IT
__HAL_USART_GET_IT_SOURCE
__HAL_USART_ONE_BIT_SAMPLE_DISABLE
__HAL_USART_ONE_BIT_SAMPLE_ENABLE
__HAL_USART_RESET_HANDLE_STATE
__HAL_USART_SEND_REQ
HAL_USART_ERROR_DMA
HAL_USART_ERROR_FE
HAL_USART_ERROR_INVALID_CALLBACK
HAL_USART_ERROR_NE
HAL_USART_ERROR_NONE
HAL_USART_ERROR_ORE
HAL_USART_ERROR_PE
HAL_USART_ERROR_RTO
HAL_USART_ERROR_UDR
IS_USART_BAUDRATE
IS_USART_CLOCK
IS_USART_LASTBIT
IS_USART_MODE
IS_USART_PARITY
IS_USART_PHASE
IS_USART_POLARITY
IS_USART_PRESCALER
IS_USART_REQUEST_PARAMETER
IS_USART_STOPBITS
USART_CLEAR_FEF
USART_CLEAR_IDLEF
USART_CLEAR_NEF
USART_CLEAR_OREF
USART_CLEAR_PEF
USART_CLEAR_RTOF
USART_CLEAR_TCF
USART_CLEAR_TXFECF
USART_CLEAR_UDRF
USART_CLOCK_DISABLE
USART_CLOCK_ENABLE
USART_CR_MASK
USART_CR_POS
USART_DIV_SAMPLING8
USART_FLAG_BUSY
USART_FLAG_FE
USART_FLAG_IDLE
USART_FLAG_NE
USART_FLAG_ORE
USART_FLAG_PE
USART_FLAG_REACK
USART_FLAG_RTOF
USART_FLAG_RXFF
USART_FLAG_RXFNE
USART_FLAG_RXFT
USART_FLAG_RXNE
USART_FLAG_TC
USART_FLAG_TEACK
USART_FLAG_TXE
USART_FLAG_TXFE
USART_FLAG_TXFNF
USART_FLAG_TXFT
USART_FLAG_UDR
USART_GET_DIV_FACTOR
USART_GETCLOCKSOURCE
USART_ISR_MASK
USART_ISR_POS
USART_IT_ERR
USART_IT_FE
USART_IT_IDLE
USART_IT_MASK
USART_IT_NE
USART_IT_ORE
USART_IT_PE
USART_IT_RXFF
USART_IT_RXFNE
USART_IT_RXFT
USART_IT_RXNE
USART_IT_TC
USART_IT_TXE
USART_IT_TXFE
USART_IT_TXFNF
USART_IT_TXFT
USART_LASTBIT_DISABLE
USART_LASTBIT_ENABLE
USART_MODE_RX
USART_MODE_TX
USART_MODE_TX_RX
USART_PARITY_EVEN
USART_PARITY_NONE
USART_PARITY_ODD
USART_PHASE_1EDGE
USART_PHASE_2EDGE
USART_POLARITY_HIGH
USART_POLARITY_LOW
USART_PRESCALER_DIV1
USART_PRESCALER_DIV10
USART_PRESCALER_DIV12
USART_PRESCALER_DIV128
USART_PRESCALER_DIV16
USART_PRESCALER_DIV2
USART_PRESCALER_DIV256
USART_PRESCALER_DIV32
USART_PRESCALER_DIV4
USART_PRESCALER_DIV6
USART_PRESCALER_DIV64
USART_PRESCALER_DIV8
USART_RXDATA_FLUSH_REQUEST
USART_STOPBITS_0_5
USART_STOPBITS_1
USART_STOPBITS_1_5
USART_STOPBITS_2
USART_TXDATA_FLUSH_REQUEST
pUSART_CallbackTypeDef
USART_HandleTypeDef
HAL_USART_CallbackIDTypeDef
HAL_USART_StateTypeDef
USART_ClockSourceTypeDef
HAL_USART_Abort
HAL_USART_Abort_IT
HAL_USART_AbortCpltCallback
HAL_USART_DeInit
HAL_USART_DMAPause
HAL_USART_DMAResume
HAL_USART_DMAStop
HAL_USART_ErrorCallback
HAL_USART_GetError
HAL_USART_GetState
HAL_USART_Init
HAL_USART_IRQHandler
HAL_USART_MspDeInit
HAL_USART_MspInit
HAL_USART_Receive
HAL_USART_Receive_DMA
HAL_USART_Receive_IT
HAL_USART_RegisterCallback
HAL_USART_RxCpltCallback
HAL_USART_RxHalfCpltCallback
HAL_USART_Transmit
HAL_USART_Transmit_DMA
HAL_USART_Transmit_IT
HAL_USART_TransmitReceive
HAL_USART_TransmitReceive_DMA
HAL_USART_TransmitReceive_IT
HAL_USART_TxCpltCallback
HAL_USART_TxHalfCpltCallback
HAL_USART_TxRxCpltCallback
HAL_USART_UnRegisterCallback
stm32g4xx_hal_usart_ex.c
TX_FIFO_DEPTH
HAL_USARTEx_ConfigNSS
HAL_USARTEx_DisableFifoMode
HAL_USARTEx_DisableSlaveMode
HAL_USARTEx_EnableFifoMode
HAL_USARTEx_EnableSlaveMode
HAL_USARTEx_RxFifoFullCallback
HAL_USARTEx_SetRxFifoThreshold
HAL_USARTEx_SetTxFifoThreshold
HAL_USARTEx_TxFifoEmptyCallback
USARTEx_SetNbDataToProcess
stm32g4xx_hal_usart_ex.h
IS_USART_NSS
IS_USART_RXFIFO_THRESHOLD
IS_USART_SLAVEMODE
IS_USART_TXFIFO_THRESHOLD
IS_USART_WORD_LENGTH
USART_FIFOMODE_DISABLE
USART_FIFOMODE_ENABLE
USART_MASK_COMPUTATION
USART_NSS_HARD
USART_NSS_SOFT
USART_RXFIFO_THRESHOLD_1_2
USART_RXFIFO_THRESHOLD_1_4
USART_RXFIFO_THRESHOLD_1_8
USART_RXFIFO_THRESHOLD_3_4
USART_RXFIFO_THRESHOLD_7_8
USART_RXFIFO_THRESHOLD_8_8
USART_SLAVEMODE_DISABLE
USART_SLAVEMODE_ENABLE
USART_TXFIFO_THRESHOLD_1_2
USART_TXFIFO_THRESHOLD_1_4
USART_TXFIFO_THRESHOLD_1_8
USART_TXFIFO_THRESHOLD_3_4
USART_TXFIFO_THRESHOLD_7_8
USART_TXFIFO_THRESHOLD_8_8
USART_WORDLENGTH_7B
USART_WORDLENGTH_8B
USART_WORDLENGTH_9B
HAL_USARTEx_ConfigNSS
HAL_USARTEx_DisableFifoMode
HAL_USARTEx_DisableSlaveMode
HAL_USARTEx_EnableFifoMode
HAL_USARTEx_EnableSlaveMode
HAL_USARTEx_RxFifoFullCallback
HAL_USARTEx_SetRxFifoThreshold
HAL_USARTEx_SetTxFifoThreshold
HAL_USARTEx_TxFifoEmptyCallback
stm32g4xx_hal_wwdg.c
HAL_WWDG_Init
HAL_WWDG_IRQHandler
HAL_WWDG_MspInit
HAL_WWDG_Refresh
HAL_WWDG_RegisterCallback
HAL_WWDG_UnRegisterCallback
stm32g4xx_hal_wwdg.h
__HAL_WWDG_CLEAR_IT
__HAL_WWDG_ENABLE
__HAL_WWDG_ENABLE_IT
__HAL_WWDG_GET_FLAG
__HAL_WWDG_GET_IT
__HAL_WWDG_GET_IT_SOURCE
IS_WWDG_COUNTER
IS_WWDG_EWI_MODE
IS_WWDG_PRESCALER
IS_WWDG_WINDOW
WWDG_EWI_DISABLE
WWDG_EWI_ENABLE
WWDG_FLAG_EWIF
WWDG_IT_EWI
WWDG_PRESCALER_1
WWDG_PRESCALER_128
WWDG_PRESCALER_16
WWDG_PRESCALER_2
WWDG_PRESCALER_32
WWDG_PRESCALER_4
WWDG_PRESCALER_64
WWDG_PRESCALER_8
pWWDG_CallbackTypeDef
WWDG_HandleTypeDef
HAL_WWDG_CallbackIDTypeDef
HAL_WWDG_EarlyWakeupCallback
HAL_WWDG_Init
HAL_WWDG_IRQHandler
HAL_WWDG_MspInit
HAL_WWDG_Refresh
HAL_WWDG_RegisterCallback
HAL_WWDG_UnRegisterCallback
stm32g4xx_ll_adc.c
ADC_TIMEOUT_DISABLE_CPU_CYCLES
ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES
assert_param
IS_LL_ADC_COMMON_CLOCK
IS_LL_ADC_DATA_ALIGN
IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE
IS_LL_ADC_INJ_SEQ_SCAN_LENGTH
IS_LL_ADC_INJ_TRIG_AUTO
IS_LL_ADC_INJ_TRIG_EXT_EDGE
IS_LL_ADC_INJ_TRIG_SOURCE
IS_LL_ADC_LOW_POWER
IS_LL_ADC_MULTI_DMA_TRANSFER
IS_LL_ADC_MULTI_MASTER_SLAVE
IS_LL_ADC_MULTI_MODE
IS_LL_ADC_MULTI_TWOSMP_DELAY
IS_LL_ADC_REG_CONTINUOUS_MODE
IS_LL_ADC_REG_DMA_TRANSFER
IS_LL_ADC_REG_OVR_DATA_BEHAVIOR
IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE
IS_LL_ADC_REG_SEQ_SCAN_LENGTH
IS_LL_ADC_REG_TRIG_SOURCE
IS_LL_ADC_RESOLUTION
LL_ADC_CommonDeInit
LL_ADC_CommonInit
LL_ADC_CommonStructInit
LL_ADC_DeInit
LL_ADC_Init
LL_ADC_INJ_Init
LL_ADC_INJ_StructInit
LL_ADC_REG_Init
LL_ADC_REG_StructInit
LL_ADC_StructInit
stm32g4xx_ll_adc.h
__LL_ADC_ANALOGWD_CHANNEL_GROUP
__LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
__LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION
__LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW
__LL_ADC_CALC_DATA_TO_VOLTAGE
__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE
__LL_ADC_CALC_TEMPERATURE
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS
__LL_ADC_CALC_VREFANALOG_VOLTAGE
__LL_ADC_CALIB_FACTOR_SINGLE_DIFF
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL
__LL_ADC_CHANNEL_TO_DECIMAL_NB
__LL_ADC_COMMON_INSTANCE
__LL_ADC_CONVERT_DATA_RESOLUTION
__LL_ADC_DECIMAL_NB_TO_CHANNEL
__LL_ADC_DIGITAL_SCALE
__LL_ADC_IS_CHANNEL_INTERNAL
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE
__LL_ADC_MULTI_INSTANCE_MASTER
ADC_AWD_CR12_REGOFFSETGAP_MASK
ADC_AWD_CR12_REGOFFSETGAP_VAL
ADC_AWD_CR1_CHANNEL_MASK
ADC_AWD_CR1_REGOFFSET
ADC_AWD_CR23_CHANNEL_MASK
ADC_AWD_CR2_REGOFFSET
ADC_AWD_CR3_REGOFFSET
ADC_AWD_CR_ALL_CHANNEL_MASK
ADC_AWD_CRX_REGOFFSET_MASK
ADC_AWD_CRX_REGOFFSET_POS
ADC_AWD_TR1_REGOFFSET
ADC_AWD_TR2_REGOFFSET
ADC_AWD_TR3_REGOFFSET
ADC_AWD_TRX_BIT_HIGH_MASK
ADC_AWD_TRX_BIT_HIGH_POS
ADC_AWD_TRX_BIT_HIGH_SHIFT4
ADC_AWD_TRX_REGOFFSET_MASK
ADC_AWD_TRX_REGOFFSET_POS
ADC_CFGR_AWD1EN_BITOFFSET_POS
ADC_CFGR_AWD1SGL_BITOFFSET_POS
ADC_CFGR_JAWD1EN_BITOFFSET_POS
ADC_CFGR_RES_BITOFFSET_POS
ADC_CHANNEL_0_BITFIELD
ADC_CHANNEL_0_NUMBER
ADC_CHANNEL_0_SMP
ADC_CHANNEL_10_BITFIELD
ADC_CHANNEL_10_NUMBER
ADC_CHANNEL_10_SMP
ADC_CHANNEL_11_BITFIELD
ADC_CHANNEL_11_NUMBER
ADC_CHANNEL_11_SMP
ADC_CHANNEL_12_BITFIELD
ADC_CHANNEL_12_NUMBER
ADC_CHANNEL_12_SMP
ADC_CHANNEL_13_BITFIELD
ADC_CHANNEL_13_NUMBER
ADC_CHANNEL_13_SMP
ADC_CHANNEL_14_BITFIELD
ADC_CHANNEL_14_NUMBER
ADC_CHANNEL_14_SMP
ADC_CHANNEL_15_BITFIELD
ADC_CHANNEL_15_NUMBER
ADC_CHANNEL_15_SMP
ADC_CHANNEL_16_BITFIELD
ADC_CHANNEL_16_NUMBER
ADC_CHANNEL_16_SMP
ADC_CHANNEL_17_BITFIELD
ADC_CHANNEL_17_NUMBER
ADC_CHANNEL_17_SMP
ADC_CHANNEL_18_BITFIELD
ADC_CHANNEL_18_NUMBER
ADC_CHANNEL_18_SMP
ADC_CHANNEL_1_BITFIELD
ADC_CHANNEL_1_NUMBER
ADC_CHANNEL_1_SMP
ADC_CHANNEL_2_BITFIELD
ADC_CHANNEL_2_NUMBER
ADC_CHANNEL_2_SMP
ADC_CHANNEL_3_BITFIELD
ADC_CHANNEL_3_NUMBER
ADC_CHANNEL_3_SMP
ADC_CHANNEL_4_BITFIELD
ADC_CHANNEL_4_NUMBER
ADC_CHANNEL_4_SMP
ADC_CHANNEL_5_BITFIELD
ADC_CHANNEL_5_NUMBER
ADC_CHANNEL_5_SMP
ADC_CHANNEL_6_BITFIELD
ADC_CHANNEL_6_NUMBER
ADC_CHANNEL_6_SMP
ADC_CHANNEL_7_BITFIELD
ADC_CHANNEL_7_NUMBER
ADC_CHANNEL_7_SMP
ADC_CHANNEL_8_BITFIELD
ADC_CHANNEL_8_NUMBER
ADC_CHANNEL_8_SMP
ADC_CHANNEL_9_BITFIELD
ADC_CHANNEL_9_NUMBER
ADC_CHANNEL_9_SMP
ADC_CHANNEL_ID_BITFIELD_MASK
ADC_CHANNEL_ID_INTERNAL_CH
ADC_CHANNEL_ID_INTERNAL_CH_2
ADC_CHANNEL_ID_INTERNAL_CH_MASK
ADC_CHANNEL_ID_MASK
ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
ADC_CHANNEL_ID_NUMBER_MASK
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0
ADC_CHANNEL_SMPRX_REGOFFSET_MASK
ADC_CHANNEL_SMPx_BITOFFSET_MASK
ADC_CHANNEL_SMPx_BITOFFSET_POS
ADC_CR_BITS_PROPERTY_RS
ADC_INJ_JDRX_REGOFFSET_MASK
ADC_INJ_RANK_1_JSQR_BITOFFSET_POS
ADC_INJ_RANK_2_JSQR_BITOFFSET_POS
ADC_INJ_RANK_3_JSQR_BITOFFSET_POS
ADC_INJ_RANK_4_JSQR_BITOFFSET_POS
ADC_INJ_RANK_ID_JSQR_MASK
ADC_INJ_TRIG_EDGE_MASK
ADC_INJ_TRIG_EXT_EDGE_DEFAULT
ADC_INJ_TRIG_EXTEN_BITOFFSET_POS
ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS
ADC_INJ_TRIG_SOURCE_MASK
ADC_JDR1_REGOFFSET
ADC_JDR2_REGOFFSET
ADC_JDR3_REGOFFSET
ADC_JDR4_REGOFFSET
ADC_JDRX_REGOFFSET_POS
ADC_OFR1_REGOFFSET
ADC_OFR2_REGOFFSET
ADC_OFR3_REGOFFSET
ADC_OFR4_REGOFFSET
ADC_OFRx_REGOFFSET_MASK
ADC_REG_RANK_10_SQRX_BITOFFSET_POS
ADC_REG_RANK_11_SQRX_BITOFFSET_POS
ADC_REG_RANK_12_SQRX_BITOFFSET_POS
ADC_REG_RANK_13_SQRX_BITOFFSET_POS
ADC_REG_RANK_14_SQRX_BITOFFSET_POS
ADC_REG_RANK_15_SQRX_BITOFFSET_POS
ADC_REG_RANK_16_SQRX_BITOFFSET_POS
ADC_REG_RANK_1_SQRX_BITOFFSET_POS
ADC_REG_RANK_2_SQRX_BITOFFSET_POS
ADC_REG_RANK_3_SQRX_BITOFFSET_POS
ADC_REG_RANK_4_SQRX_BITOFFSET_POS
ADC_REG_RANK_5_SQRX_BITOFFSET_POS
ADC_REG_RANK_6_SQRX_BITOFFSET_POS
ADC_REG_RANK_7_SQRX_BITOFFSET_POS
ADC_REG_RANK_8_SQRX_BITOFFSET_POS
ADC_REG_RANK_9_SQRX_BITOFFSET_POS
ADC_REG_RANK_ID_SQRX_MASK
ADC_REG_SQRX_REGOFFSET_MASK
ADC_REG_TRIG_EDGE_MASK
ADC_REG_TRIG_EXT_EDGE_DEFAULT
ADC_REG_TRIG_EXTEN_BITOFFSET_POS
ADC_REG_TRIG_EXTSEL_BITOFFSET_POS
ADC_REG_TRIG_SOURCE_MASK
ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK
ADC_SINGLEDIFF_CALIB_F_BIT_D_POS
ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4
ADC_SINGLEDIFF_CALIB_FACTOR_MASK
ADC_SINGLEDIFF_CALIB_START_MASK
ADC_SINGLEDIFF_CHANNEL_MASK
ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK
ADC_SMPR1_REGOFFSET
ADC_SMPR2_REGOFFSET
ADC_SMPRX_REGOFFSET_POS
ADC_SQR1_REGOFFSET
ADC_SQR2_REGOFFSET
ADC_SQR3_REGOFFSET
ADC_SQR4_REGOFFSET
ADC_SQRX_REGOFFSET_POS
ADC_TR1_HT1_BITOFFSET_POS
LL_ADC_AWD1
LL_ADC_AWD2
LL_ADC_AWD3
LL_ADC_AWD_ALL_CHANNELS_INJ
LL_ADC_AWD_ALL_CHANNELS_REG
LL_ADC_AWD_ALL_CHANNELS_REG_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG
LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG
LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ
LL_ADC_AWD_CH_VBAT_INJ
LL_ADC_AWD_CH_VBAT_REG
LL_ADC_AWD_CH_VBAT_REG_INJ
LL_ADC_AWD_CH_VOPAMP1_INJ
LL_ADC_AWD_CH_VOPAMP1_REG
LL_ADC_AWD_CH_VOPAMP1_REG_INJ
LL_ADC_AWD_CH_VOPAMP2_INJ
LL_ADC_AWD_CH_VOPAMP2_REG
LL_ADC_AWD_CH_VOPAMP2_REG_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC2_REG
LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ
LL_ADC_AWD_CH_VOPAMP3_ADC3_REG
LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ
LL_ADC_AWD_CH_VOPAMP4_INJ
LL_ADC_AWD_CH_VOPAMP4_REG
LL_ADC_AWD_CH_VOPAMP4_REG_INJ
LL_ADC_AWD_CH_VOPAMP5_INJ
LL_ADC_AWD_CH_VOPAMP5_REG
LL_ADC_AWD_CH_VOPAMP5_REG_INJ
LL_ADC_AWD_CH_VOPAMP6_INJ
LL_ADC_AWD_CH_VOPAMP6_REG
LL_ADC_AWD_CH_VOPAMP6_REG_INJ
LL_ADC_AWD_CH_VREFINT_INJ
LL_ADC_AWD_CH_VREFINT_REG
LL_ADC_AWD_CH_VREFINT_REG_INJ
LL_ADC_AWD_CHANNEL_0_INJ
LL_ADC_AWD_CHANNEL_0_REG
LL_ADC_AWD_CHANNEL_0_REG_INJ
LL_ADC_AWD_CHANNEL_10_INJ
LL_ADC_AWD_CHANNEL_10_REG
LL_ADC_AWD_CHANNEL_10_REG_INJ
LL_ADC_AWD_CHANNEL_11_INJ
LL_ADC_AWD_CHANNEL_11_REG
LL_ADC_AWD_CHANNEL_11_REG_INJ
LL_ADC_AWD_CHANNEL_12_INJ
LL_ADC_AWD_CHANNEL_12_REG
LL_ADC_AWD_CHANNEL_12_REG_INJ
LL_ADC_AWD_CHANNEL_13_INJ
LL_ADC_AWD_CHANNEL_13_REG
LL_ADC_AWD_CHANNEL_13_REG_INJ
LL_ADC_AWD_CHANNEL_14_INJ
LL_ADC_AWD_CHANNEL_14_REG
LL_ADC_AWD_CHANNEL_14_REG_INJ
LL_ADC_AWD_CHANNEL_15_INJ
LL_ADC_AWD_CHANNEL_15_REG
LL_ADC_AWD_CHANNEL_15_REG_INJ
LL_ADC_AWD_CHANNEL_16_INJ
LL_ADC_AWD_CHANNEL_16_REG
LL_ADC_AWD_CHANNEL_16_REG_INJ
LL_ADC_AWD_CHANNEL_17_INJ
LL_ADC_AWD_CHANNEL_17_REG
LL_ADC_AWD_CHANNEL_17_REG_INJ
LL_ADC_AWD_CHANNEL_18_INJ
LL_ADC_AWD_CHANNEL_18_REG
LL_ADC_AWD_CHANNEL_18_REG_INJ
LL_ADC_AWD_CHANNEL_1_INJ
LL_ADC_AWD_CHANNEL_1_REG
LL_ADC_AWD_CHANNEL_1_REG_INJ
LL_ADC_AWD_CHANNEL_2_INJ
LL_ADC_AWD_CHANNEL_2_REG
LL_ADC_AWD_CHANNEL_2_REG_INJ
LL_ADC_AWD_CHANNEL_3_INJ
LL_ADC_AWD_CHANNEL_3_REG
LL_ADC_AWD_CHANNEL_3_REG_INJ
LL_ADC_AWD_CHANNEL_4_INJ
LL_ADC_AWD_CHANNEL_4_REG
LL_ADC_AWD_CHANNEL_4_REG_INJ
LL_ADC_AWD_CHANNEL_5_INJ
LL_ADC_AWD_CHANNEL_5_REG
LL_ADC_AWD_CHANNEL_5_REG_INJ
LL_ADC_AWD_CHANNEL_6_INJ
LL_ADC_AWD_CHANNEL_6_REG
LL_ADC_AWD_CHANNEL_6_REG_INJ
LL_ADC_AWD_CHANNEL_7_INJ
LL_ADC_AWD_CHANNEL_7_REG
LL_ADC_AWD_CHANNEL_7_REG_INJ
LL_ADC_AWD_CHANNEL_8_INJ
LL_ADC_AWD_CHANNEL_8_REG
LL_ADC_AWD_CHANNEL_8_REG_INJ
LL_ADC_AWD_CHANNEL_9_INJ
LL_ADC_AWD_CHANNEL_9_REG
LL_ADC_AWD_CHANNEL_9_REG_INJ
LL_ADC_AWD_DISABLE
LL_ADC_AWD_FILTERING_2SAMPLES
LL_ADC_AWD_FILTERING_3SAMPLES
LL_ADC_AWD_FILTERING_4SAMPLES
LL_ADC_AWD_FILTERING_5SAMPLES
LL_ADC_AWD_FILTERING_6SAMPLES
LL_ADC_AWD_FILTERING_7SAMPLES
LL_ADC_AWD_FILTERING_8SAMPLES
LL_ADC_AWD_FILTERING_NONE
LL_ADC_AWD_THRESHOLD_HIGH
LL_ADC_AWD_THRESHOLD_LOW
LL_ADC_AWD_THRESHOLDS_HIGH_LOW
LL_ADC_BOTH_SINGLE_DIFF_ENDED
LL_ADC_CHANNEL_0
LL_ADC_CHANNEL_1
LL_ADC_CHANNEL_10
LL_ADC_CHANNEL_11
LL_ADC_CHANNEL_12
LL_ADC_CHANNEL_13
LL_ADC_CHANNEL_14
LL_ADC_CHANNEL_15
LL_ADC_CHANNEL_16
LL_ADC_CHANNEL_17
LL_ADC_CHANNEL_18
LL_ADC_CHANNEL_2
LL_ADC_CHANNEL_3
LL_ADC_CHANNEL_4
LL_ADC_CHANNEL_5
LL_ADC_CHANNEL_6
LL_ADC_CHANNEL_7
LL_ADC_CHANNEL_8
LL_ADC_CHANNEL_9
LL_ADC_CHANNEL_TEMPSENSOR_ADC1
LL_ADC_CHANNEL_TEMPSENSOR_ADC5
LL_ADC_CHANNEL_VBAT
LL_ADC_CHANNEL_VOPAMP1
LL_ADC_CHANNEL_VOPAMP2
LL_ADC_CHANNEL_VOPAMP3_ADC2
LL_ADC_CHANNEL_VOPAMP3_ADC3
LL_ADC_CHANNEL_VOPAMP4
LL_ADC_CHANNEL_VOPAMP5
LL_ADC_CHANNEL_VOPAMP6
LL_ADC_CHANNEL_VREFINT
LL_ADC_CLOCK_ASYNC_DIV1
LL_ADC_CLOCK_ASYNC_DIV10
LL_ADC_CLOCK_ASYNC_DIV12
LL_ADC_CLOCK_ASYNC_DIV128
LL_ADC_CLOCK_ASYNC_DIV16
LL_ADC_CLOCK_ASYNC_DIV2
LL_ADC_CLOCK_ASYNC_DIV256
LL_ADC_CLOCK_ASYNC_DIV32
LL_ADC_CLOCK_ASYNC_DIV4
LL_ADC_CLOCK_ASYNC_DIV6
LL_ADC_CLOCK_ASYNC_DIV64
LL_ADC_CLOCK_ASYNC_DIV8
LL_ADC_CLOCK_SYNC_PCLK_DIV1
LL_ADC_CLOCK_SYNC_PCLK_DIV2
LL_ADC_CLOCK_SYNC_PCLK_DIV4
LL_ADC_DATA_ALIGN_LEFT
LL_ADC_DATA_ALIGN_RIGHT
LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES
LL_ADC_DELAY_INTERNAL_REGUL_STAB_US
LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US
LL_ADC_DELAY_TEMPSENSOR_STAB_US
LL_ADC_DELAY_VREFINT_STAB_US
LL_ADC_DIFFERENTIAL_ENDED
LL_ADC_DMA_REG_REGULAR_DATA
LL_ADC_DMA_REG_REGULAR_DATA_MULTI
LL_ADC_FLAG_ADRDY
LL_ADC_FLAG_ADRDY_MST
LL_ADC_FLAG_ADRDY_SLV
LL_ADC_FLAG_AWD1
LL_ADC_FLAG_AWD1_MST
LL_ADC_FLAG_AWD1_SLV
LL_ADC_FLAG_AWD2
LL_ADC_FLAG_AWD2_MST
LL_ADC_FLAG_AWD2_SLV
LL_ADC_FLAG_AWD3
LL_ADC_FLAG_AWD3_MST
LL_ADC_FLAG_AWD3_SLV
LL_ADC_FLAG_EOC
LL_ADC_FLAG_EOC_MST
LL_ADC_FLAG_EOC_SLV
LL_ADC_FLAG_EOS
LL_ADC_FLAG_EOS_MST
LL_ADC_FLAG_EOS_SLV
LL_ADC_FLAG_EOSMP
LL_ADC_FLAG_EOSMP_MST
LL_ADC_FLAG_EOSMP_SLV
LL_ADC_FLAG_JEOC
LL_ADC_FLAG_JEOC_MST
LL_ADC_FLAG_JEOC_SLV
LL_ADC_FLAG_JEOS
LL_ADC_FLAG_JEOS_MST
LL_ADC_FLAG_JEOS_SLV
LL_ADC_FLAG_JQOVF
LL_ADC_FLAG_JQOVF_MST
LL_ADC_FLAG_JQOVF_SLV
LL_ADC_FLAG_OVR
LL_ADC_FLAG_OVR_MST
LL_ADC_FLAG_OVR_SLV
LL_ADC_GROUP_INJECTED
LL_ADC_GROUP_REGULAR
LL_ADC_GROUP_REGULAR_INJECTED
LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
LL_ADC_INJ_QUEUE_DISABLE
LL_ADC_INJ_RANK_1
LL_ADC_INJ_RANK_2
LL_ADC_INJ_RANK_3
LL_ADC_INJ_RANK_4
LL_ADC_INJ_SEQ_DISCONT_1RANK
LL_ADC_INJ_SEQ_DISCONT_DISABLE
LL_ADC_INJ_SEQ_SCAN_DISABLE
LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
LL_ADC_INJ_TRIG_EXT_EXTI_LINE3
LL_ADC_INJ_TRIG_EXT_FALLING
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
LL_ADC_INJ_TRIG_EXT_RISING
LL_ADC_INJ_TRIG_EXT_RISINGFALLING
LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
LL_ADC_INJ_TRIG_EXT_TIM16_CH1
LL_ADC_INJ_TRIG_EXT_TIM1_CH3
LL_ADC_INJ_TRIG_EXT_TIM1_CH4
LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
LL_ADC_INJ_TRIG_EXT_TIM20_CH2
LL_ADC_INJ_TRIG_EXT_TIM20_CH4
LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
LL_ADC_INJ_TRIG_EXT_TIM2_CH1
LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
LL_ADC_INJ_TRIG_EXT_TIM3_CH1
LL_ADC_INJ_TRIG_EXT_TIM3_CH3
LL_ADC_INJ_TRIG_EXT_TIM3_CH4
LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
LL_ADC_INJ_TRIG_EXT_TIM4_CH3
LL_ADC_INJ_TRIG_EXT_TIM4_CH4
LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
LL_ADC_INJ_TRIG_EXT_TIM8_CH2
LL_ADC_INJ_TRIG_EXT_TIM8_CH4
LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
LL_ADC_INJ_TRIG_INDEPENDENT
LL_ADC_INJ_TRIG_SOFTWARE
LL_ADC_IT_ADRDY
LL_ADC_IT_AWD1
LL_ADC_IT_AWD2
LL_ADC_IT_AWD3
LL_ADC_IT_EOC
LL_ADC_IT_EOS
LL_ADC_IT_EOSMP
LL_ADC_IT_JEOC
LL_ADC_IT_JEOS
LL_ADC_IT_JQOVF
LL_ADC_IT_OVR
LL_ADC_LP_AUTOWAIT
LL_ADC_LP_MODE_NONE
LL_ADC_MULTI_DUAL_INJ_ALTERN
LL_ADC_MULTI_DUAL_INJ_SIMULT
LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
LL_ADC_MULTI_DUAL_REG_INTERL
LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
LL_ADC_MULTI_DUAL_REG_SIMULT
LL_ADC_MULTI_INDEPENDENT
LL_ADC_MULTI_MASTER
LL_ADC_MULTI_MASTER_SLAVE
LL_ADC_MULTI_REG_DMA_EACH_ADC
LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
LL_ADC_MULTI_SLAVE
LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
LL_ADC_OFFSET_1
LL_ADC_OFFSET_2
LL_ADC_OFFSET_3
LL_ADC_OFFSET_4
LL_ADC_OFFSET_DISABLE
LL_ADC_OFFSET_ENABLE
LL_ADC_OFFSET_SATURATION_DISABLE
LL_ADC_OFFSET_SATURATION_ENABLE
LL_ADC_OFFSET_SIGN_NEGATIVE
LL_ADC_OFFSET_SIGN_POSITIVE
LL_ADC_OVS_DISABLE
LL_ADC_OVS_GRP_INJ_REG_RESUMED
LL_ADC_OVS_GRP_INJECTED
LL_ADC_OVS_GRP_REGULAR_CONTINUED
LL_ADC_OVS_GRP_REGULAR_RESUMED
LL_ADC_OVS_RATIO_128
LL_ADC_OVS_RATIO_16
LL_ADC_OVS_RATIO_2
LL_ADC_OVS_RATIO_256
LL_ADC_OVS_RATIO_32
LL_ADC_OVS_RATIO_4
LL_ADC_OVS_RATIO_64
LL_ADC_OVS_RATIO_8
LL_ADC_OVS_REG_CONT
LL_ADC_OVS_REG_DISCONT
LL_ADC_OVS_SHIFT_NONE
LL_ADC_OVS_SHIFT_RIGHT_1
LL_ADC_OVS_SHIFT_RIGHT_2
LL_ADC_OVS_SHIFT_RIGHT_3
LL_ADC_OVS_SHIFT_RIGHT_4
LL_ADC_OVS_SHIFT_RIGHT_5
LL_ADC_OVS_SHIFT_RIGHT_6
LL_ADC_OVS_SHIFT_RIGHT_7
LL_ADC_OVS_SHIFT_RIGHT_8
LL_ADC_PATH_INTERNAL_NONE
LL_ADC_PATH_INTERNAL_TEMPSENSOR
LL_ADC_PATH_INTERNAL_VBAT
LL_ADC_PATH_INTERNAL_VREFINT
LL_ADC_ReadReg
LL_ADC_REG_CONV_CONTINUOUS
LL_ADC_REG_CONV_SINGLE
LL_ADC_REG_DMA_TRANSFER_LIMITED
LL_ADC_REG_DMA_TRANSFER_NONE
LL_ADC_REG_DMA_TRANSFER_UNLIMITED
LL_ADC_REG_OVR_DATA_OVERWRITTEN
LL_ADC_REG_OVR_DATA_PRESERVED
LL_ADC_REG_RANK_1
LL_ADC_REG_RANK_10
LL_ADC_REG_RANK_11
LL_ADC_REG_RANK_12
LL_ADC_REG_RANK_13
LL_ADC_REG_RANK_14
LL_ADC_REG_RANK_15
LL_ADC_REG_RANK_16
LL_ADC_REG_RANK_2
LL_ADC_REG_RANK_3
LL_ADC_REG_RANK_4
LL_ADC_REG_RANK_5
LL_ADC_REG_RANK_6
LL_ADC_REG_RANK_7
LL_ADC_REG_RANK_8
LL_ADC_REG_RANK_9
LL_ADC_REG_SAMPLING_MODE_BULB
LL_ADC_REG_SAMPLING_MODE_NORMAL
LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
LL_ADC_REG_SEQ_DISCONT_1RANK
LL_ADC_REG_SEQ_DISCONT_2RANKS
LL_ADC_REG_SEQ_DISCONT_3RANKS
LL_ADC_REG_SEQ_DISCONT_4RANKS
LL_ADC_REG_SEQ_DISCONT_5RANKS
LL_ADC_REG_SEQ_DISCONT_6RANKS
LL_ADC_REG_SEQ_DISCONT_7RANKS
LL_ADC_REG_SEQ_DISCONT_8RANKS
LL_ADC_REG_SEQ_DISCONT_DISABLE
LL_ADC_REG_SEQ_SCAN_DISABLE
LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
LL_ADC_REG_TRIG_EXT_EXTI_LINE11
LL_ADC_REG_TRIG_EXT_EXTI_LINE2
LL_ADC_REG_TRIG_EXT_FALLING
LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
LL_ADC_REG_TRIG_EXT_HRTIM_TRG2
LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
LL_ADC_REG_TRIG_EXT_HRTIM_TRG4
LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
LL_ADC_REG_TRIG_EXT_LPTIM_OUT
LL_ADC_REG_TRIG_EXT_RISING
LL_ADC_REG_TRIG_EXT_RISINGFALLING
LL_ADC_REG_TRIG_EXT_TIM15_TRGO
LL_ADC_REG_TRIG_EXT_TIM1_CH1
LL_ADC_REG_TRIG_EXT_TIM1_CH2
LL_ADC_REG_TRIG_EXT_TIM1_CH3
LL_ADC_REG_TRIG_EXT_TIM1_TRGO
LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
LL_ADC_REG_TRIG_EXT_TIM20_CH1
LL_ADC_REG_TRIG_EXT_TIM20_CH2
LL_ADC_REG_TRIG_EXT_TIM20_CH3
LL_ADC_REG_TRIG_EXT_TIM20_TRGO
LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
LL_ADC_REG_TRIG_EXT_TIM2_CH1
LL_ADC_REG_TRIG_EXT_TIM2_CH2
LL_ADC_REG_TRIG_EXT_TIM2_CH3
LL_ADC_REG_TRIG_EXT_TIM2_TRGO
LL_ADC_REG_TRIG_EXT_TIM3_CH1
LL_ADC_REG_TRIG_EXT_TIM3_CH4
LL_ADC_REG_TRIG_EXT_TIM3_TRGO
LL_ADC_REG_TRIG_EXT_TIM4_CH1
LL_ADC_REG_TRIG_EXT_TIM4_CH4
LL_ADC_REG_TRIG_EXT_TIM4_TRGO
LL_ADC_REG_TRIG_EXT_TIM6_TRGO
LL_ADC_REG_TRIG_EXT_TIM7_TRGO
LL_ADC_REG_TRIG_EXT_TIM8_CH1
LL_ADC_REG_TRIG_EXT_TIM8_TRGO
LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
LL_ADC_REG_TRIG_SOFTWARE
LL_ADC_RESOLUTION_10B
LL_ADC_RESOLUTION_12B
LL_ADC_RESOLUTION_6B
LL_ADC_RESOLUTION_8B
LL_ADC_SAMPLINGTIME_12CYCLES_5
LL_ADC_SAMPLINGTIME_247CYCLES_5
LL_ADC_SAMPLINGTIME_24CYCLES_5
LL_ADC_SAMPLINGTIME_2CYCLES_5
LL_ADC_SAMPLINGTIME_47CYCLES_5
LL_ADC_SAMPLINGTIME_640CYCLES_5
LL_ADC_SAMPLINGTIME_6CYCLES_5
LL_ADC_SAMPLINGTIME_92CYCLES_5
LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
LL_ADC_SINGLE_ENDED
LL_ADC_TEMPERATURE_CALC_ERROR
LL_ADC_WriteReg
TEMPSENSOR_CAL1_ADDR
TEMPSENSOR_CAL1_TEMP
TEMPSENSOR_CAL2_ADDR
TEMPSENSOR_CAL2_TEMP
TEMPSENSOR_CAL_VREFANALOG
VREFINT_CAL_ADDR
VREFINT_CAL_VREF
LL_ADC_ClearFlag_ADRDY
LL_ADC_ClearFlag_AWD1
LL_ADC_ClearFlag_AWD2
LL_ADC_ClearFlag_AWD3
LL_ADC_ClearFlag_EOC
LL_ADC_ClearFlag_EOS
LL_ADC_ClearFlag_EOSMP
LL_ADC_ClearFlag_JEOC
LL_ADC_ClearFlag_JEOS
LL_ADC_ClearFlag_JQOVF
LL_ADC_ClearFlag_OVR
LL_ADC_CommonDeInit
LL_ADC_CommonInit
LL_ADC_CommonStructInit
LL_ADC_ConfigAnalogWDThresholds
LL_ADC_ConfigOverSamplingRatioShift
LL_ADC_DeInit
LL_ADC_Disable
LL_ADC_DisableDeepPowerDown
LL_ADC_DisableInternalRegulator
LL_ADC_DisableIT_ADRDY
LL_ADC_DisableIT_AWD1
LL_ADC_DisableIT_AWD2
LL_ADC_DisableIT_AWD3
LL_ADC_DisableIT_EOC
LL_ADC_DisableIT_EOS
LL_ADC_DisableIT_EOSMP
LL_ADC_DisableIT_JEOC
LL_ADC_DisableIT_JEOS
LL_ADC_DisableIT_JQOVF
LL_ADC_DisableIT_OVR
LL_ADC_DMA_GetRegAddr
LL_ADC_Enable
LL_ADC_EnableDeepPowerDown
LL_ADC_EnableInternalRegulator
LL_ADC_EnableIT_ADRDY
LL_ADC_EnableIT_AWD1
LL_ADC_EnableIT_AWD2
LL_ADC_EnableIT_AWD3
LL_ADC_EnableIT_EOC
LL_ADC_EnableIT_EOS
LL_ADC_EnableIT_EOSMP
LL_ADC_EnableIT_JEOC
LL_ADC_EnableIT_JEOS
LL_ADC_EnableIT_JQOVF
LL_ADC_EnableIT_OVR
LL_ADC_GetAnalogWDMonitChannels
LL_ADC_GetAnalogWDThresholds
LL_ADC_GetAWDFilteringConfiguration
LL_ADC_GetCalibrationFactor
LL_ADC_GetChannelSamplingTime
LL_ADC_GetChannelSingleDiff
LL_ADC_GetCommonClock
LL_ADC_GetCommonPathInternalCh
LL_ADC_GetDataAlignment
LL_ADC_GetGainCompensation
LL_ADC_GetLowPowerMode
LL_ADC_GetMultiDMATransfer
LL_ADC_GetMultimode
LL_ADC_GetMultiTwoSamplingDelay
LL_ADC_GetOffsetChannel
LL_ADC_GetOffsetLevel
LL_ADC_GetOffsetSaturation
LL_ADC_GetOffsetSign
LL_ADC_GetOffsetState
LL_ADC_GetOverSamplingDiscont
LL_ADC_GetOverSamplingRatio
LL_ADC_GetOverSamplingScope
LL_ADC_GetOverSamplingShift
LL_ADC_GetResolution
LL_ADC_GetSamplingTimeCommonConfig
LL_ADC_Init
LL_ADC_INJ_ConfigQueueContext
LL_ADC_INJ_GetQueueMode
LL_ADC_INJ_GetSequencerDiscont
LL_ADC_INJ_GetSequencerLength
LL_ADC_INJ_GetSequencerRanks
LL_ADC_INJ_GetTrigAuto
LL_ADC_INJ_GetTriggerEdge
LL_ADC_INJ_GetTriggerSource
LL_ADC_INJ_Init
LL_ADC_INJ_IsConversionOngoing
LL_ADC_INJ_IsStopConversionOngoing
LL_ADC_INJ_IsTriggerSourceSWStart
LL_ADC_INJ_ReadConversionData10
LL_ADC_INJ_ReadConversionData12
LL_ADC_INJ_ReadConversionData32
LL_ADC_INJ_ReadConversionData6
LL_ADC_INJ_ReadConversionData8
LL_ADC_INJ_SetQueueMode
LL_ADC_INJ_SetSequencerDiscont
LL_ADC_INJ_SetSequencerLength
LL_ADC_INJ_SetSequencerRanks
LL_ADC_INJ_SetTrigAuto
LL_ADC_INJ_SetTriggerEdge
LL_ADC_INJ_SetTriggerSource
LL_ADC_INJ_StartConversion
LL_ADC_INJ_StopConversion
LL_ADC_INJ_StructInit
LL_ADC_IsActiveFlag_ADRDY
LL_ADC_IsActiveFlag_AWD1
LL_ADC_IsActiveFlag_AWD2
LL_ADC_IsActiveFlag_AWD3
LL_ADC_IsActiveFlag_EOC
LL_ADC_IsActiveFlag_EOS
LL_ADC_IsActiveFlag_EOSMP
LL_ADC_IsActiveFlag_JEOC
LL_ADC_IsActiveFlag_JEOS
LL_ADC_IsActiveFlag_JQOVF
LL_ADC_IsActiveFlag_MST_ADRDY
LL_ADC_IsActiveFlag_MST_AWD1
LL_ADC_IsActiveFlag_MST_AWD2
LL_ADC_IsActiveFlag_MST_AWD3
LL_ADC_IsActiveFlag_MST_EOC
LL_ADC_IsActiveFlag_MST_EOS
LL_ADC_IsActiveFlag_MST_EOSMP
LL_ADC_IsActiveFlag_MST_JEOC
LL_ADC_IsActiveFlag_MST_JEOS
LL_ADC_IsActiveFlag_MST_JQOVF
LL_ADC_IsActiveFlag_MST_OVR
LL_ADC_IsActiveFlag_OVR
LL_ADC_IsActiveFlag_SLV_ADRDY
LL_ADC_IsActiveFlag_SLV_AWD1
LL_ADC_IsActiveFlag_SLV_AWD2
LL_ADC_IsActiveFlag_SLV_AWD3
LL_ADC_IsActiveFlag_SLV_EOC
LL_ADC_IsActiveFlag_SLV_EOS
LL_ADC_IsActiveFlag_SLV_EOSMP
LL_ADC_IsActiveFlag_SLV_JEOC
LL_ADC_IsActiveFlag_SLV_JEOS
LL_ADC_IsActiveFlag_SLV_JQOVF
LL_ADC_IsActiveFlag_SLV_OVR
LL_ADC_IsCalibrationOnGoing
LL_ADC_IsDeepPowerDownEnabled
LL_ADC_IsDisableOngoing
LL_ADC_IsEnabled
LL_ADC_IsEnabledIT_ADRDY
LL_ADC_IsEnabledIT_AWD1
LL_ADC_IsEnabledIT_AWD2
LL_ADC_IsEnabledIT_AWD3
LL_ADC_IsEnabledIT_EOC
LL_ADC_IsEnabledIT_EOS
LL_ADC_IsEnabledIT_EOSMP
LL_ADC_IsEnabledIT_JEOC
LL_ADC_IsEnabledIT_JEOS
LL_ADC_IsEnabledIT_JQOVF
LL_ADC_IsEnabledIT_OVR
LL_ADC_IsInternalRegulatorEnabled
LL_ADC_REG_GetContinuousMode
LL_ADC_REG_GetDMATransfer
LL_ADC_REG_GetOverrun
LL_ADC_REG_GetSamplingMode
LL_ADC_REG_GetSequencerDiscont
LL_ADC_REG_GetSequencerLength
LL_ADC_REG_GetSequencerRanks
LL_ADC_REG_GetTriggerEdge
LL_ADC_REG_GetTriggerSource
LL_ADC_REG_Init
LL_ADC_REG_IsConversionOngoing
LL_ADC_REG_IsStopConversionOngoing
LL_ADC_REG_IsTriggerSourceSWStart
LL_ADC_REG_ReadConversionData10
LL_ADC_REG_ReadConversionData12
LL_ADC_REG_ReadConversionData32
LL_ADC_REG_ReadConversionData6
LL_ADC_REG_ReadConversionData8
LL_ADC_REG_ReadMultiConversionData32
LL_ADC_REG_SetContinuousMode
LL_ADC_REG_SetDMATransfer
LL_ADC_REG_SetOverrun
LL_ADC_REG_SetSamplingMode
LL_ADC_REG_SetSequencerDiscont
LL_ADC_REG_SetSequencerLength
LL_ADC_REG_SetSequencerRanks
LL_ADC_REG_SetTriggerEdge
LL_ADC_REG_SetTriggerSource
LL_ADC_REG_StartConversion
LL_ADC_REG_StartSamplingPhase
LL_ADC_REG_StopConversion
LL_ADC_REG_StopSamplingPhase
LL_ADC_REG_StructInit
LL_ADC_SetAnalogWDMonitChannels
LL_ADC_SetAnalogWDThresholds
LL_ADC_SetAWDFilteringConfiguration
LL_ADC_SetCalibrationFactor
LL_ADC_SetChannelSamplingTime
LL_ADC_SetChannelSingleDiff
LL_ADC_SetCommonClock
LL_ADC_SetCommonPathInternalCh
LL_ADC_SetCommonPathInternalChAdd
LL_ADC_SetCommonPathInternalChRem
LL_ADC_SetDataAlignment
LL_ADC_SetGainCompensation
LL_ADC_SetLowPowerMode
LL_ADC_SetMultiDMATransfer
LL_ADC_SetMultimode
LL_ADC_SetMultiTwoSamplingDelay
LL_ADC_SetOffset
LL_ADC_SetOffsetSaturation
LL_ADC_SetOffsetSign
LL_ADC_SetOffsetState
LL_ADC_SetOverSamplingDiscont
LL_ADC_SetOverSamplingScope
LL_ADC_SetResolution
LL_ADC_SetSamplingTimeCommonConfig
LL_ADC_StartCalibration
LL_ADC_StructInit
stm32g4xx_ll_bus.h
LL_AHB1_GRP1_PERIPH_CORDIC
LL_AHB1_GRP1_PERIPH_CRC
LL_AHB1_GRP1_PERIPH_DMA1
LL_AHB1_GRP1_PERIPH_DMA2
LL_AHB1_GRP1_PERIPH_DMAMUX1
LL_AHB1_GRP1_PERIPH_FLASH
LL_AHB1_GRP1_PERIPH_FMAC
LL_AHB1_GRP1_PERIPH_SRAM1
LL_AHB2_GRP1_PERIPH_ADC12
LL_AHB2_GRP1_PERIPH_ADC345
LL_AHB2_GRP1_PERIPH_ALL
LL_AHB2_GRP1_PERIPH_CCM
LL_AHB2_GRP1_PERIPH_DAC1
LL_AHB2_GRP1_PERIPH_DAC2
LL_AHB2_GRP1_PERIPH_DAC3
LL_AHB2_GRP1_PERIPH_DAC4
LL_AHB2_GRP1_PERIPH_GPIOA
LL_AHB2_GRP1_PERIPH_GPIOB
LL_AHB2_GRP1_PERIPH_GPIOC
LL_AHB2_GRP1_PERIPH_GPIOD
LL_AHB2_GRP1_PERIPH_GPIOE
LL_AHB2_GRP1_PERIPH_GPIOF
LL_AHB2_GRP1_PERIPH_GPIOG
LL_AHB2_GRP1_PERIPH_RNG
LL_AHB2_GRP1_PERIPH_SRAM2
LL_AHB3_GRP1_PERIPH_ALL
LL_AHB3_GRP1_PERIPH_FMC
LL_AHB3_GRP1_PERIPH_QSPI
LL_APB1_GRP1_PERIPH_ALL
LL_APB1_GRP1_PERIPH_CRS
LL_APB1_GRP1_PERIPH_FDCAN
LL_APB1_GRP1_PERIPH_I2C1
LL_APB1_GRP1_PERIPH_I2C2
LL_APB1_GRP1_PERIPH_I2C3
LL_APB1_GRP1_PERIPH_LPTIM1
LL_APB1_GRP1_PERIPH_PWR
LL_APB1_GRP1_PERIPH_RTCAPB
LL_APB1_GRP1_PERIPH_SPI2
LL_APB1_GRP1_PERIPH_SPI3
LL_APB1_GRP1_PERIPH_TIM2
LL_APB1_GRP1_PERIPH_TIM3
LL_APB1_GRP1_PERIPH_TIM4
LL_APB1_GRP1_PERIPH_TIM5
LL_APB1_GRP1_PERIPH_TIM6
LL_APB1_GRP1_PERIPH_TIM7
LL_APB1_GRP1_PERIPH_UART4
LL_APB1_GRP1_PERIPH_UART5
LL_APB1_GRP1_PERIPH_USART2
LL_APB1_GRP1_PERIPH_USART3
LL_APB1_GRP1_PERIPH_USB
LL_APB1_GRP1_PERIPH_WWDG
LL_APB1_GRP2_PERIPH_ALL
LL_APB1_GRP2_PERIPH_I2C4
LL_APB1_GRP2_PERIPH_LPUART1
LL_APB1_GRP2_PERIPH_UCPD1
LL_APB2_GRP1_PERIPH_ALL
LL_APB2_GRP1_PERIPH_HRTIM1
LL_APB2_GRP1_PERIPH_SAI1
LL_APB2_GRP1_PERIPH_SPI1
LL_APB2_GRP1_PERIPH_SPI4
LL_APB2_GRP1_PERIPH_SYSCFG
LL_APB2_GRP1_PERIPH_TIM1
LL_APB2_GRP1_PERIPH_TIM15
LL_APB2_GRP1_PERIPH_TIM16
LL_APB2_GRP1_PERIPH_TIM17
LL_APB2_GRP1_PERIPH_TIM20
LL_APB2_GRP1_PERIPH_TIM8
LL_APB2_GRP1_PERIPH_USART1
LL_AHB1_GRP1_DisableClock
LL_AHB1_GRP1_DisableClockStopSleep
LL_AHB1_GRP1_EnableClock
LL_AHB1_GRP1_EnableClockStopSleep
LL_AHB1_GRP1_ForceReset
LL_AHB1_GRP1_IsEnabledClock
LL_AHB1_GRP1_ReleaseReset
LL_AHB2_GRP1_DisableClock
LL_AHB2_GRP1_DisableClockStopSleep
LL_AHB2_GRP1_EnableClock
LL_AHB2_GRP1_EnableClockStopSleep
LL_AHB2_GRP1_ForceReset
LL_AHB2_GRP1_IsEnabledClock
LL_AHB2_GRP1_ReleaseReset
LL_AHB3_GRP1_DisableClock
LL_AHB3_GRP1_DisableClockStopSleep
LL_AHB3_GRP1_EnableClock
LL_AHB3_GRP1_EnableClockStopSleep
LL_AHB3_GRP1_ForceReset
LL_AHB3_GRP1_IsEnabledClock
LL_AHB3_GRP1_ReleaseReset
LL_APB1_GRP1_DisableClock
LL_APB1_GRP1_DisableClockStopSleep
LL_APB1_GRP1_EnableClock
LL_APB1_GRP1_EnableClockStopSleep
LL_APB1_GRP1_ForceReset
LL_APB1_GRP1_IsEnabledClock
LL_APB1_GRP1_ReleaseReset
LL_APB1_GRP2_DisableClock
LL_APB1_GRP2_DisableClockStopSleep
LL_APB1_GRP2_EnableClock
LL_APB1_GRP2_EnableClockStopSleep
LL_APB1_GRP2_ForceReset
LL_APB1_GRP2_IsEnabledClock
LL_APB1_GRP2_ReleaseReset
LL_APB2_GRP1_DisableClock
LL_APB2_GRP1_DisableClockStopSleep
LL_APB2_GRP1_EnableClock
LL_APB2_GRP1_EnableClockStopSleep
LL_APB2_GRP1_ForceReset
LL_APB2_GRP1_IsEnabledClock
LL_APB2_GRP1_ReleaseReset
stm32g4xx_ll_comp.c
IS_LL_COMP_INPUT_HYSTERESIS
IS_LL_COMP_INPUT_MINUS
IS_LL_COMP_INPUT_PLUS
IS_LL_COMP_OUTPUT_BLANKING_SOURCE
IS_LL_COMP_OUTPUT_POLARITY
LL_COMP_DeInit
LL_COMP_Init
LL_COMP_StructInit
stm32g4xx_ll_comp.h
LL_COMP_BLANKINGSRC_TIM15_OC1
LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
LL_COMP_BLANKINGSRC_TIM20_OC5
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
LL_COMP_BLANKINGSRC_TIM4_OC3
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
LL_COMP_DELAY_STARTUP_US
LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US
LL_COMP_HYSTERESIS_10MV
LL_COMP_HYSTERESIS_20MV
LL_COMP_HYSTERESIS_30MV
LL_COMP_HYSTERESIS_40MV
LL_COMP_HYSTERESIS_50MV
LL_COMP_HYSTERESIS_60MV
LL_COMP_HYSTERESIS_70MV
LL_COMP_HYSTERESIS_HIGH
LL_COMP_HYSTERESIS_LOW
LL_COMP_HYSTERESIS_MEDIUM
LL_COMP_HYSTERESIS_NONE
LL_COMP_INPUT_MINUS_1_2VREFINT
LL_COMP_INPUT_MINUS_1_4VREFINT
LL_COMP_INPUT_MINUS_3_4VREFINT
LL_COMP_INPUT_MINUS_DAC1_CH1
LL_COMP_INPUT_MINUS_DAC1_CH2
LL_COMP_INPUT_MINUS_DAC2_CH1
LL_COMP_INPUT_MINUS_DAC3_CH1
LL_COMP_INPUT_MINUS_DAC3_CH2
LL_COMP_INPUT_MINUS_DAC4_CH1
LL_COMP_INPUT_MINUS_DAC4_CH2
LL_COMP_INPUT_MINUS_IO1
LL_COMP_INPUT_MINUS_IO2
LL_COMP_INPUT_MINUS_VREFINT
LL_COMP_INPUT_PLUS_IO1
LL_COMP_INPUT_PLUS_IO2
LL_COMP_OUTPUT_LEVEL_HIGH
LL_COMP_OUTPUT_LEVEL_LOW
LL_COMP_OUTPUTPOL_INVERTED
LL_COMP_OUTPUTPOL_NONINVERTED
LL_COMP_ReadReg
LL_COMP_WriteReg
LL_COMP_ConfigInputs
LL_COMP_DeInit
LL_COMP_Disable
LL_COMP_Enable
LL_COMP_GetInputHysteresis
LL_COMP_GetInputMinus
LL_COMP_GetInputPlus
LL_COMP_GetOutputBlankingSource
LL_COMP_GetOutputPolarity
LL_COMP_Init
LL_COMP_IsEnabled
LL_COMP_IsLocked
LL_COMP_Lock
LL_COMP_ReadOutputLevel
LL_COMP_SetInputHysteresis
LL_COMP_SetInputMinus
LL_COMP_SetInputPlus
LL_COMP_SetOutputBlankingSource
LL_COMP_SetOutputPolarity
LL_COMP_StructInit
stm32g4xx_ll_cordic.c
LL_CORDIC_DeInit
stm32g4xx_ll_cordic.h
LL_CORDIC_DMA_REG_DATA_OUT
LL_CORDIC_FLAG_RRDY
LL_CORDIC_FUNCTION_ARCTANGENT
LL_CORDIC_FUNCTION_COSINE
LL_CORDIC_FUNCTION_HARCTANGENT
LL_CORDIC_FUNCTION_HCOSINE
LL_CORDIC_FUNCTION_HSINE
LL_CORDIC_FUNCTION_MODULUS
LL_CORDIC_FUNCTION_NATURALLOG
LL_CORDIC_FUNCTION_PHASE
LL_CORDIC_FUNCTION_SINE
LL_CORDIC_FUNCTION_SQUAREROOT
LL_CORDIC_INSIZE_16BITS
LL_CORDIC_INSIZE_32BITS
LL_CORDIC_IT_IEN
LL_CORDIC_NBREAD_1
LL_CORDIC_NBREAD_2
LL_CORDIC_NBWRITE_1
LL_CORDIC_NBWRITE_2
LL_CORDIC_OUTSIZE_16BITS
LL_CORDIC_OUTSIZE_32BITS
LL_CORDIC_PRECISION_10CYCLES
LL_CORDIC_PRECISION_11CYCLES
LL_CORDIC_PRECISION_12CYCLES
LL_CORDIC_PRECISION_13CYCLES
LL_CORDIC_PRECISION_14CYCLES
LL_CORDIC_PRECISION_15CYCLES
LL_CORDIC_PRECISION_1CYCLE
LL_CORDIC_PRECISION_2CYCLES
LL_CORDIC_PRECISION_3CYCLES
LL_CORDIC_PRECISION_4CYCLES
LL_CORDIC_PRECISION_5CYCLES
LL_CORDIC_PRECISION_6CYCLES
LL_CORDIC_PRECISION_7CYCLES
LL_CORDIC_PRECISION_8CYCLES
LL_CORDIC_PRECISION_9CYCLES
LL_CORDIC_ReadReg
LL_CORDIC_SCALE_0
LL_CORDIC_SCALE_1
LL_CORDIC_SCALE_2
LL_CORDIC_SCALE_3
LL_CORDIC_SCALE_4
LL_CORDIC_SCALE_5
LL_CORDIC_SCALE_6
LL_CORDIC_SCALE_7
LL_CORDIC_WriteReg
LL_CORDIC_Config
LL_CORDIC_DeInit
LL_CORDIC_DisableDMAReq_RD
LL_CORDIC_DisableDMAReq_WR
LL_CORDIC_DisableIT
LL_CORDIC_DMA_GetRegAddr
LL_CORDIC_EnableDMAReq_RD
LL_CORDIC_EnableDMAReq_WR
LL_CORDIC_EnableIT
LL_CORDIC_GetFunction
LL_CORDIC_GetInSize
LL_CORDIC_GetNbRead
LL_CORDIC_GetNbWrite
LL_CORDIC_GetOutSize
LL_CORDIC_GetPrecision
LL_CORDIC_GetScale
LL_CORDIC_IsActiveFlag_RRDY
LL_CORDIC_IsEnabledDMAReq_RD
LL_CORDIC_IsEnabledDMAReq_WR
LL_CORDIC_IsEnabledIT
LL_CORDIC_ReadData
LL_CORDIC_SetFunction
LL_CORDIC_SetInSize
LL_CORDIC_SetNbRead
LL_CORDIC_SetNbWrite
LL_CORDIC_SetOutSize
LL_CORDIC_SetPrecision
LL_CORDIC_SetScale
LL_CORDIC_WriteData
stm32g4xx_ll_cortex.h
LL_HANDLER_FAULT_MEM
LL_HANDLER_FAULT_USG
LL_MPU_ACCESS_BUFFERABLE
LL_MPU_ACCESS_CACHEABLE
LL_MPU_ACCESS_NOT_BUFFERABLE
LL_MPU_ACCESS_NOT_CACHEABLE
LL_MPU_ACCESS_NOT_SHAREABLE
LL_MPU_ACCESS_SHAREABLE
LL_MPU_CTRL_HARDFAULT_NMI
LL_MPU_CTRL_HFNMI_PRIVDEF
LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
LL_MPU_CTRL_PRIVILEGED_DEFAULT
LL_MPU_INSTRUCTION_ACCESS_DISABLE
LL_MPU_INSTRUCTION_ACCESS_ENABLE
LL_MPU_REGION_FULL_ACCESS
LL_MPU_REGION_NO_ACCESS
LL_MPU_REGION_NUMBER0
LL_MPU_REGION_NUMBER1
LL_MPU_REGION_NUMBER2
LL_MPU_REGION_NUMBER3
LL_MPU_REGION_NUMBER4
LL_MPU_REGION_NUMBER5
LL_MPU_REGION_NUMBER6
LL_MPU_REGION_NUMBER7
LL_MPU_REGION_PRIV_RO
LL_MPU_REGION_PRIV_RO_URO
LL_MPU_REGION_PRIV_RW
LL_MPU_REGION_PRIV_RW_URO
LL_MPU_REGION_SIZE_128B
LL_MPU_REGION_SIZE_128KB
LL_MPU_REGION_SIZE_128MB
LL_MPU_REGION_SIZE_16KB
LL_MPU_REGION_SIZE_16MB
LL_MPU_REGION_SIZE_1GB
LL_MPU_REGION_SIZE_1KB
LL_MPU_REGION_SIZE_1MB
LL_MPU_REGION_SIZE_256B
LL_MPU_REGION_SIZE_256KB
LL_MPU_REGION_SIZE_256MB
LL_MPU_REGION_SIZE_2GB
LL_MPU_REGION_SIZE_2KB
LL_MPU_REGION_SIZE_2MB
LL_MPU_REGION_SIZE_32B
LL_MPU_REGION_SIZE_32KB
LL_MPU_REGION_SIZE_32MB
LL_MPU_REGION_SIZE_4GB
LL_MPU_REGION_SIZE_4KB
LL_MPU_REGION_SIZE_4MB
LL_MPU_REGION_SIZE_512B
LL_MPU_REGION_SIZE_512KB
LL_MPU_REGION_SIZE_512MB
LL_MPU_REGION_SIZE_64B
LL_MPU_REGION_SIZE_64KB
LL_MPU_REGION_SIZE_64MB
LL_MPU_REGION_SIZE_8KB
LL_MPU_REGION_SIZE_8MB
LL_MPU_TEX_LEVEL0
LL_MPU_TEX_LEVEL1
LL_MPU_TEX_LEVEL2
LL_MPU_TEX_LEVEL4
LL_SYSTICK_CLKSOURCE_HCLK
LL_SYSTICK_CLKSOURCE_HCLK_DIV8
LL_CPUID_GetArchitecture
LL_CPUID_GetImplementer
LL_CPUID_GetParNo
LL_CPUID_GetRevision
LL_CPUID_GetVariant
LL_HANDLER_DisableFault
LL_HANDLER_EnableFault
LL_LPM_DisableEventOnPend
LL_LPM_DisableSleepOnExit
LL_LPM_EnableDeepSleep
LL_LPM_EnableEventOnPend
LL_LPM_EnableSleep
LL_LPM_EnableSleepOnExit
LL_MPU_ConfigRegion
LL_MPU_Disable
LL_MPU_DisableRegion
LL_MPU_Enable
LL_MPU_EnableRegion
LL_MPU_IsEnabled
LL_SYSTICK_DisableIT
LL_SYSTICK_EnableIT
LL_SYSTICK_GetClkSource
LL_SYSTICK_IsActiveCounterFlag
LL_SYSTICK_IsEnabledIT
LL_SYSTICK_SetClkSource
stm32g4xx_ll_crc.c
LL_CRC_DeInit
stm32g4xx_ll_crc.h
LL_CRC_DEFAULT_CRC_INITVALUE
LL_CRC_INDATA_REVERSE_BYTE
LL_CRC_INDATA_REVERSE_HALFWORD
LL_CRC_INDATA_REVERSE_NONE
LL_CRC_INDATA_REVERSE_WORD
LL_CRC_OUTDATA_REVERSE_BIT
LL_CRC_OUTDATA_REVERSE_NONE
LL_CRC_POLYLENGTH_16B
LL_CRC_POLYLENGTH_32B
LL_CRC_POLYLENGTH_7B
LL_CRC_POLYLENGTH_8B
LL_CRC_ReadReg
LL_CRC_WriteReg
LL_CRC_DeInit
LL_CRC_FeedData16
LL_CRC_FeedData32
LL_CRC_FeedData8
LL_CRC_GetInitialData
LL_CRC_GetInputDataReverseMode
LL_CRC_GetOutputDataReverseMode
LL_CRC_GetPolynomialCoef
LL_CRC_GetPolynomialSize
LL_CRC_Read_IDR
LL_CRC_ReadData16
LL_CRC_ReadData32
LL_CRC_ReadData7
LL_CRC_ReadData8
LL_CRC_ResetCRCCalculationUnit
LL_CRC_SetInitialData
LL_CRC_SetInputDataReverseMode
LL_CRC_SetOutputDataReverseMode
LL_CRC_SetPolynomialCoef
LL_CRC_SetPolynomialSize
LL_CRC_Write_IDR
stm32g4xx_ll_crs.c
stm32g4xx_ll_crs.h
LL_CRS_CR_ERRIE
LL_CRS_CR_ESYNCIE
LL_CRS_CR_SYNCOKIE
LL_CRS_CR_SYNCWARNIE
LL_CRS_ERRORLIMIT_DEFAULT
LL_CRS_FREQ_ERROR_DIR_DOWN
LL_CRS_FREQ_ERROR_DIR_UP
LL_CRS_HSI48CALIBRATION_DEFAULT
LL_CRS_ISR_ERRF
LL_CRS_ISR_ESYNCF
LL_CRS_ISR_SYNCERR
LL_CRS_ISR_SYNCMISS
LL_CRS_ISR_SYNCOKF
LL_CRS_ISR_SYNCWARNF
LL_CRS_ISR_TRIMOVF
LL_CRS_ReadReg
LL_CRS_RELOADVALUE_DEFAULT
LL_CRS_SYNC_DIV_1
LL_CRS_SYNC_DIV_128
LL_CRS_SYNC_DIV_16
LL_CRS_SYNC_DIV_2
LL_CRS_SYNC_DIV_32
LL_CRS_SYNC_DIV_4
LL_CRS_SYNC_DIV_64
LL_CRS_SYNC_DIV_8
LL_CRS_SYNC_POLARITY_FALLING
LL_CRS_SYNC_POLARITY_RISING
LL_CRS_SYNC_SOURCE_GPIO
LL_CRS_SYNC_SOURCE_LSE
LL_CRS_SYNC_SOURCE_USB
LL_CRS_WriteReg
LL_CRS_ClearFlag_ERR
LL_CRS_ClearFlag_ESYNC
LL_CRS_ClearFlag_SYNCOK
LL_CRS_ClearFlag_SYNCWARN
LL_CRS_ConfigSynchronization
LL_CRS_DeInit
LL_CRS_DisableAutoTrimming
LL_CRS_DisableFreqErrorCounter
LL_CRS_DisableIT_ERR
LL_CRS_DisableIT_ESYNC
LL_CRS_DisableIT_SYNCOK
LL_CRS_DisableIT_SYNCWARN
LL_CRS_EnableAutoTrimming
LL_CRS_EnableFreqErrorCounter
LL_CRS_EnableIT_ERR
LL_CRS_EnableIT_ESYNC
LL_CRS_EnableIT_SYNCOK
LL_CRS_EnableIT_SYNCWARN
LL_CRS_GenerateEvent_SWSYNC
LL_CRS_GetFreqErrorCapture
LL_CRS_GetFreqErrorDirection
LL_CRS_GetFreqErrorLimit
LL_CRS_GetHSI48SmoothTrimming
LL_CRS_GetReloadCounter
LL_CRS_GetSyncDivider
LL_CRS_GetSyncPolarity
LL_CRS_GetSyncSignalSource
LL_CRS_IsActiveFlag_ERR
LL_CRS_IsActiveFlag_ESYNC
LL_CRS_IsActiveFlag_SYNCERR
LL_CRS_IsActiveFlag_SYNCMISS
LL_CRS_IsActiveFlag_SYNCOK
LL_CRS_IsActiveFlag_SYNCWARN
LL_CRS_IsActiveFlag_TRIMOVF
LL_CRS_IsEnabledAutoTrimming
LL_CRS_IsEnabledFreqErrorCounter
LL_CRS_IsEnabledIT_ERR
LL_CRS_IsEnabledIT_ESYNC
LL_CRS_IsEnabledIT_SYNCOK
LL_CRS_IsEnabledIT_SYNCWARN
LL_CRS_SetFreqErrorLimit
LL_CRS_SetHSI48SmoothTrimming
LL_CRS_SetReloadCounter
LL_CRS_SetSyncDivider
LL_CRS_SetSyncPolarity
LL_CRS_SetSyncSignalSource
stm32g4xx_ll_dac.c
IS_LL_DAC_CHANNEL
IS_LL_DAC_OUTPUT_BUFFER
IS_LL_DAC_OUTPUT_CONNECTION
IS_LL_DAC_OUTPUT_MODE
IS_LL_DAC_TRIGGER_SOURCE
IS_LL_DAC_TRIGGER_SOURCE2
IS_LL_DAC_WAVE_AUTO_GENER_CONFIG
IS_LL_DAC_WAVE_AUTO_GENER_MODE
LL_DAC_DeInit
LL_DAC_Init
LL_DAC_StructInit
stm32g4xx_ll_dac.h
__LL_DAC_CALC_VOLTAGE_TO_DATA
__LL_DAC_CHANNEL_TO_DECIMAL_NB
__LL_DAC_DECIMAL_NB_TO_CHANNEL
__LL_DAC_DIGITAL_SCALE
__LL_DAC_FORMAT_SAWTOOTHWAVECONFIG
DAC_CR_CH1_BITOFFSET
DAC_CR_CH2_BITOFFSET
DAC_CR_CHX_BITOFFSET_MASK
DAC_DHR12LD_DACC2DHR_BITOFFSET_POS
DAC_DHR12RD_DACC2DHR_BITOFFSET_POS
DAC_DHR8RD_DACC2DHR_BITOFFSET_POS
DAC_DIGITAL_SCALE_12BITS
DAC_REG_DHR12L1_REGOFFSET
DAC_REG_DHR12L2_REGOFFSET
DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR12LX_REGOFFSET_MASK
DAC_REG_DHR12R1_REGOFFSET
DAC_REG_DHR12R2_REGOFFSET
DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR12RX_REGOFFSET_MASK
DAC_REG_DHR8R1_REGOFFSET
DAC_REG_DHR8R2_REGOFFSET
DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
DAC_REG_DHR8RX_REGOFFSET_MASK
DAC_REG_DHR_REGOFFSET_MASK_POSBIT0
DAC_REG_DHRX_REGOFFSET_MASK
DAC_REG_DOR1_REGOFFSET
DAC_REG_DOR2_REGOFFSET
DAC_REG_DORX_REGOFFSET_BITOFFSET_POS
DAC_REG_DORX_REGOFFSET_MASK
DAC_REG_DORX_REGOFFSET_MASK_POSBIT0
DAC_REG_SHSR1_REGOFFSET
DAC_REG_SHSR2_REGOFFSET
DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS
DAC_REG_SHSRX_REGOFFSET_MASK
DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0
DAC_REG_STR1_REGOFFSET
DAC_REG_STR2_REGOFFSET
DAC_REG_STRX_REGOFFSET_BITOFFSET_POS
DAC_REG_STRX_REGOFFSET_MASK
DAC_REG_STRX_REGOFFSET_MASK_POSBIT0
DAC_SWTR_CH1
DAC_SWTR_CH2
DAC_SWTR_CHX_MASK
DAC_SWTRB_CH1
DAC_SWTRB_CH2
DAC_SWTRB_CHX_MASK
LL_DAC_CHANNEL_1
LL_DAC_CHANNEL_2
LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US
LL_DAC_DELAY_VOLTAGE_SETTLING_US
LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
LL_DAC_FLAG_BWST1
LL_DAC_FLAG_BWST2
LL_DAC_FLAG_CAL1
LL_DAC_FLAG_CAL2
LL_DAC_FLAG_DAC1RDY
LL_DAC_FLAG_DAC2RDY
LL_DAC_FLAG_DMAUDR1
LL_DAC_FLAG_DMAUDR2
LL_DAC_FLAG_DORSTAT1
LL_DAC_FLAG_DORSTAT2
LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
LL_DAC_HIGH_FREQ_MODE_DISABLE
LL_DAC_IT_DMAUDRIE1
LL_DAC_IT_DMAUDRIE2
LL_DAC_MODE_CALIBRATION
LL_DAC_MODE_NORMAL_OPERATION
LL_DAC_NOISE_LFSR_UNMASK_BIT0
LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
LL_DAC_OUTPUT_BUFFER_DISABLE
LL_DAC_OUTPUT_BUFFER_ENABLE
LL_DAC_OUTPUT_CONNECT_GPIO
LL_DAC_OUTPUT_CONNECT_INTERNAL
LL_DAC_OUTPUT_MODE_NORMAL
LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
LL_DAC_ReadReg
LL_DAC_RESOLUTION_12B
LL_DAC_RESOLUTION_8B
LL_DAC_SAWTOOTH_POLARITY_DECREMENT
LL_DAC_SAWTOOTH_POLARITY_INCREMENT
LL_DAC_SIGNED_FORMAT_DISABLE
LL_DAC_SIGNED_FORMAT_ENABLE
LL_DAC_TRIANGLE_AMPLITUDE_1
LL_DAC_TRIANGLE_AMPLITUDE_1023
LL_DAC_TRIANGLE_AMPLITUDE_127
LL_DAC_TRIANGLE_AMPLITUDE_15
LL_DAC_TRIANGLE_AMPLITUDE_2047
LL_DAC_TRIANGLE_AMPLITUDE_255
LL_DAC_TRIANGLE_AMPLITUDE_3
LL_DAC_TRIANGLE_AMPLITUDE_31
LL_DAC_TRIANGLE_AMPLITUDE_4095
LL_DAC_TRIANGLE_AMPLITUDE_511
LL_DAC_TRIANGLE_AMPLITUDE_63
LL_DAC_TRIANGLE_AMPLITUDE_7
LL_DAC_TRIG_EXT_EXTI_LINE10
LL_DAC_TRIG_EXT_EXTI_LINE9
LL_DAC_TRIG_EXT_HRTIM_RST_TRG1
LL_DAC_TRIG_EXT_HRTIM_RST_TRG2
LL_DAC_TRIG_EXT_HRTIM_RST_TRG3
LL_DAC_TRIG_EXT_HRTIM_RST_TRG4
LL_DAC_TRIG_EXT_HRTIM_RST_TRG5
LL_DAC_TRIG_EXT_HRTIM_RST_TRG6
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5
LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6
LL_DAC_TRIG_EXT_HRTIM_TRGO1
LL_DAC_TRIG_EXT_HRTIM_TRGO2
LL_DAC_TRIG_EXT_HRTIM_TRGO3
LL_DAC_TRIG_EXT_TIM15_TRGO
LL_DAC_TRIG_EXT_TIM1_TRGO
LL_DAC_TRIG_EXT_TIM2_TRGO
LL_DAC_TRIG_EXT_TIM3_TRGO
LL_DAC_TRIG_EXT_TIM4_TRGO
LL_DAC_TRIG_EXT_TIM6_TRGO
LL_DAC_TRIG_EXT_TIM7_TRGO
LL_DAC_TRIG_EXT_TIM8_TRGO
LL_DAC_TRIG_SOFTWARE
LL_DAC_WAVE_AUTO_GENERATION_NOISE
LL_DAC_WAVE_AUTO_GENERATION_NONE
LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
LL_DAC_WriteReg
LL_DAC_ClearFlag_DMAUDR1
LL_DAC_ClearFlag_DMAUDR2
LL_DAC_ConfigOutput
LL_DAC_ConvertData12LeftAligned
LL_DAC_ConvertData12RightAligned
LL_DAC_ConvertData8RightAligned
LL_DAC_ConvertDualData12LeftAligned
LL_DAC_ConvertDualData12RightAligned
LL_DAC_ConvertDualData8RightAligned
LL_DAC_DeInit
LL_DAC_Disable
LL_DAC_DisableDMADoubleDataMode
LL_DAC_DisableDMAReq
LL_DAC_DisableIT_DMAUDR1
LL_DAC_DisableIT_DMAUDR2
LL_DAC_DisableTrigger
LL_DAC_DMA_GetRegAddr
LL_DAC_Enable
LL_DAC_EnableDMADoubleDataMode
LL_DAC_EnableDMAReq
LL_DAC_EnableIT_DMAUDR1
LL_DAC_EnableIT_DMAUDR2
LL_DAC_EnableTrigger
LL_DAC_GetHighFrequencyMode
LL_DAC_GetMode
LL_DAC_GetOutputBuffer
LL_DAC_GetOutputConnection
LL_DAC_GetOutputMode
LL_DAC_GetSampleAndHoldHoldTime
LL_DAC_GetSampleAndHoldRefreshTime
LL_DAC_GetSampleAndHoldSampleTime
LL_DAC_GetSignedFormat
LL_DAC_GetTriggerSource
LL_DAC_GetTrimmingValue
LL_DAC_GetWaveAutoGeneration
LL_DAC_GetWaveNoiseLFSR
LL_DAC_GetWaveSawtoothPolarity
LL_DAC_GetWaveSawtoothResetData
LL_DAC_GetWaveSawtoothResetTriggerSource
LL_DAC_GetWaveSawtoothStepData
LL_DAC_GetWaveSawtoothStepTriggerSource
LL_DAC_GetWaveTriangleAmplitude
LL_DAC_Init
LL_DAC_IsActiveFlag_BWST1
LL_DAC_IsActiveFlag_BWST2
LL_DAC_IsActiveFlag_CAL1
LL_DAC_IsActiveFlag_CAL2
LL_DAC_IsActiveFlag_DAC1RDY
LL_DAC_IsActiveFlag_DAC2RDY
LL_DAC_IsActiveFlag_DMAUDR1
LL_DAC_IsActiveFlag_DMAUDR2
LL_DAC_IsActiveFlag_DORSTAT1
LL_DAC_IsActiveFlag_DORSTAT2
LL_DAC_IsDMADoubleDataModeEnabled
LL_DAC_IsDMAReqEnabled
LL_DAC_IsEnabled
LL_DAC_IsEnabledIT_DMAUDR1
LL_DAC_IsEnabledIT_DMAUDR2
LL_DAC_IsReady
LL_DAC_IsTriggerEnabled
LL_DAC_RetrieveOutputData
LL_DAC_SetHighFrequencyMode
LL_DAC_SetMode
LL_DAC_SetOutputBuffer
LL_DAC_SetOutputConnection
LL_DAC_SetOutputMode
LL_DAC_SetSampleAndHoldHoldTime
LL_DAC_SetSampleAndHoldRefreshTime
LL_DAC_SetSampleAndHoldSampleTime
LL_DAC_SetSignedFormat
LL_DAC_SetTriggerSource
LL_DAC_SetTrimmingValue
LL_DAC_SetWaveAutoGeneration
LL_DAC_SetWaveNoiseLFSR
LL_DAC_SetWaveSawtoothPolarity
LL_DAC_SetWaveSawtoothResetData
LL_DAC_SetWaveSawtoothResetTriggerSource
LL_DAC_SetWaveSawtoothStepData
LL_DAC_SetWaveSawtoothStepTriggerSource
LL_DAC_SetWaveTriangleAmplitude
LL_DAC_StructInit
LL_DAC_TrigSWConversion
LL_DAC_TrigSWConversion2
stm32g4xx_ll_dma.c
IS_LL_DMA_ALL_CHANNEL_INSTANCE
IS_LL_DMA_DIRECTION
IS_LL_DMA_MEMORYDATASIZE
IS_LL_DMA_MEMORYINCMODE
IS_LL_DMA_MODE
IS_LL_DMA_NBDATA
IS_LL_DMA_PERIPHDATASIZE
IS_LL_DMA_PERIPHINCMODE
IS_LL_DMA_PERIPHREQUEST
IS_LL_DMA_PRIORITY
LL_DMA_DeInit
LL_DMA_Init
LL_DMA_StructInit
stm32g4xx_ll_dma.h
__LL_DMA_GET_CHANNEL_INSTANCE
__LL_DMA_GET_INSTANCE
DMA_CSELR_OFFSET
DMA_POSITION_CSELR_CXS
LL_DMA_CCR_HTIE
LL_DMA_CCR_TCIE
LL_DMA_CCR_TEIE
LL_DMA_CHANNEL_1
LL_DMA_CHANNEL_2
LL_DMA_CHANNEL_3
LL_DMA_CHANNEL_4
LL_DMA_CHANNEL_5
LL_DMA_CHANNEL_6
LL_DMA_CHANNEL_7
LL_DMA_CHANNEL_8
LL_DMA_CHANNEL_ALL
LL_DMA_DIRECTION_MEMORY_TO_MEMORY
LL_DMA_DIRECTION_MEMORY_TO_PERIPH
LL_DMA_DIRECTION_PERIPH_TO_MEMORY
LL_DMA_IFCR_CGIF1
LL_DMA_IFCR_CGIF2
LL_DMA_IFCR_CGIF3
LL_DMA_IFCR_CGIF4
LL_DMA_IFCR_CGIF5
LL_DMA_IFCR_CGIF6
LL_DMA_IFCR_CGIF7
LL_DMA_IFCR_CGIF8
LL_DMA_IFCR_CHTIF1
LL_DMA_IFCR_CHTIF2
LL_DMA_IFCR_CHTIF3
LL_DMA_IFCR_CHTIF4
LL_DMA_IFCR_CHTIF5
LL_DMA_IFCR_CHTIF6
LL_DMA_IFCR_CHTIF7
LL_DMA_IFCR_CHTIF8
LL_DMA_IFCR_CTCIF1
LL_DMA_IFCR_CTCIF2
LL_DMA_IFCR_CTCIF3
LL_DMA_IFCR_CTCIF4
LL_DMA_IFCR_CTCIF5
LL_DMA_IFCR_CTCIF6
LL_DMA_IFCR_CTCIF7
LL_DMA_IFCR_CTCIF8
LL_DMA_IFCR_CTEIF1
LL_DMA_IFCR_CTEIF2
LL_DMA_IFCR_CTEIF3
LL_DMA_IFCR_CTEIF4
LL_DMA_IFCR_CTEIF5
LL_DMA_IFCR_CTEIF6
LL_DMA_IFCR_CTEIF7
LL_DMA_IFCR_CTEIF8
LL_DMA_ISR_GIF1
LL_DMA_ISR_GIF2
LL_DMA_ISR_GIF3
LL_DMA_ISR_GIF4
LL_DMA_ISR_GIF5
LL_DMA_ISR_GIF6
LL_DMA_ISR_GIF7
LL_DMA_ISR_GIF8
LL_DMA_ISR_HTIF1
LL_DMA_ISR_HTIF2
LL_DMA_ISR_HTIF3
LL_DMA_ISR_HTIF4
LL_DMA_ISR_HTIF5
LL_DMA_ISR_HTIF6
LL_DMA_ISR_HTIF7
LL_DMA_ISR_HTIF8
LL_DMA_ISR_TCIF1
LL_DMA_ISR_TCIF2
LL_DMA_ISR_TCIF3
LL_DMA_ISR_TCIF4
LL_DMA_ISR_TCIF5
LL_DMA_ISR_TCIF6
LL_DMA_ISR_TCIF7
LL_DMA_ISR_TCIF8
LL_DMA_ISR_TEIF1
LL_DMA_ISR_TEIF2
LL_DMA_ISR_TEIF3
LL_DMA_ISR_TEIF4
LL_DMA_ISR_TEIF5
LL_DMA_ISR_TEIF6
LL_DMA_ISR_TEIF7
LL_DMA_ISR_TEIF8
LL_DMA_MDATAALIGN_BYTE
LL_DMA_MDATAALIGN_HALFWORD
LL_DMA_MDATAALIGN_WORD
LL_DMA_MEMORY_INCREMENT
LL_DMA_MEMORY_NOINCREMENT
LL_DMA_MODE_CIRCULAR
LL_DMA_MODE_NORMAL
LL_DMA_PDATAALIGN_BYTE
LL_DMA_PDATAALIGN_HALFWORD
LL_DMA_PDATAALIGN_WORD
LL_DMA_PERIPH_INCREMENT
LL_DMA_PERIPH_NOINCREMENT
LL_DMA_PRIORITY_HIGH
LL_DMA_PRIORITY_LOW
LL_DMA_PRIORITY_MEDIUM
LL_DMA_PRIORITY_VERYHIGH
LL_DMA_ReadReg
LL_DMA_WriteReg
LL_DMA_ClearFlag_GI1
LL_DMA_ClearFlag_GI2
LL_DMA_ClearFlag_GI3
LL_DMA_ClearFlag_GI4
LL_DMA_ClearFlag_GI5
LL_DMA_ClearFlag_GI6
LL_DMA_ClearFlag_GI7
LL_DMA_ClearFlag_GI8
LL_DMA_ClearFlag_HT1
LL_DMA_ClearFlag_HT2
LL_DMA_ClearFlag_HT3
LL_DMA_ClearFlag_HT4
LL_DMA_ClearFlag_HT5
LL_DMA_ClearFlag_HT6
LL_DMA_ClearFlag_HT7
LL_DMA_ClearFlag_HT8
LL_DMA_ClearFlag_TC1
LL_DMA_ClearFlag_TC2
LL_DMA_ClearFlag_TC3
LL_DMA_ClearFlag_TC4
LL_DMA_ClearFlag_TC5
LL_DMA_ClearFlag_TC6
LL_DMA_ClearFlag_TC7
LL_DMA_ClearFlag_TC8
LL_DMA_ClearFlag_TE1
LL_DMA_ClearFlag_TE2
LL_DMA_ClearFlag_TE3
LL_DMA_ClearFlag_TE4
LL_DMA_ClearFlag_TE5
LL_DMA_ClearFlag_TE6
LL_DMA_ClearFlag_TE7
LL_DMA_ClearFlag_TE8
LL_DMA_ConfigAddresses
LL_DMA_ConfigTransfer
LL_DMA_DeInit
LL_DMA_DisableChannel
LL_DMA_DisableIT_HT
LL_DMA_DisableIT_TC
LL_DMA_DisableIT_TE
LL_DMA_EnableChannel
LL_DMA_EnableIT_HT
LL_DMA_EnableIT_TC
LL_DMA_EnableIT_TE
LL_DMA_GetChannelPriorityLevel
LL_DMA_GetDataLength
LL_DMA_GetDataTransferDirection
LL_DMA_GetM2MDstAddress
LL_DMA_GetM2MSrcAddress
LL_DMA_GetMemoryAddress
LL_DMA_GetMemoryIncMode
LL_DMA_GetMemorySize
LL_DMA_GetMode
LL_DMA_GetPeriphAddress
LL_DMA_GetPeriphIncMode
LL_DMA_GetPeriphRequest
LL_DMA_GetPeriphSize
LL_DMA_Init
LL_DMA_IsActiveFlag_GI1
LL_DMA_IsActiveFlag_GI2
LL_DMA_IsActiveFlag_GI3
LL_DMA_IsActiveFlag_GI4
LL_DMA_IsActiveFlag_GI5
LL_DMA_IsActiveFlag_GI6
LL_DMA_IsActiveFlag_GI7
LL_DMA_IsActiveFlag_GI8
LL_DMA_IsActiveFlag_HT1
LL_DMA_IsActiveFlag_HT2
LL_DMA_IsActiveFlag_HT3
LL_DMA_IsActiveFlag_HT4
LL_DMA_IsActiveFlag_HT5
LL_DMA_IsActiveFlag_HT6
LL_DMA_IsActiveFlag_HT7
LL_DMA_IsActiveFlag_HT8
LL_DMA_IsActiveFlag_TC1
LL_DMA_IsActiveFlag_TC2
LL_DMA_IsActiveFlag_TC3
LL_DMA_IsActiveFlag_TC4
LL_DMA_IsActiveFlag_TC5
LL_DMA_IsActiveFlag_TC6
LL_DMA_IsActiveFlag_TC7
LL_DMA_IsActiveFlag_TC8
LL_DMA_IsActiveFlag_TE1
LL_DMA_IsActiveFlag_TE2
LL_DMA_IsActiveFlag_TE3
LL_DMA_IsActiveFlag_TE4
LL_DMA_IsActiveFlag_TE5
LL_DMA_IsActiveFlag_TE6
LL_DMA_IsActiveFlag_TE7
LL_DMA_IsActiveFlag_TE8
LL_DMA_IsEnabledChannel
LL_DMA_IsEnabledIT_HT
LL_DMA_IsEnabledIT_TC
LL_DMA_IsEnabledIT_TE
LL_DMA_SetChannelPriorityLevel
LL_DMA_SetDataLength
LL_DMA_SetDataTransferDirection
LL_DMA_SetM2MDstAddress
LL_DMA_SetM2MSrcAddress
LL_DMA_SetMemoryAddress
LL_DMA_SetMemoryIncMode
LL_DMA_SetMemorySize
LL_DMA_SetMode
LL_DMA_SetPeriphAddress
LL_DMA_SetPeriphIncMode
LL_DMA_SetPeriphRequest
LL_DMA_SetPeriphSize
LL_DMA_StructInit
CHANNEL_OFFSET_TAB
stm32g4xx_ll_dmamux.h
DMAMUX_RGCR_SIZE
LL_DMAMUX_CCR_SOIE
LL_DMAMUX_CFR_CSOF0
LL_DMAMUX_CFR_CSOF1
LL_DMAMUX_CFR_CSOF10
LL_DMAMUX_CFR_CSOF11
LL_DMAMUX_CFR_CSOF12
LL_DMAMUX_CFR_CSOF13
LL_DMAMUX_CFR_CSOF14
LL_DMAMUX_CFR_CSOF15
LL_DMAMUX_CFR_CSOF2
LL_DMAMUX_CFR_CSOF3
LL_DMAMUX_CFR_CSOF4
LL_DMAMUX_CFR_CSOF5
LL_DMAMUX_CFR_CSOF6
LL_DMAMUX_CFR_CSOF7
LL_DMAMUX_CFR_CSOF8
LL_DMAMUX_CFR_CSOF9
LL_DMAMUX_CHANNEL_0
LL_DMAMUX_CHANNEL_1
LL_DMAMUX_CHANNEL_10
LL_DMAMUX_CHANNEL_11
LL_DMAMUX_CHANNEL_12
LL_DMAMUX_CHANNEL_13
LL_DMAMUX_CHANNEL_14
LL_DMAMUX_CHANNEL_15
LL_DMAMUX_CHANNEL_2
LL_DMAMUX_CHANNEL_3
LL_DMAMUX_CHANNEL_4
LL_DMAMUX_CHANNEL_5
LL_DMAMUX_CHANNEL_6
LL_DMAMUX_CHANNEL_7
LL_DMAMUX_CHANNEL_8
LL_DMAMUX_CHANNEL_9
LL_DMAMUX_CSR_SOF0
LL_DMAMUX_CSR_SOF1
LL_DMAMUX_CSR_SOF10
LL_DMAMUX_CSR_SOF11
LL_DMAMUX_CSR_SOF12
LL_DMAMUX_CSR_SOF13
LL_DMAMUX_CSR_SOF14
LL_DMAMUX_CSR_SOF15
LL_DMAMUX_CSR_SOF2
LL_DMAMUX_CSR_SOF3
LL_DMAMUX_CSR_SOF4
LL_DMAMUX_CSR_SOF5
LL_DMAMUX_CSR_SOF6
LL_DMAMUX_CSR_SOF7
LL_DMAMUX_CSR_SOF8
LL_DMAMUX_CSR_SOF9
LL_DMAMUX_ReadReg
LL_DMAMUX_REQ_ADC1
LL_DMAMUX_REQ_ADC2
LL_DMAMUX_REQ_ADC3
LL_DMAMUX_REQ_ADC4
LL_DMAMUX_REQ_ADC5
LL_DMAMUX_REQ_AES_IN
LL_DMAMUX_REQ_AES_OUT
LL_DMAMUX_REQ_CORDIC_READ
LL_DMAMUX_REQ_CORDIC_WRITE
LL_DMAMUX_REQ_DAC1_CH1
LL_DMAMUX_REQ_DAC1_CH2
LL_DMAMUX_REQ_DAC2_CH1
LL_DMAMUX_REQ_DAC3_CH1
LL_DMAMUX_REQ_DAC3_CH2
LL_DMAMUX_REQ_DAC4_CH1
LL_DMAMUX_REQ_DAC4_CH2
LL_DMAMUX_REQ_FMAC_READ
LL_DMAMUX_REQ_FMAC_WRITE
LL_DMAMUX_REQ_GEN_0
LL_DMAMUX_REQ_GEN_1
LL_DMAMUX_REQ_GEN_2
LL_DMAMUX_REQ_GEN_3
LL_DMAMUX_REQ_GEN_DMAMUX_CH0
LL_DMAMUX_REQ_GEN_DMAMUX_CH1
LL_DMAMUX_REQ_GEN_DMAMUX_CH2
LL_DMAMUX_REQ_GEN_DMAMUX_CH3
LL_DMAMUX_REQ_GEN_EXTI_LINE0
LL_DMAMUX_REQ_GEN_EXTI_LINE1
LL_DMAMUX_REQ_GEN_EXTI_LINE10
LL_DMAMUX_REQ_GEN_EXTI_LINE11
LL_DMAMUX_REQ_GEN_EXTI_LINE12
LL_DMAMUX_REQ_GEN_EXTI_LINE13
LL_DMAMUX_REQ_GEN_EXTI_LINE14
LL_DMAMUX_REQ_GEN_EXTI_LINE15
LL_DMAMUX_REQ_GEN_EXTI_LINE2
LL_DMAMUX_REQ_GEN_EXTI_LINE3
LL_DMAMUX_REQ_GEN_EXTI_LINE4
LL_DMAMUX_REQ_GEN_EXTI_LINE5
LL_DMAMUX_REQ_GEN_EXTI_LINE6
LL_DMAMUX_REQ_GEN_EXTI_LINE7
LL_DMAMUX_REQ_GEN_EXTI_LINE8
LL_DMAMUX_REQ_GEN_EXTI_LINE9
LL_DMAMUX_REQ_GEN_LPTIM1_OUT
LL_DMAMUX_REQ_GEN_NO_EVENT
LL_DMAMUX_REQ_GEN_POL_FALLING
LL_DMAMUX_REQ_GEN_POL_RISING
LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
LL_DMAMUX_REQ_GENERATOR0
LL_DMAMUX_REQ_GENERATOR1
LL_DMAMUX_REQ_GENERATOR2
LL_DMAMUX_REQ_GENERATOR3
LL_DMAMUX_REQ_HRTIM1_A
LL_DMAMUX_REQ_HRTIM1_B
LL_DMAMUX_REQ_HRTIM1_C
LL_DMAMUX_REQ_HRTIM1_D
LL_DMAMUX_REQ_HRTIM1_E
LL_DMAMUX_REQ_HRTIM1_F
LL_DMAMUX_REQ_HRTIM1_M
LL_DMAMUX_REQ_I2C1_RX
LL_DMAMUX_REQ_I2C1_TX
LL_DMAMUX_REQ_I2C2_RX
LL_DMAMUX_REQ_I2C2_TX
LL_DMAMUX_REQ_I2C3_RX
LL_DMAMUX_REQ_I2C3_TX
LL_DMAMUX_REQ_I2C4_RX
LL_DMAMUX_REQ_I2C4_TX
LL_DMAMUX_REQ_LPUART1_RX
LL_DMAMUX_REQ_LPUART1_TX
LL_DMAMUX_REQ_MEM2MEM
LL_DMAMUX_REQ_QSPI
LL_DMAMUX_REQ_SAI1_A
LL_DMAMUX_REQ_SAI1_B
LL_DMAMUX_REQ_SPI1_RX
LL_DMAMUX_REQ_SPI1_TX
LL_DMAMUX_REQ_SPI2_RX
LL_DMAMUX_REQ_SPI2_TX
LL_DMAMUX_REQ_SPI3_RX
LL_DMAMUX_REQ_SPI3_TX
LL_DMAMUX_REQ_SPI4_RX
LL_DMAMUX_REQ_SPI4_TX
LL_DMAMUX_REQ_TIM15_CH1
LL_DMAMUX_REQ_TIM15_COM
LL_DMAMUX_REQ_TIM15_TRIG
LL_DMAMUX_REQ_TIM15_UP
LL_DMAMUX_REQ_TIM16_CH1
LL_DMAMUX_REQ_TIM16_UP
LL_DMAMUX_REQ_TIM17_CH1
LL_DMAMUX_REQ_TIM17_UP
LL_DMAMUX_REQ_TIM1_CH1
LL_DMAMUX_REQ_TIM1_CH2
LL_DMAMUX_REQ_TIM1_CH3
LL_DMAMUX_REQ_TIM1_CH4
LL_DMAMUX_REQ_TIM1_COM
LL_DMAMUX_REQ_TIM1_TRIG
LL_DMAMUX_REQ_TIM1_UP
LL_DMAMUX_REQ_TIM20_CH1
LL_DMAMUX_REQ_TIM20_CH2
LL_DMAMUX_REQ_TIM20_CH3
LL_DMAMUX_REQ_TIM20_CH4
LL_DMAMUX_REQ_TIM20_COM
LL_DMAMUX_REQ_TIM20_TRIG
LL_DMAMUX_REQ_TIM20_UP
LL_DMAMUX_REQ_TIM2_CH1
LL_DMAMUX_REQ_TIM2_CH2
LL_DMAMUX_REQ_TIM2_CH3
LL_DMAMUX_REQ_TIM2_CH4
LL_DMAMUX_REQ_TIM2_UP
LL_DMAMUX_REQ_TIM3_CH1
LL_DMAMUX_REQ_TIM3_CH2
LL_DMAMUX_REQ_TIM3_CH3
LL_DMAMUX_REQ_TIM3_CH4
LL_DMAMUX_REQ_TIM3_TRIG
LL_DMAMUX_REQ_TIM3_UP
LL_DMAMUX_REQ_TIM4_CH1
LL_DMAMUX_REQ_TIM4_CH2
LL_DMAMUX_REQ_TIM4_CH3
LL_DMAMUX_REQ_TIM4_CH4
LL_DMAMUX_REQ_TIM4_UP
LL_DMAMUX_REQ_TIM5_CH1
LL_DMAMUX_REQ_TIM5_CH2
LL_DMAMUX_REQ_TIM5_CH3
LL_DMAMUX_REQ_TIM5_CH4
LL_DMAMUX_REQ_TIM5_TRIG
LL_DMAMUX_REQ_TIM5_UP
LL_DMAMUX_REQ_TIM6_UP
LL_DMAMUX_REQ_TIM7_UP
LL_DMAMUX_REQ_TIM8_CH1
LL_DMAMUX_REQ_TIM8_CH2
LL_DMAMUX_REQ_TIM8_CH3
LL_DMAMUX_REQ_TIM8_CH4
LL_DMAMUX_REQ_TIM8_COM
LL_DMAMUX_REQ_TIM8_TRIG
LL_DMAMUX_REQ_TIM8_UP
LL_DMAMUX_REQ_UART4_RX
LL_DMAMUX_REQ_UART4_TX
LL_DMAMUX_REQ_UART5_RX
LL_DMAMUX_REQ_UART5_TX
LL_DMAMUX_REQ_UCPD1_RX
LL_DMAMUX_REQ_UCPD1_TX
LL_DMAMUX_REQ_USART1_RX
LL_DMAMUX_REQ_USART1_TX
LL_DMAMUX_REQ_USART2_RX
LL_DMAMUX_REQ_USART2_TX
LL_DMAMUX_REQ_USART3_RX
LL_DMAMUX_REQ_USART3_TX
LL_DMAMUX_RGCFR_RGCOF0
LL_DMAMUX_RGCFR_RGCOF1
LL_DMAMUX_RGCFR_RGCOF2
LL_DMAMUX_RGCFR_RGCOF3
LL_DMAMUX_RGCR_RGOIE
LL_DMAMUX_RGSR_RGOF0
LL_DMAMUX_RGSR_RGOF1
LL_DMAMUX_RGSR_RGOF2
LL_DMAMUX_RGSR_RGOF3
LL_DMAMUX_SYNC_DMAMUX_CH0
LL_DMAMUX_SYNC_DMAMUX_CH1
LL_DMAMUX_SYNC_DMAMUX_CH2
LL_DMAMUX_SYNC_DMAMUX_CH3
LL_DMAMUX_SYNC_EXTI_LINE0
LL_DMAMUX_SYNC_EXTI_LINE1
LL_DMAMUX_SYNC_EXTI_LINE10
LL_DMAMUX_SYNC_EXTI_LINE11
LL_DMAMUX_SYNC_EXTI_LINE12
LL_DMAMUX_SYNC_EXTI_LINE13
LL_DMAMUX_SYNC_EXTI_LINE14
LL_DMAMUX_SYNC_EXTI_LINE15
LL_DMAMUX_SYNC_EXTI_LINE2
LL_DMAMUX_SYNC_EXTI_LINE3
LL_DMAMUX_SYNC_EXTI_LINE4
LL_DMAMUX_SYNC_EXTI_LINE5
LL_DMAMUX_SYNC_EXTI_LINE6
LL_DMAMUX_SYNC_EXTI_LINE7
LL_DMAMUX_SYNC_EXTI_LINE8
LL_DMAMUX_SYNC_EXTI_LINE9
LL_DMAMUX_SYNC_LPTIM1_OUT
LL_DMAMUX_SYNC_NO_EVENT
LL_DMAMUX_SYNC_POL_FALLING
LL_DMAMUX_SYNC_POL_RISING
LL_DMAMUX_SYNC_POL_RISING_FALLING
LL_DMAMUX_WriteReg
UNUSED
LL_DMAMUX_ClearFlag_RGO0
LL_DMAMUX_ClearFlag_RGO1
LL_DMAMUX_ClearFlag_RGO2
LL_DMAMUX_ClearFlag_RGO3
LL_DMAMUX_ClearFlag_SO0
LL_DMAMUX_ClearFlag_SO1
LL_DMAMUX_ClearFlag_SO10
LL_DMAMUX_ClearFlag_SO11
LL_DMAMUX_ClearFlag_SO12
LL_DMAMUX_ClearFlag_SO13
LL_DMAMUX_ClearFlag_SO14
LL_DMAMUX_ClearFlag_SO15
LL_DMAMUX_ClearFlag_SO2
LL_DMAMUX_ClearFlag_SO3
LL_DMAMUX_ClearFlag_SO4
LL_DMAMUX_ClearFlag_SO5
LL_DMAMUX_ClearFlag_SO6
LL_DMAMUX_ClearFlag_SO7
LL_DMAMUX_ClearFlag_SO8
LL_DMAMUX_ClearFlag_SO9
LL_DMAMUX_DisableEventGeneration
LL_DMAMUX_DisableIT_RGO
LL_DMAMUX_DisableIT_SO
LL_DMAMUX_DisableRequestGen
LL_DMAMUX_DisableSync
LL_DMAMUX_EnableEventGeneration
LL_DMAMUX_EnableIT_RGO
LL_DMAMUX_EnableIT_SO
LL_DMAMUX_EnableRequestGen
LL_DMAMUX_EnableSync
LL_DMAMUX_GetGenRequestNb
LL_DMAMUX_GetRequestGenPolarity
LL_DMAMUX_GetRequestID
LL_DMAMUX_GetRequestSignalID
LL_DMAMUX_GetSyncID
LL_DMAMUX_GetSyncPolarity
LL_DMAMUX_GetSyncRequestNb
LL_DMAMUX_IsActiveFlag_RGO0
LL_DMAMUX_IsActiveFlag_RGO1
LL_DMAMUX_IsActiveFlag_RGO2
LL_DMAMUX_IsActiveFlag_RGO3
LL_DMAMUX_IsActiveFlag_SO0
LL_DMAMUX_IsActiveFlag_SO1
LL_DMAMUX_IsActiveFlag_SO10
LL_DMAMUX_IsActiveFlag_SO11
LL_DMAMUX_IsActiveFlag_SO12
LL_DMAMUX_IsActiveFlag_SO13
LL_DMAMUX_IsActiveFlag_SO14
LL_DMAMUX_IsActiveFlag_SO15
LL_DMAMUX_IsActiveFlag_SO2
LL_DMAMUX_IsActiveFlag_SO3
LL_DMAMUX_IsActiveFlag_SO4
LL_DMAMUX_IsActiveFlag_SO5
LL_DMAMUX_IsActiveFlag_SO6
LL_DMAMUX_IsActiveFlag_SO7
LL_DMAMUX_IsActiveFlag_SO8
LL_DMAMUX_IsActiveFlag_SO9
LL_DMAMUX_IsEnabledEventGeneration
LL_DMAMUX_IsEnabledIT_RGO
LL_DMAMUX_IsEnabledIT_SO
LL_DMAMUX_IsEnabledRequestGen
LL_DMAMUX_IsEnabledSync
LL_DMAMUX_SetGenRequestNb
LL_DMAMUX_SetRequestGenPolarity
LL_DMAMUX_SetRequestID
LL_DMAMUX_SetRequestSignalID
LL_DMAMUX_SetSyncID
LL_DMAMUX_SetSyncPolarity
LL_DMAMUX_SetSyncRequestNb
stm32g4xx_ll_exti.c
IS_LL_EXTI_LINE_0_31
IS_LL_EXTI_LINE_32_63
IS_LL_EXTI_MODE
IS_LL_EXTI_TRIGGER
LL_EXTI_DeInit
LL_EXTI_Init
LL_EXTI_StructInit
stm32g4xx_ll_exti.h
LL_EXTI_LINE_1
LL_EXTI_LINE_10
LL_EXTI_LINE_11
LL_EXTI_LINE_12
LL_EXTI_LINE_13
LL_EXTI_LINE_14
LL_EXTI_LINE_15
LL_EXTI_LINE_16
LL_EXTI_LINE_17
LL_EXTI_LINE_18
LL_EXTI_LINE_19
LL_EXTI_LINE_2
LL_EXTI_LINE_20
LL_EXTI_LINE_21
LL_EXTI_LINE_22
LL_EXTI_LINE_23
LL_EXTI_LINE_24
LL_EXTI_LINE_25
LL_EXTI_LINE_26
LL_EXTI_LINE_27
LL_EXTI_LINE_28
LL_EXTI_LINE_29
LL_EXTI_LINE_3
LL_EXTI_LINE_30
LL_EXTI_LINE_31
LL_EXTI_LINE_32
LL_EXTI_LINE_33
LL_EXTI_LINE_34
LL_EXTI_LINE_35
LL_EXTI_LINE_36
LL_EXTI_LINE_37
LL_EXTI_LINE_38
LL_EXTI_LINE_39
LL_EXTI_LINE_4
LL_EXTI_LINE_40
LL_EXTI_LINE_41
LL_EXTI_LINE_42
LL_EXTI_LINE_5
LL_EXTI_LINE_6
LL_EXTI_LINE_7
LL_EXTI_LINE_8
LL_EXTI_LINE_9
LL_EXTI_LINE_ALL
LL_EXTI_LINE_ALL_0_31
LL_EXTI_LINE_ALL_32_63
LL_EXTI_LINE_NONE
LL_EXTI_MODE_EVENT
LL_EXTI_MODE_IT
LL_EXTI_MODE_IT_EVENT
LL_EXTI_ReadReg
LL_EXTI_TRIGGER_FALLING
LL_EXTI_TRIGGER_NONE
LL_EXTI_TRIGGER_RISING
LL_EXTI_TRIGGER_RISING_FALLING
LL_EXTI_WriteReg
LL_EXTI_ClearFlag_0_31
LL_EXTI_ClearFlag_32_63
LL_EXTI_DeInit
LL_EXTI_DisableEvent_0_31
LL_EXTI_DisableEvent_32_63
LL_EXTI_DisableFallingTrig_0_31
LL_EXTI_DisableFallingTrig_32_63
LL_EXTI_DisableIT_0_31
LL_EXTI_DisableIT_32_63
LL_EXTI_DisableRisingTrig_0_31
LL_EXTI_DisableRisingTrig_32_63
LL_EXTI_EnableEvent_0_31
LL_EXTI_EnableEvent_32_63
LL_EXTI_EnableFallingTrig_0_31
LL_EXTI_EnableFallingTrig_32_63
LL_EXTI_EnableIT_0_31
LL_EXTI_EnableIT_32_63
LL_EXTI_EnableRisingTrig_0_31
LL_EXTI_EnableRisingTrig_32_63
LL_EXTI_GenerateSWI_0_31
LL_EXTI_GenerateSWI_32_63
LL_EXTI_Init
LL_EXTI_IsActiveFlag_0_31
LL_EXTI_IsActiveFlag_32_63
LL_EXTI_IsEnabledEvent_0_31
LL_EXTI_IsEnabledEvent_32_63
LL_EXTI_IsEnabledFallingTrig_0_31
LL_EXTI_IsEnabledFallingTrig_32_63
LL_EXTI_IsEnabledIT_0_31
LL_EXTI_IsEnabledIT_32_63
LL_EXTI_IsEnabledRisingTrig_0_31
LL_EXTI_IsEnabledRisingTrig_32_63
LL_EXTI_ReadFlag_0_31
LL_EXTI_ReadFlag_32_63
LL_EXTI_StructInit
stm32g4xx_ll_fmac.c
LL_FMAC_DeInit
LL_FMAC_Init
stm32g4xx_ll_fmac.h
LL_FMAC_CR_RIEN
LL_FMAC_CR_SATIEN
LL_FMAC_CR_UNFLIEN
LL_FMAC_CR_WIEN
LL_FMAC_FUNC_CONVO_FIR
LL_FMAC_FUNC_IIR_DIRECT_FORM_1
LL_FMAC_FUNC_LOAD_X1
LL_FMAC_FUNC_LOAD_X2
LL_FMAC_FUNC_LOAD_Y
LL_FMAC_PROCESSING_START
LL_FMAC_PROCESSING_STOP
LL_FMAC_ReadReg
LL_FMAC_SR_OVFL
LL_FMAC_SR_SAT
LL_FMAC_SR_UNFL
LL_FMAC_SR_X1FULL
LL_FMAC_SR_YEMPTY
LL_FMAC_WM_0_THRESHOLD_1
LL_FMAC_WM_1_THRESHOLD_2
LL_FMAC_WM_2_THRESHOLD_4
LL_FMAC_WM_3_THRESHOLD_8
LL_FMAC_WriteReg
LL_FMAC_ConfigFunc
LL_FMAC_ConfigX1
LL_FMAC_ConfigX2
LL_FMAC_ConfigY
LL_FMAC_DeInit
LL_FMAC_DisableClipping
LL_FMAC_DisableDMAReq_READ
LL_FMAC_DisableDMAReq_WRITE
LL_FMAC_DisableIT_OVFL
LL_FMAC_DisableIT_RD
LL_FMAC_DisableIT_SAT
LL_FMAC_DisableIT_UNFL
LL_FMAC_DisableIT_WR
LL_FMAC_DisableStart
LL_FMAC_EnableClipping
LL_FMAC_EnableDMAReq_READ
LL_FMAC_EnableDMAReq_WRITE
LL_FMAC_EnableIT_OVFL
LL_FMAC_EnableIT_RD
LL_FMAC_EnableIT_SAT
LL_FMAC_EnableIT_UNFL
LL_FMAC_EnableIT_WR
LL_FMAC_EnableReset
LL_FMAC_EnableStart
LL_FMAC_GetFunction
LL_FMAC_GetParamP
LL_FMAC_GetParamQ
LL_FMAC_GetParamR
LL_FMAC_GetX1Base
LL_FMAC_GetX1BufferSize
LL_FMAC_GetX1FullWatermark
LL_FMAC_GetX2Base
LL_FMAC_GetX2BufferSize
LL_FMAC_GetYBase
LL_FMAC_GetYBufferSize
LL_FMAC_GetYEmptyWatermark
LL_FMAC_Init
LL_FMAC_IsActiveFlag_OVFL
LL_FMAC_IsActiveFlag_SAT
LL_FMAC_IsActiveFlag_UNFL
LL_FMAC_IsActiveFlag_X1FULL
LL_FMAC_IsActiveFlag_YEMPTY
LL_FMAC_IsEnabledClipping
LL_FMAC_IsEnabledDMAReq_READ
LL_FMAC_IsEnabledDMAReq_WRITE
LL_FMAC_IsEnabledIT_OVFL
LL_FMAC_IsEnabledIT_RD
LL_FMAC_IsEnabledIT_SAT
LL_FMAC_IsEnabledIT_UNFL
LL_FMAC_IsEnabledIT_WR
LL_FMAC_IsEnabledReset
LL_FMAC_IsEnabledStart
LL_FMAC_ReadData
LL_FMAC_SetFunction
LL_FMAC_SetParamP
LL_FMAC_SetParamQ
LL_FMAC_SetParamR
LL_FMAC_SetX1Base
LL_FMAC_SetX1BufferSize
LL_FMAC_SetX1FullWatermark
LL_FMAC_SetX2Base
LL_FMAC_SetX2BufferSize
LL_FMAC_SetYBase
LL_FMAC_SetYBufferSize
LL_FMAC_SetYEmptyWatermark
LL_FMAC_WriteData
stm32g4xx_ll_gpio.c
IS_LL_GPIO_ALTERNATE
IS_LL_GPIO_MODE
IS_LL_GPIO_OUTPUT_TYPE
IS_LL_GPIO_PIN
IS_LL_GPIO_PULL
IS_LL_GPIO_SPEED
LL_GPIO_DeInit
LL_GPIO_Init
LL_GPIO_StructInit
stm32g4xx_ll_gpio.h
LL_GPIO_AF_1
LL_GPIO_AF_10
LL_GPIO_AF_11
LL_GPIO_AF_12
LL_GPIO_AF_13
LL_GPIO_AF_14
LL_GPIO_AF_15
LL_GPIO_AF_2
LL_GPIO_AF_3
LL_GPIO_AF_4
LL_GPIO_AF_5
LL_GPIO_AF_6
LL_GPIO_AF_7
LL_GPIO_AF_8
LL_GPIO_AF_9
LL_GPIO_MODE_ALTERNATE
LL_GPIO_MODE_ANALOG
LL_GPIO_MODE_INPUT
LL_GPIO_MODE_OUTPUT
LL_GPIO_OUTPUT_OPENDRAIN
LL_GPIO_OUTPUT_PUSHPULL
LL_GPIO_PIN_0
LL_GPIO_PIN_1
LL_GPIO_PIN_10
LL_GPIO_PIN_11
LL_GPIO_PIN_12
LL_GPIO_PIN_13
LL_GPIO_PIN_14
LL_GPIO_PIN_15
LL_GPIO_PIN_2
LL_GPIO_PIN_3
LL_GPIO_PIN_4
LL_GPIO_PIN_5
LL_GPIO_PIN_6
LL_GPIO_PIN_7
LL_GPIO_PIN_8
LL_GPIO_PIN_9
LL_GPIO_PIN_ALL
LL_GPIO_PULL_DOWN
LL_GPIO_PULL_NO
LL_GPIO_PULL_UP
LL_GPIO_ReadReg
LL_GPIO_SPEED_FAST
LL_GPIO_SPEED_FREQ_HIGH
LL_GPIO_SPEED_FREQ_LOW
LL_GPIO_SPEED_FREQ_MEDIUM
LL_GPIO_SPEED_FREQ_VERY_HIGH
LL_GPIO_SPEED_HIGH
LL_GPIO_SPEED_LOW
LL_GPIO_SPEED_MEDIUM
LL_GPIO_WriteReg
LL_GPIO_DeInit
LL_GPIO_GetAFPin_0_7
LL_GPIO_GetAFPin_8_15
LL_GPIO_GetPinMode
LL_GPIO_GetPinOutputType
LL_GPIO_GetPinPull
LL_GPIO_GetPinSpeed
LL_GPIO_Init
LL_GPIO_IsAnyPinLocked
LL_GPIO_IsInputPinSet
LL_GPIO_IsOutputPinSet
LL_GPIO_IsPinLocked
LL_GPIO_LockPin
LL_GPIO_ReadInputPort
LL_GPIO_ReadOutputPort
LL_GPIO_ResetOutputPin
LL_GPIO_SetAFPin_0_7
LL_GPIO_SetAFPin_8_15
LL_GPIO_SetOutputPin
LL_GPIO_SetPinMode
LL_GPIO_SetPinOutputType
LL_GPIO_SetPinPull
LL_GPIO_SetPinSpeed
LL_GPIO_StructInit
LL_GPIO_TogglePin
LL_GPIO_WriteOutputPort
stm32g4xx_ll_hrtim.c
LL_HRTIM_DeInit
stm32g4xx_ll_hrtim.h
HRTIM_BM_CONFIG_MASK
HRTIM_CR1_UDIS_MASK
HRTIM_CR2_SWAP_MASK
HRTIM_CR2_SWRST_MASK
HRTIM_CR2_SWUPD_MASK
HRTIM_EE_CONFIG_MASK
HRTIM_FLT_CONFIG_MASK
HRTIM_FLT_SRC_1_MASK
HRTIM_OENR_ODIS_MASK
HRTIM_OENR_OEN_MASK
HRTIM_OUT_CONFIG_MASK
LL_HRTIM_ADCTRIG_1
LL_HRTIM_ADCTRIG_10
LL_HRTIM_ADCTRIG_2
LL_HRTIM_ADCTRIG_3
LL_HRTIM_ADCTRIG_4
LL_HRTIM_ADCTRIG_5
LL_HRTIM_ADCTRIG_6
LL_HRTIM_ADCTRIG_7
LL_HRTIM_ADCTRIG_8
LL_HRTIM_ADCTRIG_9
LL_HRTIM_ADCTRIG_SRC13_EEV1
LL_HRTIM_ADCTRIG_SRC13_EEV2
LL_HRTIM_ADCTRIG_SRC13_EEV3
LL_HRTIM_ADCTRIG_SRC13_EEV4
LL_HRTIM_ADCTRIG_SRC13_EEV5
LL_HRTIM_ADCTRIG_SRC13_MCMP1
LL_HRTIM_ADCTRIG_SRC13_MCMP2
LL_HRTIM_ADCTRIG_SRC13_MCMP3
LL_HRTIM_ADCTRIG_SRC13_MCMP4
LL_HRTIM_ADCTRIG_SRC13_MPER
LL_HRTIM_ADCTRIG_SRC13_NONE
LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
LL_HRTIM_ADCTRIG_SRC13_TIMAPER
LL_HRTIM_ADCTRIG_SRC13_TIMARST
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMBPER
LL_HRTIM_ADCTRIG_SRC13_TIMBRST
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMCPER
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMDPER
LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
LL_HRTIM_ADCTRIG_SRC13_TIMEPER
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
LL_HRTIM_ADCTRIG_SRC13_TIMFPER
LL_HRTIM_ADCTRIG_SRC13_TIMFRST
LL_HRTIM_ADCTRIG_SRC24_EEV10
LL_HRTIM_ADCTRIG_SRC24_EEV6
LL_HRTIM_ADCTRIG_SRC24_EEV7
LL_HRTIM_ADCTRIG_SRC24_EEV8
LL_HRTIM_ADCTRIG_SRC24_EEV9
LL_HRTIM_ADCTRIG_SRC24_MCMP1
LL_HRTIM_ADCTRIG_SRC24_MCMP2
LL_HRTIM_ADCTRIG_SRC24_MCMP3
LL_HRTIM_ADCTRIG_SRC24_MCMP4
LL_HRTIM_ADCTRIG_SRC24_MPER
LL_HRTIM_ADCTRIG_SRC24_NONE
LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
LL_HRTIM_ADCTRIG_SRC24_TIMAPER
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMBPER
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMCPER
LL_HRTIM_ADCTRIG_SRC24_TIMCRST
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMDPER
LL_HRTIM_ADCTRIG_SRC24_TIMDRST
LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
LL_HRTIM_ADCTRIG_SRC24_TIMERST
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
LL_HRTIM_ADCTRIG_SRC24_TIMFPER
LL_HRTIM_ADCTRIG_SRC579_EEV1
LL_HRTIM_ADCTRIG_SRC579_EEV2
LL_HRTIM_ADCTRIG_SRC579_EEV3
LL_HRTIM_ADCTRIG_SRC579_EEV4
LL_HRTIM_ADCTRIG_SRC579_EEV5
LL_HRTIM_ADCTRIG_SRC579_MCMP1
LL_HRTIM_ADCTRIG_SRC579_MCMP2
LL_HRTIM_ADCTRIG_SRC579_MCMP3
LL_HRTIM_ADCTRIG_SRC579_MCMP4
LL_HRTIM_ADCTRIG_SRC579_MPER
LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIME_PER
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
LL_HRTIM_ADCTRIG_SRC6810_EEV10
LL_HRTIM_ADCTRIG_SRC6810_EEV6
LL_HRTIM_ADCTRIG_SRC6810_EEV7
LL_HRTIM_ADCTRIG_SRC6810_EEV8
LL_HRTIM_ADCTRIG_SRC6810_EEV9
LL_HRTIM_ADCTRIG_SRC6810_MCMP1
LL_HRTIM_ADCTRIG_SRC6810_MCMP2
LL_HRTIM_ADCTRIG_SRC6810_MCMP3
LL_HRTIM_ADCTRIG_SRC6810_MCMP4
LL_HRTIM_ADCTRIG_SRC6810_MPER
LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
LL_HRTIM_ADCTRIG_UPDATE_MASTER
LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
LL_HRTIM_BM_CLKSRC_FHRTIM
LL_HRTIM_BM_CLKSRC_MASTER
LL_HRTIM_BM_CLKSRC_TIM16_OC
LL_HRTIM_BM_CLKSRC_TIM17_OC
LL_HRTIM_BM_CLKSRC_TIM7_TRGO
LL_HRTIM_BM_CLKSRC_TIMER_A
LL_HRTIM_BM_CLKSRC_TIMER_B
LL_HRTIM_BM_CLKSRC_TIMER_C
LL_HRTIM_BM_CLKSRC_TIMER_D
LL_HRTIM_BM_CLKSRC_TIMER_E
LL_HRTIM_BM_CLKSRC_TIMER_F
LL_HRTIM_BM_MODE_CONTINOUS
LL_HRTIM_BM_MODE_SINGLESHOT
LL_HRTIM_BM_PRESCALER_DIV1
LL_HRTIM_BM_PRESCALER_DIV1024
LL_HRTIM_BM_PRESCALER_DIV128
LL_HRTIM_BM_PRESCALER_DIV16
LL_HRTIM_BM_PRESCALER_DIV16384
LL_HRTIM_BM_PRESCALER_DIV2
LL_HRTIM_BM_PRESCALER_DIV2048
LL_HRTIM_BM_PRESCALER_DIV256
LL_HRTIM_BM_PRESCALER_DIV32
LL_HRTIM_BM_PRESCALER_DIV32768
LL_HRTIM_BM_PRESCALER_DIV4
LL_HRTIM_BM_PRESCALER_DIV4096
LL_HRTIM_BM_PRESCALER_DIV512
LL_HRTIM_BM_PRESCALER_DIV64
LL_HRTIM_BM_PRESCALER_DIV8
LL_HRTIM_BM_PRESCALER_DIV8192
LL_HRTIM_BM_STATUS_BURST_ONGOING
LL_HRTIM_BM_STATUS_NORMAL
LL_HRTIM_BM_TRIG_EVENT_7
LL_HRTIM_BM_TRIG_EVENT_8
LL_HRTIM_BM_TRIG_EVENT_ONCHIP
LL_HRTIM_BM_TRIG_MASTER_CMP1
LL_HRTIM_BM_TRIG_MASTER_CMP2
LL_HRTIM_BM_TRIG_MASTER_CMP3
LL_HRTIM_BM_TRIG_MASTER_CMP4
LL_HRTIM_BM_TRIG_MASTER_REPETITION
LL_HRTIM_BM_TRIG_MASTER_RESET
LL_HRTIM_BM_TRIG_NONE
LL_HRTIM_BM_TRIG_TIMA_CMP1
LL_HRTIM_BM_TRIG_TIMA_CMP2
LL_HRTIM_BM_TRIG_TIMA_EVENT7
LL_HRTIM_BM_TRIG_TIMA_REPETITION
LL_HRTIM_BM_TRIG_TIMA_RESET
LL_HRTIM_BM_TRIG_TIMB_CMP1
LL_HRTIM_BM_TRIG_TIMB_CMP2
LL_HRTIM_BM_TRIG_TIMB_REPETITION
LL_HRTIM_BM_TRIG_TIMB_RESET
LL_HRTIM_BM_TRIG_TIMC_CMP1
LL_HRTIM_BM_TRIG_TIMC_REPETITION
LL_HRTIM_BM_TRIG_TIMC_RESET
LL_HRTIM_BM_TRIG_TIMD_CMP2
LL_HRTIM_BM_TRIG_TIMD_EVENT8
LL_HRTIM_BM_TRIG_TIMD_REPETITION
LL_HRTIM_BM_TRIG_TIMD_RESET
LL_HRTIM_BM_TRIG_TIME_CMP1
LL_HRTIM_BM_TRIG_TIME_CMP2
LL_HRTIM_BM_TRIG_TIME_REPETITION
LL_HRTIM_BM_TRIG_TIMF_CMP1
LL_HRTIM_BM_TRIG_TIMF_REPETITION
LL_HRTIM_BM_TRIG_TIMF_RESET
LL_HRTIM_BURSTDMA_CR2
LL_HRTIM_BURSTDMA_EEFR3
LL_HRTIM_BURSTDMA_MCMP1
LL_HRTIM_BURSTDMA_MCMP2
LL_HRTIM_BURSTDMA_MCMP3
LL_HRTIM_BURSTDMA_MCMP4
LL_HRTIM_BURSTDMA_MCNT
LL_HRTIM_BURSTDMA_MCR
LL_HRTIM_BURSTDMA_MDIER
LL_HRTIM_BURSTDMA_MICR
LL_HRTIM_BURSTDMA_MPER
LL_HRTIM_BURSTDMA_MREP
LL_HRTIM_BURSTDMA_NONE
LL_HRTIM_BURSTDMA_TIMCHPR
LL_HRTIM_BURSTDMA_TIMCMP1
LL_HRTIM_BURSTDMA_TIMCMP2
LL_HRTIM_BURSTDMA_TIMCMP3
LL_HRTIM_BURSTDMA_TIMCMP4
LL_HRTIM_BURSTDMA_TIMCNT
LL_HRTIM_BURSTDMA_TIMDIER
LL_HRTIM_BURSTDMA_TIMDTR
LL_HRTIM_BURSTDMA_TIMEEFR1
LL_HRTIM_BURSTDMA_TIMEEFR2
LL_HRTIM_BURSTDMA_TIMFLTR
LL_HRTIM_BURSTDMA_TIMICR
LL_HRTIM_BURSTDMA_TIMMCR
LL_HRTIM_BURSTDMA_TIMOUTR
LL_HRTIM_BURSTDMA_TIMPER
LL_HRTIM_BURSTDMA_TIMREP
LL_HRTIM_BURSTDMA_TIMRST1R
LL_HRTIM_BURSTDMA_TIMRST2R
LL_HRTIM_BURSTDMA_TIMRSTR
LL_HRTIM_BURSTDMA_TIMSET1R
LL_HRTIM_BURSTDMA_TIMSET2R
LL_HRTIM_BURSTMODE_MAINTAINCLOCK
LL_HRTIM_BURSTMODE_RESETCOUNTER
LL_HRTIM_CAPTURETRIG_EEV_1
LL_HRTIM_CAPTURETRIG_EEV_10
LL_HRTIM_CAPTURETRIG_EEV_2
LL_HRTIM_CAPTURETRIG_EEV_3
LL_HRTIM_CAPTURETRIG_EEV_4
LL_HRTIM_CAPTURETRIG_EEV_5
LL_HRTIM_CAPTURETRIG_EEV_6
LL_HRTIM_CAPTURETRIG_EEV_7
LL_HRTIM_CAPTURETRIG_EEV_8
LL_HRTIM_CAPTURETRIG_EEV_9
LL_HRTIM_CAPTURETRIG_NONE
LL_HRTIM_CAPTURETRIG_SW
LL_HRTIM_CAPTURETRIG_TA1_RESET
LL_HRTIM_CAPTURETRIG_TA1_SET
LL_HRTIM_CAPTURETRIG_TB1_RESET
LL_HRTIM_CAPTURETRIG_TB1_SET
LL_HRTIM_CAPTURETRIG_TC1_RESET
LL_HRTIM_CAPTURETRIG_TC1_SET
LL_HRTIM_CAPTURETRIG_TD1_RESET
LL_HRTIM_CAPTURETRIG_TD1_SET
LL_HRTIM_CAPTURETRIG_TE1_RESET
LL_HRTIM_CAPTURETRIG_TE1_SET
LL_HRTIM_CAPTURETRIG_TF1_RESET
LL_HRTIM_CAPTURETRIG_TF1_SET
LL_HRTIM_CAPTURETRIG_TIMA_CMP1
LL_HRTIM_CAPTURETRIG_TIMA_CMP2
LL_HRTIM_CAPTURETRIG_TIMB_CMP1
LL_HRTIM_CAPTURETRIG_TIMB_CMP2
LL_HRTIM_CAPTURETRIG_TIMC_CMP1
LL_HRTIM_CAPTURETRIG_TIMC_CMP2
LL_HRTIM_CAPTURETRIG_TIMD_CMP1
LL_HRTIM_CAPTURETRIG_TIMD_CMP2
LL_HRTIM_CAPTURETRIG_TIME_CMP1
LL_HRTIM_CAPTURETRIG_TIME_CMP2
LL_HRTIM_CAPTURETRIG_TIMF_CMP1
LL_HRTIM_CAPTURETRIG_TIMF_CMP2
LL_HRTIM_CAPTURETRIG_UPDATE
LL_HRTIM_CAPTUREUNIT_1
LL_HRTIM_CAPTUREUNIT_2
LL_HRTIM_CHP_DUTYCYCLE_0
LL_HRTIM_CHP_DUTYCYCLE_125
LL_HRTIM_CHP_DUTYCYCLE_250
LL_HRTIM_CHP_DUTYCYCLE_375
LL_HRTIM_CHP_DUTYCYCLE_500
LL_HRTIM_CHP_DUTYCYCLE_625
LL_HRTIM_CHP_DUTYCYCLE_750
LL_HRTIM_CHP_DUTYCYCLE_875
LL_HRTIM_CHP_PRESCALER_DIV112
LL_HRTIM_CHP_PRESCALER_DIV128
LL_HRTIM_CHP_PRESCALER_DIV144
LL_HRTIM_CHP_PRESCALER_DIV16
LL_HRTIM_CHP_PRESCALER_DIV160
LL_HRTIM_CHP_PRESCALER_DIV176
LL_HRTIM_CHP_PRESCALER_DIV192
LL_HRTIM_CHP_PRESCALER_DIV208
LL_HRTIM_CHP_PRESCALER_DIV224
LL_HRTIM_CHP_PRESCALER_DIV240
LL_HRTIM_CHP_PRESCALER_DIV256
LL_HRTIM_CHP_PRESCALER_DIV32
LL_HRTIM_CHP_PRESCALER_DIV48
LL_HRTIM_CHP_PRESCALER_DIV64
LL_HRTIM_CHP_PRESCALER_DIV80
LL_HRTIM_CHP_PRESCALER_DIV96
LL_HRTIM_CHP_PULSEWIDTH_112
LL_HRTIM_CHP_PULSEWIDTH_128
LL_HRTIM_CHP_PULSEWIDTH_144
LL_HRTIM_CHP_PULSEWIDTH_16
LL_HRTIM_CHP_PULSEWIDTH_160
LL_HRTIM_CHP_PULSEWIDTH_176
LL_HRTIM_CHP_PULSEWIDTH_192
LL_HRTIM_CHP_PULSEWIDTH_208
LL_HRTIM_CHP_PULSEWIDTH_224
LL_HRTIM_CHP_PULSEWIDTH_240
LL_HRTIM_CHP_PULSEWIDTH_256
LL_HRTIM_CHP_PULSEWIDTH_32
LL_HRTIM_CHP_PULSEWIDTH_48
LL_HRTIM_CHP_PULSEWIDTH_64
LL_HRTIM_CHP_PULSEWIDTH_80
LL_HRTIM_CHP_PULSEWIDTH_96
LL_HRTIM_COMPAREMODE_DELAY_CMP1
LL_HRTIM_COMPAREMODE_DELAY_CMP3
LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
LL_HRTIM_COMPAREMODE_REGULAR
LL_HRTIM_COMPAREUNIT_2
LL_HRTIM_COMPAREUNIT_4
LL_HRTIM_COUNTING_MODE_UP
LL_HRTIM_COUNTING_MODE_UP_DOWN
LL_HRTIM_CPPSTAT_OUTPUT1
LL_HRTIM_CPPSTAT_OUTPUT2
LL_HRTIM_DACTRIG_DACTRIGOUT_1
LL_HRTIM_DACTRIG_DACTRIGOUT_2
LL_HRTIM_DACTRIG_DACTRIGOUT_3
LL_HRTIM_DACTRIG_NONE
LL_HRTIM_DCDE_DISABLED
LL_HRTIM_DCDE_ENABLED
LL_HRTIM_DCDR_COUNTER
LL_HRTIM_DCDR_OUT1SET
LL_HRTIM_DCDS_CMP2
LL_HRTIM_DCDS_OUT1RST
LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
LL_HRTIM_DLLCALIBRATION_RATE_0
LL_HRTIM_DLLCALIBRATION_RATE_1
LL_HRTIM_DLLCALIBRATION_RATE_2
LL_HRTIM_DLLCALIBRATION_RATE_3
LL_HRTIM_DLYPRT_BALANCED_EEV6
LL_HRTIM_DLYPRT_BALANCED_EEV7
LL_HRTIM_DLYPRT_BALANCED_EEV8
LL_HRTIM_DLYPRT_BALANCED_EEV9
LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
LL_HRTIM_DT_FALLING_NEGATIVE
LL_HRTIM_DT_FALLING_POSITIVE
LL_HRTIM_DT_PRESCALER_DIV1
LL_HRTIM_DT_PRESCALER_DIV2
LL_HRTIM_DT_PRESCALER_DIV4
LL_HRTIM_DT_PRESCALER_DIV8
LL_HRTIM_DT_PRESCALER_MUL16
LL_HRTIM_DT_PRESCALER_MUL2
LL_HRTIM_DT_PRESCALER_MUL4
LL_HRTIM_DT_PRESCALER_MUL8
LL_HRTIM_DT_RISING_NEGATIVE
LL_HRTIM_DT_RISING_POSITIVE
LL_HRTIM_EE_COUNTER_A
LL_HRTIM_EE_COUNTER_B
LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
LL_HRTIM_EE_FASTMODE_DISABLE
LL_HRTIM_EE_FASTMODE_ENABLE
LL_HRTIM_EE_FILTER_1
LL_HRTIM_EE_FILTER_10
LL_HRTIM_EE_FILTER_11
LL_HRTIM_EE_FILTER_12
LL_HRTIM_EE_FILTER_13
LL_HRTIM_EE_FILTER_14
LL_HRTIM_EE_FILTER_15
LL_HRTIM_EE_FILTER_2
LL_HRTIM_EE_FILTER_3
LL_HRTIM_EE_FILTER_4
LL_HRTIM_EE_FILTER_5
LL_HRTIM_EE_FILTER_6
LL_HRTIM_EE_FILTER_7
LL_HRTIM_EE_FILTER_8
LL_HRTIM_EE_FILTER_9
LL_HRTIM_EE_FILTER_NONE
LL_HRTIM_EE_POLARITY_HIGH
LL_HRTIM_EE_POLARITY_LOW
LL_HRTIM_EE_PRESCALER_DIV1
LL_HRTIM_EE_PRESCALER_DIV2
LL_HRTIM_EE_PRESCALER_DIV4
LL_HRTIM_EE_PRESCALER_DIV8
LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
LL_HRTIM_EE_SENSITIVITY_LEVEL
LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
LL_HRTIM_EEFLTR_BLANKINGCMP1
LL_HRTIM_EEFLTR_BLANKINGCMP2
LL_HRTIM_EEFLTR_BLANKINGCMP3
LL_HRTIM_EEFLTR_BLANKINGCMP4
LL_HRTIM_EEFLTR_NONE
LL_HRTIM_EEFLTR_WINDOWINGCMP2
LL_HRTIM_EEFLTR_WINDOWINGCMP3
LL_HRTIM_EEFLTR_WINDOWINGTIM
LL_HRTIM_EELATCH_DISABLED
LL_HRTIM_EELATCH_ENABLED
LL_HRTIM_EEV10SRC_ADC5_AWD1
LL_HRTIM_EEV10SRC_COMP7_OUT
LL_HRTIM_EEV10SRC_GPIO
LL_HRTIM_EEV10SRC_TIM6_TRGO
LL_HRTIM_EEV1SRC_ADC1_AWD1
LL_HRTIM_EEV1SRC_COMP2_OUT
LL_HRTIM_EEV1SRC_GPIO
LL_HRTIM_EEV1SRC_TIM1_TRGO
LL_HRTIM_EEV2SRC_ADC1_AWD2
LL_HRTIM_EEV2SRC_COMP4_OUT
LL_HRTIM_EEV2SRC_GPIO
LL_HRTIM_EEV2SRC_TIM2_TRGO
LL_HRTIM_EEV3SRC_ADC1_AWD3
LL_HRTIM_EEV3SRC_COMP6_OUT
LL_HRTIM_EEV3SRC_GPIO
LL_HRTIM_EEV3SRC_TIM3_TRGO
LL_HRTIM_EEV4SRC_ADC2_AWD1
LL_HRTIM_EEV4SRC_COMP1_OUT
LL_HRTIM_EEV4SRC_COMP5_OUT
LL_HRTIM_EEV4SRC_GPIO
LL_HRTIM_EEV5SRC_ADC2_AWD2
LL_HRTIM_EEV5SRC_COMP3_OUT
LL_HRTIM_EEV5SRC_COMP7_OUT
LL_HRTIM_EEV5SRC_GPIO
LL_HRTIM_EEV6SRC_ADC2_AWD3
LL_HRTIM_EEV6SRC_COMP1_OUT
LL_HRTIM_EEV6SRC_COMP2_OUT
LL_HRTIM_EEV6SRC_GPIO
LL_HRTIM_EEV7SRC_ADC3_AWD1
LL_HRTIM_EEV7SRC_COMP4_OUT
LL_HRTIM_EEV7SRC_GPIO
LL_HRTIM_EEV7SRC_TIM7_TRGO
LL_HRTIM_EEV8SRC_ADC4_AWD1
LL_HRTIM_EEV8SRC_COMP3_OUT
LL_HRTIM_EEV8SRC_COMP6_OUT
LL_HRTIM_EEV8SRC_GPIO
LL_HRTIM_EEV9SRC_COMP4_OUT
LL_HRTIM_EEV9SRC_COMP5_OUT
LL_HRTIM_EEV9SRC_GPIO
LL_HRTIM_EEV9SRC_TIM15_TRGO
LL_HRTIM_EVENT_1
LL_HRTIM_EVENT_10
LL_HRTIM_EVENT_2
LL_HRTIM_EVENT_3
LL_HRTIM_EVENT_4
LL_HRTIM_EVENT_5
LL_HRTIM_EVENT_6
LL_HRTIM_EVENT_7
LL_HRTIM_EVENT_8
LL_HRTIM_EVENT_9
LL_HRTIM_FAULT_1
LL_HRTIM_FAULT_2
LL_HRTIM_FAULT_3
LL_HRTIM_FAULT_4
LL_HRTIM_FAULT_5
LL_HRTIM_FAULT_6
LL_HRTIM_FLT_BLANKING_MOVING
LL_HRTIM_FLT_BLANKING_RSTALIGNED
LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
LL_HRTIM_FLT_FILTER_1
LL_HRTIM_FLT_FILTER_10
LL_HRTIM_FLT_FILTER_11
LL_HRTIM_FLT_FILTER_12
LL_HRTIM_FLT_FILTER_13
LL_HRTIM_FLT_FILTER_14
LL_HRTIM_FLT_FILTER_15
LL_HRTIM_FLT_FILTER_2
LL_HRTIM_FLT_FILTER_3
LL_HRTIM_FLT_FILTER_4
LL_HRTIM_FLT_FILTER_5
LL_HRTIM_FLT_FILTER_6
LL_HRTIM_FLT_FILTER_7
LL_HRTIM_FLT_FILTER_8
LL_HRTIM_FLT_FILTER_9
LL_HRTIM_FLT_FILTER_NONE
LL_HRTIM_FLT_POLARITY_HIGH
LL_HRTIM_FLT_POLARITY_LOW
LL_HRTIM_FLT_PRESCALER_DIV1
LL_HRTIM_FLT_PRESCALER_DIV2
LL_HRTIM_FLT_PRESCALER_DIV4
LL_HRTIM_FLT_PRESCALER_DIV8
LL_HRTIM_FLT_SRC_DIGITALINPUT
LL_HRTIM_FLT_SRC_EEVINPUT
LL_HRTIM_FLT_SRC_INTERNAL
LL_HRTIM_GTCMP1_EQUAL
LL_HRTIM_GTCMP1_GREATER
LL_HRTIM_GTCMP3_EQUAL
LL_HRTIM_GTCMP3_GREATER
LL_HRTIM_HALF_MODE_DISABLED
LL_HRTIM_HALF_MODE_ENABLE
LL_HRTIM_IER_BMPERIE
LL_HRTIM_IER_DLLRDYIE
LL_HRTIM_IER_FLT1IE
LL_HRTIM_IER_FLT2IE
LL_HRTIM_IER_FLT3IE
LL_HRTIM_IER_FLT4IE
LL_HRTIM_IER_FLT5IE
LL_HRTIM_IER_FLT6IE
LL_HRTIM_IER_SYSFLTIE
LL_HRTIM_INTERLEAVED_MODE_DISABLED
LL_HRTIM_INTERLEAVED_MODE_DUAL
LL_HRTIM_INTERLEAVED_MODE_QUAD
LL_HRTIM_INTERLEAVED_MODE_TRIPLE
LL_HRTIM_IPPSTAT_OUTPUT1
LL_HRTIM_IPPSTAT_OUTPUT2
LL_HRTIM_ISR_BMPER
LL_HRTIM_ISR_DLLRDY
LL_HRTIM_ISR_FLT1
LL_HRTIM_ISR_FLT2
LL_HRTIM_ISR_FLT3
LL_HRTIM_ISR_FLT4
LL_HRTIM_ISR_FLT5
LL_HRTIM_ISR_FLT6
LL_HRTIM_ISR_SYSFLT
LL_HRTIM_MDIER_MCMP1IE
LL_HRTIM_MDIER_MCMP2IE
LL_HRTIM_MDIER_MCMP3IE
LL_HRTIM_MDIER_MCMP4IE
LL_HRTIM_MDIER_MREPIE
LL_HRTIM_MDIER_MUPDIE
LL_HRTIM_MDIER_SYNCIE
LL_HRTIM_MISR_MCMP1
LL_HRTIM_MISR_MCMP2
LL_HRTIM_MISR_MCMP3
LL_HRTIM_MISR_MCMP4
LL_HRTIM_MISR_MREP
LL_HRTIM_MISR_MUPD
LL_HRTIM_MISR_SYNC
LL_HRTIM_MODE_CONTINUOUS
LL_HRTIM_MODE_RETRIGGERABLE
LL_HRTIM_MODE_SINGLESHOT
LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
LL_HRTIM_OUT_CHOPPERMODE_DISABLED
LL_HRTIM_OUT_CHOPPERMODE_ENABLED
LL_HRTIM_OUT_FAULTSTATE_ACTIVE
LL_HRTIM_OUT_FAULTSTATE_HIGHZ
LL_HRTIM_OUT_FAULTSTATE_INACTIVE
LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
LL_HRTIM_OUT_IDLE_WHEN_BURST
LL_HRTIM_OUT_IDLELEVEL_ACTIVE
LL_HRTIM_OUT_IDLELEVEL_INACTIVE
LL_HRTIM_OUT_LEVEL_ACTIVE
LL_HRTIM_OUT_LEVEL_INACTIVE
LL_HRTIM_OUT_NEGATIVE_POLARITY
LL_HRTIM_OUT_NO_IDLE
LL_HRTIM_OUT_POSITIVE_POLARITY
LL_HRTIM_OUTPUT_TA1
LL_HRTIM_OUTPUT_TA2
LL_HRTIM_OUTPUT_TB1
LL_HRTIM_OUTPUT_TB2
LL_HRTIM_OUTPUT_TC1
LL_HRTIM_OUTPUT_TC2
LL_HRTIM_OUTPUT_TD1
LL_HRTIM_OUTPUT_TD2
LL_HRTIM_OUTPUT_TE1
LL_HRTIM_OUTPUT_TE2
LL_HRTIM_OUTPUT_TF1
LL_HRTIM_OUTPUT_TF2
LL_HRTIM_OUTPUTRESET_EEV_1
LL_HRTIM_OUTPUTRESET_EEV_10
LL_HRTIM_OUTPUTRESET_EEV_2
LL_HRTIM_OUTPUTRESET_EEV_3
LL_HRTIM_OUTPUTRESET_EEV_4
LL_HRTIM_OUTPUTRESET_EEV_5
LL_HRTIM_OUTPUTRESET_EEV_6
LL_HRTIM_OUTPUTRESET_EEV_7
LL_HRTIM_OUTPUTRESET_EEV_8
LL_HRTIM_OUTPUTRESET_EEV_9
LL_HRTIM_OUTPUTRESET_MASTERCMP1
LL_HRTIM_OUTPUTRESET_MASTERCMP2
LL_HRTIM_OUTPUTRESET_MASTERCMP3
LL_HRTIM_OUTPUTRESET_MASTERCMP4
LL_HRTIM_OUTPUTRESET_MASTERPER
LL_HRTIM_OUTPUTRESET_NONE
LL_HRTIM_OUTPUTRESET_RESYNC
LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP1
LL_HRTIM_OUTPUTRESET_TIMCMP2
LL_HRTIM_OUTPUTRESET_TIMCMP3
LL_HRTIM_OUTPUTRESET_TIMCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
LL_HRTIM_OUTPUTRESET_TIMPER
LL_HRTIM_OUTPUTRESET_UPDATE
LL_HRTIM_OUTPUTSET_EEV_1
LL_HRTIM_OUTPUTSET_EEV_10
LL_HRTIM_OUTPUTSET_EEV_2
LL_HRTIM_OUTPUTSET_EEV_3
LL_HRTIM_OUTPUTSET_EEV_4
LL_HRTIM_OUTPUTSET_EEV_5
LL_HRTIM_OUTPUTSET_EEV_6
LL_HRTIM_OUTPUTSET_EEV_7
LL_HRTIM_OUTPUTSET_EEV_8
LL_HRTIM_OUTPUTSET_EEV_9
LL_HRTIM_OUTPUTSET_MASTERCMP1
LL_HRTIM_OUTPUTSET_MASTERCMP2
LL_HRTIM_OUTPUTSET_MASTERCMP3
LL_HRTIM_OUTPUTSET_MASTERCMP4
LL_HRTIM_OUTPUTSET_MASTERPER
LL_HRTIM_OUTPUTSET_NONE
LL_HRTIM_OUTPUTSET_RESYNC
LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
LL_HRTIM_OUTPUTSET_TIMCMP1
LL_HRTIM_OUTPUTSET_TIMCMP2
LL_HRTIM_OUTPUTSET_TIMCMP3
LL_HRTIM_OUTPUTSET_TIMCMP4
LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
LL_HRTIM_OUTPUTSET_TIMPER
LL_HRTIM_OUTPUTSET_UPDATE
LL_HRTIM_OUTPUTSTATE_FAULT
LL_HRTIM_OUTPUTSTATE_IDLE
LL_HRTIM_OUTPUTSTATE_RUN
LL_HRTIM_PRESCALERRATIO_DIV1
LL_HRTIM_PRESCALERRATIO_DIV2
LL_HRTIM_PRESCALERRATIO_DIV4
LL_HRTIM_PRESCALERRATIO_MUL16
LL_HRTIM_PRESCALERRATIO_MUL2
LL_HRTIM_PRESCALERRATIO_MUL32
LL_HRTIM_PRESCALERRATIO_MUL4
LL_HRTIM_PRESCALERRATIO_MUL8
LL_HRTIM_ReadReg
LL_HRTIM_RESETTRIG_CMP2
LL_HRTIM_RESETTRIG_CMP4
LL_HRTIM_RESETTRIG_EEV_1
LL_HRTIM_RESETTRIG_EEV_10
LL_HRTIM_RESETTRIG_EEV_2
LL_HRTIM_RESETTRIG_EEV_3
LL_HRTIM_RESETTRIG_EEV_4
LL_HRTIM_RESETTRIG_EEV_5
LL_HRTIM_RESETTRIG_EEV_6
LL_HRTIM_RESETTRIG_EEV_7
LL_HRTIM_RESETTRIG_EEV_8
LL_HRTIM_RESETTRIG_EEV_9
LL_HRTIM_RESETTRIG_MASTER_CMP1
LL_HRTIM_RESETTRIG_MASTER_CMP2
LL_HRTIM_RESETTRIG_MASTER_CMP3
LL_HRTIM_RESETTRIG_MASTER_CMP4
LL_HRTIM_RESETTRIG_MASTER_PER
LL_HRTIM_RESETTRIG_NONE
LL_HRTIM_RESETTRIG_OTHER1_CMP1
LL_HRTIM_RESETTRIG_OTHER1_CMP2
LL_HRTIM_RESETTRIG_OTHER1_CMP4
LL_HRTIM_RESETTRIG_OTHER2_CMP1
LL_HRTIM_RESETTRIG_OTHER2_CMP2
LL_HRTIM_RESETTRIG_OTHER2_CMP4
LL_HRTIM_RESETTRIG_OTHER3_CMP1
LL_HRTIM_RESETTRIG_OTHER3_CMP2
LL_HRTIM_RESETTRIG_OTHER3_CMP4
LL_HRTIM_RESETTRIG_OTHER4_CMP1
LL_HRTIM_RESETTRIG_OTHER4_CMP2
LL_HRTIM_RESETTRIG_OTHER4_CMP4
LL_HRTIM_RESETTRIG_OTHER5_CMP1
LL_HRTIM_RESETTRIG_OTHER5_CMP2
LL_HRTIM_RESETTRIG_UPDATE
LL_HRTIM_ROLLOVER_MODE_BOTH
LL_HRTIM_ROLLOVER_MODE_PER
LL_HRTIM_ROLLOVER_MODE_RST
LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
LL_HRTIM_SYNCIN_SRC_NONE
LL_HRTIM_SYNCIN_SRC_TIM_EVENT
LL_HRTIM_SYNCOUT_DISABLED
LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
LL_HRTIM_SYNCOUT_POSITIVE_PULSE
LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
LL_HRTIM_SYNCOUT_SRC_MASTER_START
LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
LL_HRTIM_SYNCOUT_SRC_TIMA_START
LL_HRTIM_TIMDIER_CMP1IE
LL_HRTIM_TIMDIER_CMP2IE
LL_HRTIM_TIMDIER_CMP3IE
LL_HRTIM_TIMDIER_CMP4IE
LL_HRTIM_TIMDIER_CPT1IE
LL_HRTIM_TIMDIER_CPT2IE
LL_HRTIM_TIMDIER_DLYPRTIE
LL_HRTIM_TIMDIER_REPIE
LL_HRTIM_TIMDIER_RST1IE
LL_HRTIM_TIMDIER_RST2IE
LL_HRTIM_TIMDIER_RSTIE
LL_HRTIM_TIMDIER_SET1IE
LL_HRTIM_TIMDIER_SET2IE
LL_HRTIM_TIMDIER_UPDIE
LL_HRTIM_TIMER_A
LL_HRTIM_TIMER_ALL
LL_HRTIM_TIMER_B
LL_HRTIM_TIMER_C
LL_HRTIM_TIMER_D
LL_HRTIM_TIMER_E
LL_HRTIM_TIMER_F
LL_HRTIM_TIMER_MASTER
LL_HRTIM_TIMER_NONE
LL_HRTIM_TIMER_X
LL_HRTIM_TIMISR_CMP1
LL_HRTIM_TIMISR_CMP2
LL_HRTIM_TIMISR_CMP3
LL_HRTIM_TIMISR_CMP4
LL_HRTIM_TIMISR_CPT1
LL_HRTIM_TIMISR_CPT2
LL_HRTIM_TIMISR_DLYPRT
LL_HRTIM_TIMISR_REP
LL_HRTIM_TIMISR_RST
LL_HRTIM_TIMISR_RST1
LL_HRTIM_TIMISR_RST2
LL_HRTIM_TIMISR_SET1
LL_HRTIM_TIMISR_SET2
LL_HRTIM_TIMISR_UPD
LL_HRTIM_TRIGHALF_DISABLED
LL_HRTIM_TRIGHALF_ENABLED
LL_HRTIM_UPDATEGATING_DMABURST
LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
LL_HRTIM_UPDATEGATING_INDEPENDENT
LL_HRTIM_UPDATEGATING_UPDEN1
LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
LL_HRTIM_UPDATEGATING_UPDEN2
LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
LL_HRTIM_UPDATEGATING_UPDEN3
LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
LL_HRTIM_UPDATETRIG_MASTER
LL_HRTIM_UPDATETRIG_NONE
LL_HRTIM_UPDATETRIG_REPETITION
LL_HRTIM_UPDATETRIG_RESET
LL_HRTIM_UPDATETRIG_TIMER_A
LL_HRTIM_UPDATETRIG_TIMER_B
LL_HRTIM_UPDATETRIG_TIMER_C
LL_HRTIM_UPDATETRIG_TIMER_D
LL_HRTIM_UPDATETRIG_TIMER_E
LL_HRTIM_UPDATETRIG_TIMER_F
LL_HRTIM_WriteReg
LL_HRTIM_BM_Config
LL_HRTIM_BM_Disable
LL_HRTIM_BM_DisablePreload
LL_HRTIM_BM_Enable
LL_HRTIM_BM_EnablePreload
LL_HRTIM_BM_GetClockSrc
LL_HRTIM_BM_GetCompare
LL_HRTIM_BM_GetMode
LL_HRTIM_BM_GetPeriod
LL_HRTIM_BM_GetPrescaler
LL_HRTIM_BM_GetStatus
LL_HRTIM_BM_GetTrig
LL_HRTIM_BM_IsEnabled
LL_HRTIM_BM_IsEnabledPreload
LL_HRTIM_BM_SetClockSrc
LL_HRTIM_BM_SetCompare
LL_HRTIM_BM_SetMode
LL_HRTIM_BM_SetPeriod
LL_HRTIM_BM_SetPrescaler
LL_HRTIM_BM_SetTrig
LL_HRTIM_BM_Start
LL_HRTIM_BM_Stop
LL_HRTIM_CHP_Config
LL_HRTIM_CHP_GetDutyCycle
LL_HRTIM_CHP_GetPrescaler
LL_HRTIM_CHP_GetPulseWidth
LL_HRTIM_CHP_SetDutyCycle
LL_HRTIM_CHP_SetPrescaler
LL_HRTIM_CHP_SetPulseWidth
LL_HRTIM_ClearFlag_BMPER
LL_HRTIM_ClearFlag_CMP1
LL_HRTIM_ClearFlag_CMP2
LL_HRTIM_ClearFlag_CMP3
LL_HRTIM_ClearFlag_CMP4
LL_HRTIM_ClearFlag_CPT1
LL_HRTIM_ClearFlag_CPT2
LL_HRTIM_ClearFlag_DLLRDY
LL_HRTIM_ClearFlag_DLYPRT
LL_HRTIM_ClearFlag_FLT1
LL_HRTIM_ClearFlag_FLT2
LL_HRTIM_ClearFlag_FLT3
LL_HRTIM_ClearFlag_FLT4
LL_HRTIM_ClearFlag_FLT5
LL_HRTIM_ClearFlag_FLT6
LL_HRTIM_ClearFlag_REP
LL_HRTIM_ClearFlag_RST
LL_HRTIM_ClearFlag_RST1
LL_HRTIM_ClearFlag_RST2
LL_HRTIM_ClearFlag_SET1
LL_HRTIM_ClearFlag_SET2
LL_HRTIM_ClearFlag_SYNC
LL_HRTIM_ClearFlag_SYSFLT
LL_HRTIM_ClearFlag_UPDATE
LL_HRTIM_ConfigADCTrig
LL_HRTIM_ConfigDLLCalibration
LL_HRTIM_ConfigSyncOut
LL_HRTIM_CounterReset
LL_HRTIM_DeInit
LL_HRTIM_DisableDMAReq_CMP1
LL_HRTIM_DisableDMAReq_CMP2
LL_HRTIM_DisableDMAReq_CMP3
LL_HRTIM_DisableDMAReq_CMP4
LL_HRTIM_DisableDMAReq_CPT1
LL_HRTIM_DisableDMAReq_CPT2
LL_HRTIM_DisableDMAReq_DLYPRT
LL_HRTIM_DisableDMAReq_REP
LL_HRTIM_DisableDMAReq_RST
LL_HRTIM_DisableDMAReq_RST1
LL_HRTIM_DisableDMAReq_RST2
LL_HRTIM_DisableDMAReq_SET1
LL_HRTIM_DisableDMAReq_SET2
LL_HRTIM_DisableDMAReq_SYNC
LL_HRTIM_DisableDMAReq_UPDATE
LL_HRTIM_DisableIT_BMPER
LL_HRTIM_DisableIT_CMP1
LL_HRTIM_DisableIT_CMP2
LL_HRTIM_DisableIT_CMP3
LL_HRTIM_DisableIT_CMP4
LL_HRTIM_DisableIT_CPT1
LL_HRTIM_DisableIT_CPT2
LL_HRTIM_DisableIT_DLLRDY
LL_HRTIM_DisableIT_DLYPRT
LL_HRTIM_DisableIT_FLT1
LL_HRTIM_DisableIT_FLT2
LL_HRTIM_DisableIT_FLT3
LL_HRTIM_DisableIT_FLT4
LL_HRTIM_DisableIT_FLT5
LL_HRTIM_DisableIT_FLT6
LL_HRTIM_DisableIT_REP
LL_HRTIM_DisableIT_RST
LL_HRTIM_DisableIT_RST1
LL_HRTIM_DisableIT_RST2
LL_HRTIM_DisableIT_SET1
LL_HRTIM_DisableIT_SET2
LL_HRTIM_DisableIT_SYNC
LL_HRTIM_DisableIT_SYSFLT
LL_HRTIM_DisableIT_UPDATE
LL_HRTIM_DisableOutput
LL_HRTIM_DisableSwapOutputs
LL_HRTIM_DT_Config
LL_HRTIM_DT_GetFallingSign
LL_HRTIM_DT_GetFallingValue
LL_HRTIM_DT_GetPrescaler
LL_HRTIM_DT_GetRisingSign
LL_HRTIM_DT_GetRisingValue
LL_HRTIM_DT_LockFalling
LL_HRTIM_DT_LockFallingSign
LL_HRTIM_DT_LockRising
LL_HRTIM_DT_LockRisingSign
LL_HRTIM_DT_SetFallingSign
LL_HRTIM_DT_SetFallingValue
LL_HRTIM_DT_SetPrescaler
LL_HRTIM_DT_SetRisingSign
LL_HRTIM_DT_SetRisingValue
LL_HRTIM_EE_Config
LL_HRTIM_EE_GetFastMode
LL_HRTIM_EE_GetFilter
LL_HRTIM_EE_GetPolarity
LL_HRTIM_EE_GetPrescaler
LL_HRTIM_EE_GetSensitivity
LL_HRTIM_EE_GetSrc
LL_HRTIM_EE_SetFastMode
LL_HRTIM_EE_SetFilter
LL_HRTIM_EE_SetPolarity
LL_HRTIM_EE_SetPrescaler
LL_HRTIM_EE_SetSensitivity
LL_HRTIM_EE_SetSrc
LL_HRTIM_EnableDMAReq_CMP1
LL_HRTIM_EnableDMAReq_CMP2
LL_HRTIM_EnableDMAReq_CMP3
LL_HRTIM_EnableDMAReq_CMP4
LL_HRTIM_EnableDMAReq_CPT1
LL_HRTIM_EnableDMAReq_CPT2
LL_HRTIM_EnableDMAReq_DLYPRT
LL_HRTIM_EnableDMAReq_REP
LL_HRTIM_EnableDMAReq_RST
LL_HRTIM_EnableDMAReq_RST1
LL_HRTIM_EnableDMAReq_RST2
LL_HRTIM_EnableDMAReq_SET1
LL_HRTIM_EnableDMAReq_SET2
LL_HRTIM_EnableDMAReq_SYNC
LL_HRTIM_EnableDMAReq_UPDATE
LL_HRTIM_EnableIT_BMPER
LL_HRTIM_EnableIT_CMP1
LL_HRTIM_EnableIT_CMP2
LL_HRTIM_EnableIT_CMP3
LL_HRTIM_EnableIT_CMP4
LL_HRTIM_EnableIT_CPT1
LL_HRTIM_EnableIT_CPT2
LL_HRTIM_EnableIT_DLLRDY
LL_HRTIM_EnableIT_DLYPRT
LL_HRTIM_EnableIT_FLT1
LL_HRTIM_EnableIT_FLT2
LL_HRTIM_EnableIT_FLT3
LL_HRTIM_EnableIT_FLT4
LL_HRTIM_EnableIT_FLT5
LL_HRTIM_EnableIT_FLT6
LL_HRTIM_EnableIT_REP
LL_HRTIM_EnableIT_RST
LL_HRTIM_EnableIT_RST1
LL_HRTIM_EnableIT_RST2
LL_HRTIM_EnableIT_SET1
LL_HRTIM_EnableIT_SET2
LL_HRTIM_EnableIT_SYNC
LL_HRTIM_EnableIT_SYSFLT
LL_HRTIM_EnableIT_UPDATE
LL_HRTIM_EnableOutput
LL_HRTIM_EnableSwapOutputs
LL_HRTIM_FLT_Config
LL_HRTIM_FLT_Disable
LL_HRTIM_FLT_DisableBlanking
LL_HRTIM_FLT_Enable
LL_HRTIM_FLT_EnableBlanking
LL_HRTIM_FLT_GetBlankingSrc
LL_HRTIM_FLT_GetCounterThreshold
LL_HRTIM_FLT_GetFilter
LL_HRTIM_FLT_GetPolarity
LL_HRTIM_FLT_GetPrescaler
LL_HRTIM_FLT_GetResetMode
LL_HRTIM_FLT_GetSrc
LL_HRTIM_FLT_IsEnabled
LL_HRTIM_FLT_IsEnabledBlanking
LL_HRTIM_FLT_Lock
LL_HRTIM_FLT_ResetCounter
LL_HRTIM_FLT_SetBlankingSrc
LL_HRTIM_FLT_SetCounterThreshold
LL_HRTIM_FLT_SetFilter
LL_HRTIM_FLT_SetPolarity
LL_HRTIM_FLT_SetPrescaler
LL_HRTIM_FLT_SetResetMode
LL_HRTIM_FLT_SetSrc
LL_HRTIM_ForceUpdate
LL_HRTIM_GetADCPostScaler
LL_HRTIM_GetADCTrigSrc
LL_HRTIM_GetADCTrigUpdate
LL_HRTIM_GetSyncInSrc
LL_HRTIM_GetSyncOutConfig
LL_HRTIM_GetSyncOutSrc
LL_HRTIM_IsActiveFlag_BMPER
LL_HRTIM_IsActiveFlag_CMP1
LL_HRTIM_IsActiveFlag_CMP2
LL_HRTIM_IsActiveFlag_CMP3
LL_HRTIM_IsActiveFlag_CMP4
LL_HRTIM_IsActiveFlag_CPT1
LL_HRTIM_IsActiveFlag_CPT2
LL_HRTIM_IsActiveFlag_DLLRDY
LL_HRTIM_IsActiveFlag_DLYPRT
LL_HRTIM_IsActiveFlag_FLT1
LL_HRTIM_IsActiveFlag_FLT2
LL_HRTIM_IsActiveFlag_FLT3
LL_HRTIM_IsActiveFlag_FLT4
LL_HRTIM_IsActiveFlag_FLT5
LL_HRTIM_IsActiveFlag_FLT6
LL_HRTIM_IsActiveFlag_REP
LL_HRTIM_IsActiveFlag_RST
LL_HRTIM_IsActiveFlag_RST1
LL_HRTIM_IsActiveFlag_RST2
LL_HRTIM_IsActiveFlag_SET1
LL_HRTIM_IsActiveFlag_SET2
LL_HRTIM_IsActiveFlag_SYNC
LL_HRTIM_IsActiveFlag_SYSFLT
LL_HRTIM_IsActiveFlag_UPDATE
LL_HRTIM_IsDisabledOutput
LL_HRTIM_IsEnabledDMAReq_CMP1
LL_HRTIM_IsEnabledDMAReq_CMP2
LL_HRTIM_IsEnabledDMAReq_CMP3
LL_HRTIM_IsEnabledDMAReq_CMP4
LL_HRTIM_IsEnabledDMAReq_CPT1
LL_HRTIM_IsEnabledDMAReq_CPT2
LL_HRTIM_IsEnabledDMAReq_DLYPRT
LL_HRTIM_IsEnabledDMAReq_REP
LL_HRTIM_IsEnabledDMAReq_RST
LL_HRTIM_IsEnabledDMAReq_RST1
LL_HRTIM_IsEnabledDMAReq_RST2
LL_HRTIM_IsEnabledDMAReq_SET1
LL_HRTIM_IsEnabledDMAReq_SET2
LL_HRTIM_IsEnabledDMAReq_SYNC
LL_HRTIM_IsEnabledDMAReq_UPDATE
LL_HRTIM_IsEnabledIT_BMPER
LL_HRTIM_IsEnabledIT_CMP1
LL_HRTIM_IsEnabledIT_CMP2
LL_HRTIM_IsEnabledIT_CMP3
LL_HRTIM_IsEnabledIT_CMP4
LL_HRTIM_IsEnabledIT_CPT1
LL_HRTIM_IsEnabledIT_CPT2
LL_HRTIM_IsEnabledIT_DLLRDY
LL_HRTIM_IsEnabledIT_DLYPRT
LL_HRTIM_IsEnabledIT_FLT1
LL_HRTIM_IsEnabledIT_FLT2
LL_HRTIM_IsEnabledIT_FLT3
LL_HRTIM_IsEnabledIT_FLT4
LL_HRTIM_IsEnabledIT_FLT5
LL_HRTIM_IsEnabledIT_FLT6
LL_HRTIM_IsEnabledIT_REP
LL_HRTIM_IsEnabledIT_RST
LL_HRTIM_IsEnabledIT_RST1
LL_HRTIM_IsEnabledIT_RST2
LL_HRTIM_IsEnabledIT_SET1
LL_HRTIM_IsEnabledIT_SET2
LL_HRTIM_IsEnabledIT_SYNC
LL_HRTIM_IsEnabledIT_SYSFLT
LL_HRTIM_IsEnabledIT_UPDATE
LL_HRTIM_IsEnabledOutput
LL_HRTIM_IsEnabledSwapOutputs
LL_HRTIM_OUT_Config
LL_HRTIM_OUT_ForceLevel
LL_HRTIM_OUT_GetBMEntryMode
LL_HRTIM_OUT_GetChopperMode
LL_HRTIM_OUT_GetDLYPRTOutStatus
LL_HRTIM_OUT_GetFaultState
LL_HRTIM_OUT_GetIdleLevel
LL_HRTIM_OUT_GetIdleMode
LL_HRTIM_OUT_GetLevel
LL_HRTIM_OUT_GetOutputResetSrc
LL_HRTIM_OUT_GetOutputSetSrc
LL_HRTIM_OUT_GetPolarity
LL_HRTIM_OUT_SetBMEntryMode
LL_HRTIM_OUT_SetChopperMode
LL_HRTIM_OUT_SetFaultState
LL_HRTIM_OUT_SetIdleLevel
LL_HRTIM_OUT_SetIdleMode
LL_HRTIM_OUT_SetOutputResetSrc
LL_HRTIM_OUT_SetOutputSetSrc
LL_HRTIM_OUT_SetPolarity
LL_HRTIM_ResumeUpdate
LL_HRTIM_SetADCPostScaler
LL_HRTIM_SetADCTrigSrc
LL_HRTIM_SetADCTrigUpdate
LL_HRTIM_SetSyncInSrc
LL_HRTIM_SetSyncOutConfig
LL_HRTIM_SetSyncOutSrc
LL_HRTIM_StartDLLCalibration
LL_HRTIM_SuspendUpdate
LL_HRTIM_TIM_ConfigBurstDMA
LL_HRTIM_TIM_CounterDisable
LL_HRTIM_TIM_CounterEnable
LL_HRTIM_TIM_DisableBIAR
LL_HRTIM_TIM_DisableDeadTime
LL_HRTIM_TIM_DisableDLYPRT
LL_HRTIM_TIM_DisableDualDacTrigger
LL_HRTIM_TIM_DisableEventCounter
LL_HRTIM_TIM_DisableFault
LL_HRTIM_TIM_DisableHalfMode
LL_HRTIM_TIM_DisablePreload
LL_HRTIM_TIM_DisablePushPullMode
LL_HRTIM_TIM_DisableResetOnSync
LL_HRTIM_TIM_DisableResyncUpdate
LL_HRTIM_TIM_DisableStartOnSync
LL_HRTIM_TIM_EnableBIAR
LL_HRTIM_TIM_EnableDeadTime
LL_HRTIM_TIM_EnableDLYPRT
LL_HRTIM_TIM_EnableDualDacTrigger
LL_HRTIM_TIM_EnableEventCounter
LL_HRTIM_TIM_EnableFault
LL_HRTIM_TIM_EnableHalfMode
LL_HRTIM_TIM_EnablePreload
LL_HRTIM_TIM_EnablePushPullMode
LL_HRTIM_TIM_EnableResetOnSync
LL_HRTIM_TIM_EnableResyncUpdate
LL_HRTIM_TIM_EnableStartOnSync
LL_HRTIM_TIM_GetADCRollOverMode
LL_HRTIM_TIM_GetBMRollOverMode
LL_HRTIM_TIM_GetBurstModeOption
LL_HRTIM_TIM_GetCapture1
LL_HRTIM_TIM_GetCapture1Direction
LL_HRTIM_TIM_GetCapture2
LL_HRTIM_TIM_GetCapture2Direction
LL_HRTIM_TIM_GetCaptureTrig
LL_HRTIM_TIM_GetComp1Mode
LL_HRTIM_TIM_GetComp3Mode
LL_HRTIM_TIM_GetCompare1
LL_HRTIM_TIM_GetCompare2
LL_HRTIM_TIM_GetCompare3
LL_HRTIM_TIM_GetCompare4
LL_HRTIM_TIM_GetCompareMode
LL_HRTIM_TIM_GetCounter
LL_HRTIM_TIM_GetCounterMode
LL_HRTIM_TIM_GetCountingMode
LL_HRTIM_TIM_GetCurrentPushPullStatus
LL_HRTIM_TIM_GetDACTrig
LL_HRTIM_TIM_GetDLYPRTMode
LL_HRTIM_TIM_GetDualDacResetTrigger
LL_HRTIM_TIM_GetDualDacStepTrigger
LL_HRTIM_TIM_GetEventCounterResetMode
LL_HRTIM_TIM_GetEventCounterSource
LL_HRTIM_TIM_GetEventCounterThreshold
LL_HRTIM_TIM_GetEventFilter
LL_HRTIM_TIM_GetEventLatchStatus
LL_HRTIM_TIM_GetFaultEventRollOverMode
LL_HRTIM_TIM_GetIdlePushPullStatus
LL_HRTIM_TIM_GetInterleavedMode
LL_HRTIM_TIM_GetOutputRollOverMode
LL_HRTIM_TIM_GetPeriod
LL_HRTIM_TIM_GetPrescaler
LL_HRTIM_TIM_GetRepetition
LL_HRTIM_TIM_GetResetTrig
LL_HRTIM_TIM_GetRollOverMode
LL_HRTIM_TIM_GetTriggeredHalfMode
LL_HRTIM_TIM_GetUpdateGating
LL_HRTIM_TIM_GetUpdateTrig
LL_HRTIM_TIM_IsCounterEnabled
LL_HRTIM_TIM_IsEnabledBIAR
LL_HRTIM_TIM_IsEnabledDeadTime
LL_HRTIM_TIM_IsEnabledDLYPRT
LL_HRTIM_TIM_IsEnabledDualDacTrigger
LL_HRTIM_TIM_IsEnabledEventCounter
LL_HRTIM_TIM_IsEnabledFault
LL_HRTIM_TIM_IsEnabledHalfMode
LL_HRTIM_TIM_IsEnabledPreload
LL_HRTIM_TIM_IsEnabledPushPullMode
LL_HRTIM_TIM_IsEnabledResetOnSync
LL_HRTIM_TIM_IsEnabledResyncUpdate
LL_HRTIM_TIM_IsEnabledStartOnSync
LL_HRTIM_TIM_LockFault
LL_HRTIM_TIM_ResetEventCounter
LL_HRTIM_TIM_SetADCRollOverMode
LL_HRTIM_TIM_SetBMRollOverMode
LL_HRTIM_TIM_SetBurstModeOption
LL_HRTIM_TIM_SetCaptureTrig
LL_HRTIM_TIM_SetComp1Mode
LL_HRTIM_TIM_SetComp3Mode
LL_HRTIM_TIM_SetCompare1
LL_HRTIM_TIM_SetCompare2
LL_HRTIM_TIM_SetCompare3
LL_HRTIM_TIM_SetCompare4
LL_HRTIM_TIM_SetCompareMode
LL_HRTIM_TIM_SetCounter
LL_HRTIM_TIM_SetCounterMode
LL_HRTIM_TIM_SetCountingMode
LL_HRTIM_TIM_SetDACTrig
LL_HRTIM_TIM_SetDLYPRTMode
LL_HRTIM_TIM_SetDualDacResetTrigger
LL_HRTIM_TIM_SetDualDacStepTrigger
LL_HRTIM_TIM_SetEventCounterResetMode
LL_HRTIM_TIM_SetEventCounterSource
LL_HRTIM_TIM_SetEventCounterThreshold
LL_HRTIM_TIM_SetEventFilter
LL_HRTIM_TIM_SetEventLatchStatus
LL_HRTIM_TIM_SetFaultEventRollOverMode
LL_HRTIM_TIM_SetInterleavedMode
LL_HRTIM_TIM_SetOutputRollOverMode
LL_HRTIM_TIM_SetPeriod
LL_HRTIM_TIM_SetPrescaler
LL_HRTIM_TIM_SetRepetition
LL_HRTIM_TIM_SetResetTrig
LL_HRTIM_TIM_SetRollOverMode
LL_HRTIM_TIM_SetTriggeredHalfMode
LL_HRTIM_TIM_SetUpdateGating
LL_HRTIM_TIM_SetUpdateTrig
REG_MASK_TAB_ADCER
REG_MASK_TAB_ADCUR
REG_MASK_TAB_CPT
REG_MASK_TAB_INTLVD
REG_MASK_TAB_UPDATEGATING
REG_MASK_TAB_UPDATETRIG
REG_OFFSET_TAB_ADCER
REG_OFFSET_TAB_ADCPSx
REG_OFFSET_TAB_ADCUR
REG_OFFSET_TAB_EECR
REG_OFFSET_TAB_FLTINR
REG_OFFSET_TAB_OUTxR
REG_OFFSET_TAB_SETxR
REG_OFFSET_TAB_TIMER
REG_SHIFT_TAB_ADCER
REG_SHIFT_TAB_ADCUR
REG_SHIFT_TAB_CPT
REG_SHIFT_TAB_EExSRC
REG_SHIFT_TAB_FLTx
REG_SHIFT_TAB_FLTxCNT
REG_SHIFT_TAB_FLTxE
REG_SHIFT_TAB_FLTxF
REG_SHIFT_TAB_INTLVD
REG_SHIFT_TAB_OUTxR
REG_SHIFT_TAB_OxSTAT
REG_SHIFT_TAB_UPDATEGATING
REG_SHIFT_TAB_UPDATETRIG
stm32g4xx_ll_i2c.c
IS_LL_I2C_ANALOG_FILTER
IS_LL_I2C_DIGITAL_FILTER
IS_LL_I2C_OWN_ADDRESS1
IS_LL_I2C_OWN_ADDRSIZE
IS_LL_I2C_PERIPHERAL_MODE
IS_LL_I2C_TYPE_ACKNOWLEDGE
LL_I2C_DeInit
LL_I2C_Init
LL_I2C_StructInit
stm32g4xx_ll_i2c.h
LL_I2C_ACK
LL_I2C_ADDRESSING_MODE_10BIT
LL_I2C_ADDRESSING_MODE_7BIT
LL_I2C_ADDRSLAVE_10BIT
LL_I2C_ADDRSLAVE_7BIT
LL_I2C_ANALOGFILTER_DISABLE
LL_I2C_ANALOGFILTER_ENABLE
LL_I2C_CR1_ADDRIE
LL_I2C_CR1_ERRIE
LL_I2C_CR1_NACKIE
LL_I2C_CR1_RXIE
LL_I2C_CR1_STOPIE
LL_I2C_CR1_TCIE
LL_I2C_CR1_TXIE
LL_I2C_DIRECTION_READ
LL_I2C_DIRECTION_WRITE
LL_I2C_DMA_REG_DATA_RECEIVE
LL_I2C_DMA_REG_DATA_TRANSMIT
LL_I2C_GENERATE_NOSTARTSTOP
LL_I2C_GENERATE_RESTART_10BIT_READ
LL_I2C_GENERATE_RESTART_10BIT_WRITE
LL_I2C_GENERATE_RESTART_7BIT_READ
LL_I2C_GENERATE_RESTART_7BIT_WRITE
LL_I2C_GENERATE_START_READ
LL_I2C_GENERATE_START_WRITE
LL_I2C_GENERATE_STOP
LL_I2C_ICR_ADDRCF
LL_I2C_ICR_ALERTCF
LL_I2C_ICR_ARLOCF
LL_I2C_ICR_BERRCF
LL_I2C_ICR_NACKCF
LL_I2C_ICR_OVRCF
LL_I2C_ICR_PECCF
LL_I2C_ICR_STOPCF
LL_I2C_ICR_TIMOUTCF
LL_I2C_ISR_ADDR
LL_I2C_ISR_ALERT
LL_I2C_ISR_ARLO
LL_I2C_ISR_BERR
LL_I2C_ISR_BUSY
LL_I2C_ISR_NACKF
LL_I2C_ISR_OVR
LL_I2C_ISR_PECERR
LL_I2C_ISR_RXNE
LL_I2C_ISR_STOPF
LL_I2C_ISR_TC
LL_I2C_ISR_TCR
LL_I2C_ISR_TIMEOUT
LL_I2C_ISR_TXE
LL_I2C_ISR_TXIS
LL_I2C_MODE_AUTOEND
LL_I2C_MODE_I2C
LL_I2C_MODE_RELOAD
LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
LL_I2C_MODE_SMBUS_DEVICE
LL_I2C_MODE_SMBUS_DEVICE_ARP
LL_I2C_MODE_SMBUS_HOST
LL_I2C_MODE_SMBUS_RELOAD
LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
LL_I2C_MODE_SOFTEND
LL_I2C_NACK
LL_I2C_OWNADDRESS1_10BIT
LL_I2C_OWNADDRESS1_7BIT
LL_I2C_OWNADDRESS2_MASK01
LL_I2C_OWNADDRESS2_MASK02
LL_I2C_OWNADDRESS2_MASK03
LL_I2C_OWNADDRESS2_MASK04
LL_I2C_OWNADDRESS2_MASK05
LL_I2C_OWNADDRESS2_MASK06
LL_I2C_OWNADDRESS2_MASK07
LL_I2C_OWNADDRESS2_NOMASK
LL_I2C_ReadReg
LL_I2C_REQUEST_READ
LL_I2C_REQUEST_WRITE
LL_I2C_SMBUS_ALL_TIMEOUT
LL_I2C_SMBUS_TIMEOUTA
LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
LL_I2C_SMBUS_TIMEOUTB
LL_I2C_WriteReg
LL_I2C_AcknowledgeNextData
LL_I2C_ClearFlag_ADDR
LL_I2C_ClearFlag_ARLO
LL_I2C_ClearFlag_BERR
LL_I2C_ClearFlag_NACK
LL_I2C_ClearFlag_OVR
LL_I2C_ClearFlag_STOP
LL_I2C_ClearFlag_TXE
LL_I2C_ClearSMBusFlag_ALERT
LL_I2C_ClearSMBusFlag_PECERR
LL_I2C_ClearSMBusFlag_TIMEOUT
LL_I2C_ConfigFilters
LL_I2C_ConfigSMBusTimeout
LL_I2C_DeInit
LL_I2C_Disable
LL_I2C_DisableAnalogFilter
LL_I2C_DisableAuto10BitRead
LL_I2C_DisableAutoEndMode
LL_I2C_DisableClockStretching
LL_I2C_DisableDMAReq_RX
LL_I2C_DisableDMAReq_TX
LL_I2C_DisableGeneralCall
LL_I2C_DisableIT_ADDR
LL_I2C_DisableIT_ERR
LL_I2C_DisableIT_NACK
LL_I2C_DisableIT_RX
LL_I2C_DisableIT_STOP
LL_I2C_DisableIT_TC
LL_I2C_DisableIT_TX
LL_I2C_DisableOwnAddress1
LL_I2C_DisableOwnAddress2
LL_I2C_DisableReloadMode
LL_I2C_DisableSlaveByteControl
LL_I2C_DisableSMBusAlert
LL_I2C_DisableSMBusPEC
LL_I2C_DisableSMBusTimeout
LL_I2C_DisableWakeUpFromStop
LL_I2C_DMA_GetRegAddr
LL_I2C_Enable
LL_I2C_EnableAnalogFilter
LL_I2C_EnableAuto10BitRead
LL_I2C_EnableAutoEndMode
LL_I2C_EnableClockStretching
LL_I2C_EnableDMAReq_RX
LL_I2C_EnableDMAReq_TX
LL_I2C_EnableGeneralCall
LL_I2C_EnableIT_ADDR
LL_I2C_EnableIT_ERR
LL_I2C_EnableIT_NACK
LL_I2C_EnableIT_RX
LL_I2C_EnableIT_STOP
LL_I2C_EnableIT_TC
LL_I2C_EnableIT_TX
LL_I2C_EnableOwnAddress1
LL_I2C_EnableOwnAddress2
LL_I2C_EnableReloadMode
LL_I2C_EnableSlaveByteControl
LL_I2C_EnableSMBusAlert
LL_I2C_EnableSMBusPEC
LL_I2C_EnableSMBusPECCompare
LL_I2C_EnableSMBusTimeout
LL_I2C_EnableWakeUpFromStop
LL_I2C_GenerateStartCondition
LL_I2C_GenerateStopCondition
LL_I2C_GetAddressMatchCode
LL_I2C_GetClockHighPeriod
LL_I2C_GetClockLowPeriod
LL_I2C_GetDataHoldTime
LL_I2C_GetDataSetupTime
LL_I2C_GetDigitalFilter
LL_I2C_GetMasterAddressingMode
LL_I2C_GetMode
LL_I2C_GetSlaveAddr
LL_I2C_GetSMBusPEC
LL_I2C_GetSMBusTimeoutA
LL_I2C_GetSMBusTimeoutAMode
LL_I2C_GetSMBusTimeoutB
LL_I2C_GetTimingPrescaler
LL_I2C_GetTransferDirection
LL_I2C_GetTransferRequest
LL_I2C_GetTransferSize
LL_I2C_HandleTransfer
LL_I2C_Init
LL_I2C_IsActiveFlag_ADDR
LL_I2C_IsActiveFlag_ARLO
LL_I2C_IsActiveFlag_BERR
LL_I2C_IsActiveFlag_BUSY
LL_I2C_IsActiveFlag_NACK
LL_I2C_IsActiveFlag_OVR
LL_I2C_IsActiveFlag_RXNE
LL_I2C_IsActiveFlag_STOP
LL_I2C_IsActiveFlag_TC
LL_I2C_IsActiveFlag_TCR
LL_I2C_IsActiveFlag_TXE
LL_I2C_IsActiveFlag_TXIS
LL_I2C_IsActiveSMBusFlag_ALERT
LL_I2C_IsActiveSMBusFlag_PECERR
LL_I2C_IsActiveSMBusFlag_TIMEOUT
LL_I2C_IsEnabled
LL_I2C_IsEnabledAnalogFilter
LL_I2C_IsEnabledAuto10BitRead
LL_I2C_IsEnabledAutoEndMode
LL_I2C_IsEnabledClockStretching
LL_I2C_IsEnabledDMAReq_RX
LL_I2C_IsEnabledDMAReq_TX
LL_I2C_IsEnabledGeneralCall
LL_I2C_IsEnabledIT_ADDR
LL_I2C_IsEnabledIT_ERR
LL_I2C_IsEnabledIT_NACK
LL_I2C_IsEnabledIT_RX
LL_I2C_IsEnabledIT_STOP
LL_I2C_IsEnabledIT_TC
LL_I2C_IsEnabledIT_TX
LL_I2C_IsEnabledOwnAddress1
LL_I2C_IsEnabledOwnAddress2
LL_I2C_IsEnabledReloadMode
LL_I2C_IsEnabledSlaveByteControl
LL_I2C_IsEnabledSMBusAlert
LL_I2C_IsEnabledSMBusPEC
LL_I2C_IsEnabledSMBusPECCompare
LL_I2C_IsEnabledSMBusTimeout
LL_I2C_IsEnabledWakeUpFromStop
LL_I2C_ReceiveData8
LL_I2C_SetDigitalFilter
LL_I2C_SetMasterAddressingMode
LL_I2C_SetMode
LL_I2C_SetOwnAddress1
LL_I2C_SetOwnAddress2
LL_I2C_SetSlaveAddr
LL_I2C_SetSMBusTimeoutA
LL_I2C_SetSMBusTimeoutAMode
LL_I2C_SetSMBusTimeoutB
LL_I2C_SetTiming
LL_I2C_SetTransferRequest
LL_I2C_SetTransferSize
LL_I2C_StructInit
LL_I2C_TransmitData8
stm32g4xx_ll_iwdg.h
LL_IWDG_KEY_RELOAD
LL_IWDG_KEY_WR_ACCESS_DISABLE
LL_IWDG_KEY_WR_ACCESS_ENABLE
LL_IWDG_PRESCALER_128
LL_IWDG_PRESCALER_16
LL_IWDG_PRESCALER_256
LL_IWDG_PRESCALER_32
LL_IWDG_PRESCALER_4
LL_IWDG_PRESCALER_64
LL_IWDG_PRESCALER_8
LL_IWDG_ReadReg
LL_IWDG_SR_PVU
LL_IWDG_SR_RVU
LL_IWDG_SR_WVU
LL_IWDG_WriteReg
LL_IWDG_DisableWriteAccess
LL_IWDG_Enable
LL_IWDG_EnableWriteAccess
LL_IWDG_GetPrescaler
LL_IWDG_GetReloadCounter
LL_IWDG_GetWindow
LL_IWDG_IsActiveFlag_PVU
LL_IWDG_IsActiveFlag_RVU
LL_IWDG_IsActiveFlag_WVU
LL_IWDG_IsReady
LL_IWDG_ReloadCounter
LL_IWDG_SetPrescaler
LL_IWDG_SetReloadCounter
LL_IWDG_SetWindow
stm32g4xx_ll_lptim.c
IS_LL_LPTIM_CLOCK_PRESCALER
IS_LL_LPTIM_CLOCK_SOURCE
IS_LL_LPTIM_OUTPUT_POLARITY
IS_LL_LPTIM_WAVEFORM
LL_LPTIM_DeInit
LL_LPTIM_Disable
LL_LPTIM_Init
LL_LPTIM_StructInit
stm32g4xx_ll_lptim.h
LL_LPTIM_CLK_FILTER_4
LL_LPTIM_CLK_FILTER_8
LL_LPTIM_CLK_FILTER_NONE
LL_LPTIM_CLK_POLARITY_FALLING
LL_LPTIM_CLK_POLARITY_RISING
LL_LPTIM_CLK_POLARITY_RISING_FALLING
LL_LPTIM_CLK_SOURCE_EXTERNAL
LL_LPTIM_CLK_SOURCE_INTERNAL
LL_LPTIM_COUNTER_MODE_EXTERNAL
LL_LPTIM_COUNTER_MODE_INTERNAL
LL_LPTIM_ENCODER_MODE_FALLING
LL_LPTIM_ENCODER_MODE_RISING
LL_LPTIM_ENCODER_MODE_RISING_FALLING
LL_LPTIM_IER_ARRMIE
LL_LPTIM_IER_ARROKIE
LL_LPTIM_IER_CMPMIE
LL_LPTIM_IER_CMPOKIE
LL_LPTIM_IER_DOWNIE
LL_LPTIM_IER_EXTTRIGIE
LL_LPTIM_IER_UPIE
LL_LPTIM_INPUT1_SRC_COMP1
LL_LPTIM_INPUT1_SRC_COMP3
LL_LPTIM_INPUT1_SRC_COMP5
LL_LPTIM_INPUT1_SRC_COMP7
LL_LPTIM_INPUT1_SRC_GPIO
LL_LPTIM_INPUT2_SRC_COMP2
LL_LPTIM_INPUT2_SRC_COMP4
LL_LPTIM_INPUT2_SRC_COMP6
LL_LPTIM_INPUT2_SRC_GPIO
LL_LPTIM_ISR_ARRM
LL_LPTIM_ISR_ARROK
LL_LPTIM_ISR_CMPM
LL_LPTIM_ISR_CMPOK
LL_LPTIM_ISR_DOWN
LL_LPTIM_ISR_EXTTRIG
LL_LPTIM_ISR_UP
LL_LPTIM_OPERATING_MODE_CONTINUOUS
LL_LPTIM_OPERATING_MODE_ONESHOT
LL_LPTIM_OUTPUT_POLARITY_INVERSE
LL_LPTIM_OUTPUT_POLARITY_REGULAR
LL_LPTIM_OUTPUT_WAVEFORM_PWM
LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
LL_LPTIM_PRESCALER_DIV1
LL_LPTIM_PRESCALER_DIV128
LL_LPTIM_PRESCALER_DIV16
LL_LPTIM_PRESCALER_DIV2
LL_LPTIM_PRESCALER_DIV32
LL_LPTIM_PRESCALER_DIV4
LL_LPTIM_PRESCALER_DIV64
LL_LPTIM_PRESCALER_DIV8
LL_LPTIM_ReadReg
LL_LPTIM_TRIG_FILTER_2
LL_LPTIM_TRIG_FILTER_4
LL_LPTIM_TRIG_FILTER_8
LL_LPTIM_TRIG_FILTER_NONE
LL_LPTIM_TRIG_POLARITY_FALLING
LL_LPTIM_TRIG_POLARITY_RISING
LL_LPTIM_TRIG_POLARITY_RISING_FALLING
LL_LPTIM_TRIG_SOURCE_COMP1
LL_LPTIM_TRIG_SOURCE_COMP2
LL_LPTIM_TRIG_SOURCE_COMP3
LL_LPTIM_TRIG_SOURCE_COMP4
LL_LPTIM_TRIG_SOURCE_COMP5
LL_LPTIM_TRIG_SOURCE_COMP6
LL_LPTIM_TRIG_SOURCE_COMP7
LL_LPTIM_TRIG_SOURCE_GPIO
LL_LPTIM_TRIG_SOURCE_RTCALARMA
LL_LPTIM_TRIG_SOURCE_RTCALARMB
LL_LPTIM_TRIG_SOURCE_RTCTAMP1
LL_LPTIM_TRIG_SOURCE_RTCTAMP2
LL_LPTIM_TRIG_SOURCE_RTCTAMP3
LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
LL_LPTIM_UPDATE_MODE_IMMEDIATE
LL_LPTIM_WriteReg
LL_LPTIM_ClearFlag_ARRM
LL_LPTIM_ClearFlag_ARROK
LL_LPTIM_ClearFlag_CMPM
LL_LPTIM_ClearFlag_CMPOK
LL_LPTIM_ClearFlag_DOWN
LL_LPTIM_ClearFlag_EXTTRIG
LL_LPTIM_ClearFlag_UP
LL_LPTIM_ConfigClock
LL_LPTIM_ConfigOutput
LL_LPTIM_ConfigTrigger
LL_LPTIM_DeInit
LL_LPTIM_Disable
LL_LPTIM_DisableEncoderMode
LL_LPTIM_DisableIT_ARRM
LL_LPTIM_DisableIT_ARROK
LL_LPTIM_DisableIT_CMPM
LL_LPTIM_DisableIT_CMPOK
LL_LPTIM_DisableIT_DOWN
LL_LPTIM_DisableIT_EXTTRIG
LL_LPTIM_DisableIT_UP
LL_LPTIM_DisableResetAfterRead
LL_LPTIM_DisableTimeout
LL_LPTIM_Enable
LL_LPTIM_EnableEncoderMode
LL_LPTIM_EnableIT_ARRM
LL_LPTIM_EnableIT_ARROK
LL_LPTIM_EnableIT_CMPM
LL_LPTIM_EnableIT_CMPOK
LL_LPTIM_EnableIT_DOWN
LL_LPTIM_EnableIT_EXTTRIG
LL_LPTIM_EnableIT_UP
LL_LPTIM_EnableResetAfterRead
LL_LPTIM_EnableTimeout
LL_LPTIM_GetAutoReload
LL_LPTIM_GetClockFilter
LL_LPTIM_GetClockPolarity
LL_LPTIM_GetClockSource
LL_LPTIM_GetCompare
LL_LPTIM_GetCounter
LL_LPTIM_GetCounterMode
LL_LPTIM_GetEncoderMode
LL_LPTIM_GetPolarity
LL_LPTIM_GetPrescaler
LL_LPTIM_GetTriggerFilter
LL_LPTIM_GetTriggerPolarity
LL_LPTIM_GetTriggerSource
LL_LPTIM_GetUpdateMode
LL_LPTIM_GetWaveform
LL_LPTIM_Init
LL_LPTIM_IsActiveFlag_ARRM
LL_LPTIM_IsActiveFlag_ARROK
LL_LPTIM_IsActiveFlag_CMPM
LL_LPTIM_IsActiveFlag_CMPOK
LL_LPTIM_IsActiveFlag_DOWN
LL_LPTIM_IsActiveFlag_EXTTRIG
LL_LPTIM_IsActiveFlag_UP
LL_LPTIM_IsEnabled
LL_LPTIM_IsEnabledEncoderMode
LL_LPTIM_IsEnabledIT_ARRM
LL_LPTIM_IsEnabledIT_ARROK
LL_LPTIM_IsEnabledIT_CMPM
LL_LPTIM_IsEnabledIT_CMPOK
LL_LPTIM_IsEnabledIT_DOWN
LL_LPTIM_IsEnabledIT_EXTTRIG
LL_LPTIM_IsEnabledIT_UP
LL_LPTIM_IsEnabledResetAfterRead
LL_LPTIM_IsEnabledTimeout
LL_LPTIM_ResetCounter
LL_LPTIM_SetAutoReload
LL_LPTIM_SetClockSource
LL_LPTIM_SetCompare
LL_LPTIM_SetCounterMode
LL_LPTIM_SetEncoderMode
LL_LPTIM_SetInput1Src
LL_LPTIM_SetInput2Src
LL_LPTIM_SetPolarity
LL_LPTIM_SetPrescaler
LL_LPTIM_SetUpdateMode
LL_LPTIM_SetWaveform
LL_LPTIM_StartCounter
LL_LPTIM_StructInit
LL_LPTIM_TrigSw
stm32g4xx_ll_lpuart.c
IS_LL_LPUART_BAUDRATE
IS_LL_LPUART_BRR_MAX
IS_LL_LPUART_BRR_MIN
IS_LL_LPUART_DATAWIDTH
IS_LL_LPUART_DIRECTION
IS_LL_LPUART_HWCONTROL
IS_LL_LPUART_PARITY
IS_LL_LPUART_PRESCALER
IS_LL_LPUART_STOPBITS
LPUART_DEFAULT_BAUDRATE
LL_LPUART_DeInit
LL_LPUART_Init
LL_LPUART_StructInit
stm32g4xx_ll_lpuart.h
LL_LPUART_ADDRESS_DETECT_4B
LL_LPUART_ADDRESS_DETECT_7B
LL_LPUART_BINARY_LOGIC_NEGATIVE
LL_LPUART_BINARY_LOGIC_POSITIVE
LL_LPUART_BITORDER_LSBFIRST
LL_LPUART_BITORDER_MSBFIRST
LL_LPUART_CR1_CMIE
LL_LPUART_CR1_IDLEIE
LL_LPUART_CR1_PEIE
LL_LPUART_CR1_RXFFIE
LL_LPUART_CR1_RXNEIE_RXFNEIE
LL_LPUART_CR1_TCIE
LL_LPUART_CR1_TXEIE_TXFNFIE
LL_LPUART_CR1_TXFEIE
LL_LPUART_CR3_CTSIE
LL_LPUART_CR3_EIE
LL_LPUART_CR3_RXFTIE
LL_LPUART_CR3_TXFTIE
LL_LPUART_CR3_WUFIE
LL_LPUART_DATAWIDTH_7B
LL_LPUART_DATAWIDTH_8B
LL_LPUART_DATAWIDTH_9B
LL_LPUART_DE_POLARITY_HIGH
LL_LPUART_DE_POLARITY_LOW
LL_LPUART_DIRECTION_NONE
LL_LPUART_DIRECTION_RX
LL_LPUART_DIRECTION_TX
LL_LPUART_DIRECTION_TX_RX
LL_LPUART_DisableIT_RXNE
LL_LPUART_DisableIT_TXE
LL_LPUART_DMA_REG_DATA_RECEIVE
LL_LPUART_DMA_REG_DATA_TRANSMIT
LL_LPUART_EnableIT_RXNE
LL_LPUART_EnableIT_TXE
LL_LPUART_FIFOTHRESHOLD_1_2
LL_LPUART_FIFOTHRESHOLD_1_4
LL_LPUART_FIFOTHRESHOLD_1_8
LL_LPUART_FIFOTHRESHOLD_3_4
LL_LPUART_FIFOTHRESHOLD_7_8
LL_LPUART_FIFOTHRESHOLD_8_8
LL_LPUART_HWCONTROL_CTS
LL_LPUART_HWCONTROL_NONE
LL_LPUART_HWCONTROL_RTS
LL_LPUART_HWCONTROL_RTS_CTS
LL_LPUART_ICR_CMCF
LL_LPUART_ICR_CTSCF
LL_LPUART_ICR_FECF
LL_LPUART_ICR_IDLECF
LL_LPUART_ICR_NCF
LL_LPUART_ICR_ORECF
LL_LPUART_ICR_PECF
LL_LPUART_ICR_TCCF
LL_LPUART_ICR_WUCF
LL_LPUART_IsActiveFlag_RXNE
LL_LPUART_IsActiveFlag_TXE
LL_LPUART_IsEnabledIT_RXNE
LL_LPUART_IsEnabledIT_TXE
LL_LPUART_ISR_BUSY
LL_LPUART_ISR_CMF
LL_LPUART_ISR_CTS
LL_LPUART_ISR_CTSIF
LL_LPUART_ISR_FE
LL_LPUART_ISR_IDLE
LL_LPUART_ISR_NE
LL_LPUART_ISR_ORE
LL_LPUART_ISR_PE
LL_LPUART_ISR_REACK
LL_LPUART_ISR_RWU
LL_LPUART_ISR_RXFF
LL_LPUART_ISR_RXFT
LL_LPUART_ISR_RXNE_RXFNE
LL_LPUART_ISR_SBKF
LL_LPUART_ISR_TC
LL_LPUART_ISR_TEACK
LL_LPUART_ISR_TXE_TXFNF
LL_LPUART_ISR_TXFE
LL_LPUART_ISR_TXFT
LL_LPUART_ISR_WUF
LL_LPUART_PARITY_EVEN
LL_LPUART_PARITY_NONE
LL_LPUART_PARITY_ODD
LL_LPUART_PRESCALER_DIV1
LL_LPUART_PRESCALER_DIV10
LL_LPUART_PRESCALER_DIV12
LL_LPUART_PRESCALER_DIV128
LL_LPUART_PRESCALER_DIV16
LL_LPUART_PRESCALER_DIV2
LL_LPUART_PRESCALER_DIV256
LL_LPUART_PRESCALER_DIV32
LL_LPUART_PRESCALER_DIV4
LL_LPUART_PRESCALER_DIV6
LL_LPUART_PRESCALER_DIV64
LL_LPUART_PRESCALER_DIV8
LL_LPUART_ReadReg
LL_LPUART_RXPIN_LEVEL_INVERTED
LL_LPUART_RXPIN_LEVEL_STANDARD
LL_LPUART_STOPBITS_1
LL_LPUART_STOPBITS_2
LL_LPUART_TXPIN_LEVEL_INVERTED
LL_LPUART_TXPIN_LEVEL_STANDARD
LL_LPUART_TXRX_STANDARD
LL_LPUART_TXRX_SWAPPED
LL_LPUART_WAKEUP_ADDRESSMARK
LL_LPUART_WAKEUP_IDLELINE
LL_LPUART_WAKEUP_ON_ADDRESS
LL_LPUART_WAKEUP_ON_RXNE
LL_LPUART_WAKEUP_ON_STARTBIT
LL_LPUART_WriteReg
LPUART_BRR_MASK
LPUART_BRR_MIN_VALUE
LPUART_LPUARTDIV_FREQ_MUL
LL_LPUART_ClearFlag_CM
LL_LPUART_ClearFlag_FE
LL_LPUART_ClearFlag_IDLE
LL_LPUART_ClearFlag_nCTS
LL_LPUART_ClearFlag_NE
LL_LPUART_ClearFlag_ORE
LL_LPUART_ClearFlag_PE
LL_LPUART_ClearFlag_TC
LL_LPUART_ClearFlag_WKUP
LL_LPUART_ConfigCharacter
LL_LPUART_ConfigFIFOsThreshold
LL_LPUART_ConfigNodeAddress
LL_LPUART_DeInit
LL_LPUART_Disable
LL_LPUART_DisableCTSHWFlowCtrl
LL_LPUART_DisableDEMode
LL_LPUART_DisableDirectionRx
LL_LPUART_DisableDirectionTx
LL_LPUART_DisableDMADeactOnRxErr
LL_LPUART_DisableDMAReq_RX
LL_LPUART_DisableDMAReq_TX
LL_LPUART_DisableFIFO
LL_LPUART_DisableHalfDuplex
LL_LPUART_DisableInStopMode
LL_LPUART_DisableIT_CM
LL_LPUART_DisableIT_CTS
LL_LPUART_DisableIT_ERROR
LL_LPUART_DisableIT_IDLE
LL_LPUART_DisableIT_PE
LL_LPUART_DisableIT_RXFF
LL_LPUART_DisableIT_RXFT
LL_LPUART_DisableIT_RXNE_RXFNE
LL_LPUART_DisableIT_TC
LL_LPUART_DisableIT_TXE_TXFNF
LL_LPUART_DisableIT_TXFE
LL_LPUART_DisableIT_TXFT
LL_LPUART_DisableIT_WKUP
LL_LPUART_DisableMuteMode
LL_LPUART_DisableOverrunDetect
LL_LPUART_DisableRTSHWFlowCtrl
LL_LPUART_DMA_GetRegAddr
LL_LPUART_Enable
LL_LPUART_EnableCTSHWFlowCtrl
LL_LPUART_EnableDEMode
LL_LPUART_EnableDirectionRx
LL_LPUART_EnableDirectionTx
LL_LPUART_EnableDMADeactOnRxErr
LL_LPUART_EnableDMAReq_RX
LL_LPUART_EnableDMAReq_TX
LL_LPUART_EnableFIFO
LL_LPUART_EnableHalfDuplex
LL_LPUART_EnableInStopMode
LL_LPUART_EnableIT_CM
LL_LPUART_EnableIT_CTS
LL_LPUART_EnableIT_ERROR
LL_LPUART_EnableIT_IDLE
LL_LPUART_EnableIT_PE
LL_LPUART_EnableIT_RXFF
LL_LPUART_EnableIT_RXFT
LL_LPUART_EnableIT_RXNE_RXFNE
LL_LPUART_EnableIT_TC
LL_LPUART_EnableIT_TXE_TXFNF
LL_LPUART_EnableIT_TXFE
LL_LPUART_EnableIT_TXFT
LL_LPUART_EnableIT_WKUP
LL_LPUART_EnableMuteMode
LL_LPUART_EnableOverrunDetect
LL_LPUART_EnableRTSHWFlowCtrl
LL_LPUART_GetBaudRate
LL_LPUART_GetBinaryDataLogic
LL_LPUART_GetDataWidth
LL_LPUART_GetDEAssertionTime
LL_LPUART_GetDEDeassertionTime
LL_LPUART_GetDESignalPolarity
LL_LPUART_GetHWFlowCtrl
LL_LPUART_GetNodeAddress
LL_LPUART_GetNodeAddressLen
LL_LPUART_GetParity
LL_LPUART_GetPrescaler
LL_LPUART_GetRXFIFOThreshold
LL_LPUART_GetRXPinLevel
LL_LPUART_GetStopBitsLength
LL_LPUART_GetTransferBitOrder
LL_LPUART_GetTransferDirection
LL_LPUART_GetTXFIFOThreshold
LL_LPUART_GetTXPinLevel
LL_LPUART_GetTXRXSwap
LL_LPUART_GetWakeUpMethod
LL_LPUART_GetWKUPType
LL_LPUART_Init
LL_LPUART_IsActiveFlag_BUSY
LL_LPUART_IsActiveFlag_CM
LL_LPUART_IsActiveFlag_CTS
LL_LPUART_IsActiveFlag_FE
LL_LPUART_IsActiveFlag_IDLE
LL_LPUART_IsActiveFlag_nCTS
LL_LPUART_IsActiveFlag_NE
LL_LPUART_IsActiveFlag_ORE
LL_LPUART_IsActiveFlag_PE
LL_LPUART_IsActiveFlag_REACK
LL_LPUART_IsActiveFlag_RWU
LL_LPUART_IsActiveFlag_RXFF
LL_LPUART_IsActiveFlag_RXFT
LL_LPUART_IsActiveFlag_RXNE_RXFNE
LL_LPUART_IsActiveFlag_SBK
LL_LPUART_IsActiveFlag_TC
LL_LPUART_IsActiveFlag_TEACK
LL_LPUART_IsActiveFlag_TXE_TXFNF
LL_LPUART_IsActiveFlag_TXFE
LL_LPUART_IsActiveFlag_TXFT
LL_LPUART_IsActiveFlag_WKUP
LL_LPUART_IsEnabled
LL_LPUART_IsEnabledDEMode
LL_LPUART_IsEnabledDMADeactOnRxErr
LL_LPUART_IsEnabledDMAReq_RX
LL_LPUART_IsEnabledDMAReq_TX
LL_LPUART_IsEnabledFIFO
LL_LPUART_IsEnabledHalfDuplex
LL_LPUART_IsEnabledInStopMode
LL_LPUART_IsEnabledIT_CM
LL_LPUART_IsEnabledIT_CTS
LL_LPUART_IsEnabledIT_ERROR
LL_LPUART_IsEnabledIT_IDLE
LL_LPUART_IsEnabledIT_PE
LL_LPUART_IsEnabledIT_RXFF
LL_LPUART_IsEnabledIT_RXFT
LL_LPUART_IsEnabledIT_RXNE_RXFNE
LL_LPUART_IsEnabledIT_TC
LL_LPUART_IsEnabledIT_TXE_TXFNF
LL_LPUART_IsEnabledIT_TXFE
LL_LPUART_IsEnabledIT_TXFT
LL_LPUART_IsEnabledIT_WKUP
LL_LPUART_IsEnabledMuteMode
LL_LPUART_IsEnabledOverrunDetect
LL_LPUART_ReceiveData8
LL_LPUART_ReceiveData9
LL_LPUART_RequestBreakSending
LL_LPUART_RequestEnterMuteMode
LL_LPUART_RequestRxDataFlush
LL_LPUART_RequestTxDataFlush
LL_LPUART_SetBaudRate
LL_LPUART_SetBinaryDataLogic
LL_LPUART_SetDataWidth
LL_LPUART_SetDEAssertionTime
LL_LPUART_SetDEDeassertionTime
LL_LPUART_SetDESignalPolarity
LL_LPUART_SetHWFlowCtrl
LL_LPUART_SetParity
LL_LPUART_SetPrescaler
LL_LPUART_SetRXFIFOThreshold
LL_LPUART_SetRXPinLevel
LL_LPUART_SetStopBitsLength
LL_LPUART_SetTransferBitOrder
LL_LPUART_SetTransferDirection
LL_LPUART_SetTXFIFOThreshold
LL_LPUART_SetTXPinLevel
LL_LPUART_SetTXRXSwap
LL_LPUART_SetWakeUpMethod
LL_LPUART_SetWKUPType
LL_LPUART_StructInit
LL_LPUART_TransmitData8
LL_LPUART_TransmitData9
LPUART_PRESCALER_TAB
stm32g4xx_ll_opamp.c
IS_LL_OPAMP_FUNCTIONAL_MODE
IS_LL_OPAMP_INPUT_INVERTING
IS_LL_OPAMP_INPUT_NONINVERTING
IS_LL_OPAMP_POWER_MODE
LL_OPAMP_DeInit
LL_OPAMP_Init
LL_OPAMP_StructInit
stm32g4xx_ll_opamp.h
LL_OPAMP_DELAY_STARTUP_US
LL_OPAMP_INPUT_INVERT_CONNECT_NO
LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
LL_OPAMP_INPUT_INVERT_IO0
LL_OPAMP_INPUT_INVERT_IO0_SEC
LL_OPAMP_INPUT_INVERT_IO1
LL_OPAMP_INPUT_INVERT_IO1_SEC
LL_OPAMP_INPUT_INVERT_PGA_SEC
LL_OPAMP_INPUT_MUX_DISABLE
LL_OPAMP_INPUT_MUX_TIM1_CH6
LL_OPAMP_INPUT_MUX_TIM20_CH6
LL_OPAMP_INPUT_MUX_TIM8_CH6
LL_OPAMP_INPUT_NONINVERT_DAC
LL_OPAMP_INPUT_NONINVERT_DAC_SEC
LL_OPAMP_INPUT_NONINVERT_IO0
LL_OPAMP_INPUT_NONINVERT_IO0_SEC
LL_OPAMP_INPUT_NONINVERT_IO1
LL_OPAMP_INPUT_NONINVERT_IO1_SEC
LL_OPAMP_INPUT_NONINVERT_IO2
LL_OPAMP_INPUT_NONINVERT_IO2_SEC
LL_OPAMP_INPUT_NONINVERT_IO3
LL_OPAMP_INPUT_NONINVERT_IO3_SEC
LL_OPAMP_INTERNAL_OUPUT_DISABLED
LL_OPAMP_INTERNAL_OUPUT_ENABLED
LL_OPAMP_INTERNAL_OUTPUT_DISABLED
LL_OPAMP_INTERNAL_OUTPUT_ENABLED
LL_OPAMP_MODE_CALIBRATION
LL_OPAMP_MODE_FOLLOWER
LL_OPAMP_MODE_FUNCTIONAL
LL_OPAMP_MODE_PGA
LL_OPAMP_MODE_PGA_IO0
LL_OPAMP_MODE_PGA_IO0_BIAS
LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
LL_OPAMP_MODE_STANDALONE
LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
LL_OPAMP_POWERMODE_HIGHSPEED
LL_OPAMP_POWERMODE_NORMAL
LL_OPAMP_POWERMODE_NORMALSPEED
LL_OPAMP_ReadReg
LL_OPAMP_TRIMMING_FACTORY
LL_OPAMP_TRIMMING_NMOS
LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA
LL_OPAMP_TRIMMING_PMOS
LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA
LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
LL_OPAMP_TRIMMING_USER
LL_OPAMP_WriteReg
OPAMP_TRIMMING_SELECT_MASK
OPAMP_TRIMMING_VALUE_MASK
LL_OPAMP_DeInit
LL_OPAMP_Disable
LL_OPAMP_Enable
LL_OPAMP_GetCalibrationSelection
LL_OPAMP_GetFunctionalMode
LL_OPAMP_GetInputInverting
LL_OPAMP_GetInputInvertingSecondary
LL_OPAMP_GetInputNonInverting
LL_OPAMP_GetInputNonInvertingSecondary
LL_OPAMP_GetInputsMuxMode
LL_OPAMP_GetInternalOutput
LL_OPAMP_GetMode
LL_OPAMP_GetPGAGain
LL_OPAMP_GetPowerMode
LL_OPAMP_GetTrimmingMode
LL_OPAMP_GetTrimmingValue
LL_OPAMP_Init
LL_OPAMP_IsCalibrationOutputSet
LL_OPAMP_IsEnabled
LL_OPAMP_IsLocked
LL_OPAMP_IsTimerMuxLocked
LL_OPAMP_Lock
LL_OPAMP_LockTimerMux
LL_OPAMP_SetCalibrationSelection
LL_OPAMP_SetFunctionalMode
LL_OPAMP_SetInputInverting
LL_OPAMP_SetInputInvertingSecondary
LL_OPAMP_SetInputNonInverting
LL_OPAMP_SetInputNonInvertingSecondary
LL_OPAMP_SetInputsMuxMode
LL_OPAMP_SetInternalOutput
LL_OPAMP_SetMode
LL_OPAMP_SetPGAGain
LL_OPAMP_SetPowerMode
LL_OPAMP_SetTrimmingMode
LL_OPAMP_SetTrimmingValue
LL_OPAMP_StructInit
stm32g4xx_ll_pwr.c
stm32g4xx_ll_pwr.h
LL_PWR_BATT_CHARGRESISTOR_1_5K
LL_PWR_DisableDeadBatteryPD
LL_PWR_DisableStandByModePD
LL_PWR_DisableUSBDeadBattery
LL_PWR_DisableUSBStandByModePD
LL_PWR_EnableDeadBatteryPD
LL_PWR_EnableStandByModePD
LL_PWR_EnableUSBDeadBattery
LL_PWR_EnableUSBStandByModePD
LL_PWR_GPIO_A
LL_PWR_GPIO_B
LL_PWR_GPIO_BIT_0
LL_PWR_GPIO_BIT_1
LL_PWR_GPIO_BIT_10
LL_PWR_GPIO_BIT_11
LL_PWR_GPIO_BIT_12
LL_PWR_GPIO_BIT_13
LL_PWR_GPIO_BIT_14
LL_PWR_GPIO_BIT_15
LL_PWR_GPIO_BIT_2
LL_PWR_GPIO_BIT_3
LL_PWR_GPIO_BIT_4
LL_PWR_GPIO_BIT_5
LL_PWR_GPIO_BIT_6
LL_PWR_GPIO_BIT_7
LL_PWR_GPIO_BIT_8
LL_PWR_GPIO_BIT_9
LL_PWR_GPIO_C
LL_PWR_GPIO_D
LL_PWR_GPIO_E
LL_PWR_GPIO_F
LL_PWR_GPIO_G
LL_PWR_IsActiveFlag_VOSF
LL_PWR_IsEnabledUSBDeadBattery
LL_PWR_IsEnabledUSBStandByModePD
LL_PWR_MODE_SHUTDOWN
LL_PWR_MODE_STANDBY
LL_PWR_MODE_STOP0
LL_PWR_MODE_STOP1
LL_PWR_PVDLEVEL_0
LL_PWR_PVDLEVEL_1
LL_PWR_PVDLEVEL_2
LL_PWR_PVDLEVEL_3
LL_PWR_PVDLEVEL_4
LL_PWR_PVDLEVEL_5
LL_PWR_PVDLEVEL_6
LL_PWR_PVDLEVEL_7
LL_PWR_PVM_VDDA_ADC
LL_PWR_PVM_VDDA_COMP
LL_PWR_PVM_VDDA_FASTDAC
LL_PWR_PVM_VDDA_OPAMP_DAC
LL_PWR_ReadReg
LL_PWR_REGU_VOLTAGE_SCALE1
LL_PWR_REGU_VOLTAGE_SCALE2
LL_PWR_SCR_CSBF
LL_PWR_SCR_CWUF
LL_PWR_SCR_CWUF1
LL_PWR_SCR_CWUF2
LL_PWR_SCR_CWUF3
LL_PWR_SCR_CWUF4
LL_PWR_SCR_CWUF5
LL_PWR_SR1_SBF
LL_PWR_SR1_WUF1
LL_PWR_SR1_WUF2
LL_PWR_SR1_WUF3
LL_PWR_SR1_WUF4
LL_PWR_SR1_WUF5
LL_PWR_SR1_WUFI
LL_PWR_SR2_PVDO
LL_PWR_SR2_PVMO1
LL_PWR_SR2_PVMO2
LL_PWR_SR2_PVMO3
LL_PWR_SR2_PVMO4
LL_PWR_SR2_REGLPF
LL_PWR_SR2_REGLPS
LL_PWR_SR2_VOSF
LL_PWR_WAKEUP_PIN1
LL_PWR_WAKEUP_PIN2
LL_PWR_WAKEUP_PIN3
LL_PWR_WAKEUP_PIN4
LL_PWR_WAKEUP_PIN5
LL_PWR_WriteReg
LL_PWR_ClearFlag_SB
LL_PWR_ClearFlag_WU
LL_PWR_ClearFlag_WU1
LL_PWR_ClearFlag_WU2
LL_PWR_ClearFlag_WU3
LL_PWR_ClearFlag_WU4
LL_PWR_ClearFlag_WU5
LL_PWR_DeInit
LL_PWR_DisableBatteryCharging
LL_PWR_DisableBkUpAccess
LL_PWR_DisableGPIOPullDown
LL_PWR_DisableGPIOPullUp
LL_PWR_DisableInternWU
LL_PWR_DisableLowPowerRunMode
LL_PWR_DisablePUPDCfg
LL_PWR_DisablePVD
LL_PWR_DisablePVM
LL_PWR_DisableRange1BoostMode
LL_PWR_DisableSRAM2Retention
LL_PWR_DisableUCPDDeadBattery
LL_PWR_DisableUCPDStandbyMode
LL_PWR_DisableWakeUpPin
LL_PWR_EnableBatteryCharging
LL_PWR_EnableBkUpAccess
LL_PWR_EnableGPIOPullDown
LL_PWR_EnableGPIOPullUp
LL_PWR_EnableInternWU
LL_PWR_EnableLowPowerRunMode
LL_PWR_EnablePUPDCfg
LL_PWR_EnablePVD
LL_PWR_EnablePVM
LL_PWR_EnableRange1BoostMode
LL_PWR_EnableSRAM2Retention
LL_PWR_EnableUCPDDeadBattery
LL_PWR_EnableUCPDStandbyMode
LL_PWR_EnableWakeUpPin
LL_PWR_EnterLowPowerRunMode
LL_PWR_ExitLowPowerRunMode
LL_PWR_GetBattChargResistor
LL_PWR_GetPowerMode
LL_PWR_GetPVDLevel
LL_PWR_GetRegulVoltageScaling
LL_PWR_IsActiveFlag_InternWU
LL_PWR_IsActiveFlag_PVDO
LL_PWR_IsActiveFlag_PVMO1
LL_PWR_IsActiveFlag_PVMO2
LL_PWR_IsActiveFlag_PVMO3
LL_PWR_IsActiveFlag_PVMO4
LL_PWR_IsActiveFlag_REGLPF
LL_PWR_IsActiveFlag_REGLPS
LL_PWR_IsActiveFlag_SB
LL_PWR_IsActiveFlag_VOS
LL_PWR_IsActiveFlag_WU1
LL_PWR_IsActiveFlag_WU2
LL_PWR_IsActiveFlag_WU3
LL_PWR_IsActiveFlag_WU4
LL_PWR_IsActiveFlag_WU5
LL_PWR_IsEnabledBatteryCharging
LL_PWR_IsEnabledBkUpAccess
LL_PWR_IsEnabledGPIOPullDown
LL_PWR_IsEnabledGPIOPullUp
LL_PWR_IsEnabledInternWU
LL_PWR_IsEnabledLowPowerRunMode
LL_PWR_IsEnabledPUPDCfg
LL_PWR_IsEnabledPVD
LL_PWR_IsEnabledPVM
LL_PWR_IsEnabledRange1BoostMode
LL_PWR_IsEnabledSRAM2Retention
LL_PWR_IsEnabledUCPDDeadBattery
LL_PWR_IsEnabledUCPDStandbyMode
LL_PWR_IsEnabledWakeUpPin
LL_PWR_IsWakeUpPinPolarityLow
LL_PWR_SetBattChargResistor
LL_PWR_SetPowerMode
LL_PWR_SetPVDLevel
LL_PWR_SetRegulVoltageScaling
LL_PWR_SetWakeUpPinPolarityHigh
LL_PWR_SetWakeUpPinPolarityLow
stm32g4xx_ll_rcc.c
IS_LL_RCC_ADC_CLKSOURCE
IS_LL_RCC_FDCAN_CLKSOURCE
IS_LL_RCC_I2C_CLKSOURCE
IS_LL_RCC_I2S_CLKSOURCE
IS_LL_RCC_LPTIM_CLKSOURCE
IS_LL_RCC_LPUART_CLKSOURCE
IS_LL_RCC_QUADSPI_CLKSOURCE
IS_LL_RCC_RNG_CLKSOURCE
IS_LL_RCC_SAI_CLKSOURCE
IS_LL_RCC_UART_CLKSOURCE
IS_LL_RCC_USART_CLKSOURCE
IS_LL_RCC_USB_CLKSOURCE
LL_RCC_DeInit
LL_RCC_GetADCClockFreq
LL_RCC_GetFDCANClockFreq
LL_RCC_GetI2CClockFreq
LL_RCC_GetI2SClockFreq
LL_RCC_GetLPTIMClockFreq
LL_RCC_GetLPUARTClockFreq
LL_RCC_GetQUADSPIClockFreq
LL_RCC_GetRNGClockFreq
LL_RCC_GetSAIClockFreq
LL_RCC_GetSystemClocksFreq
LL_RCC_GetUARTClockFreq
LL_RCC_GetUSARTClockFreq
LL_RCC_GetUSBClockFreq
RCC_GetHCLKClockFreq
RCC_GetPCLK1ClockFreq
RCC_GetPCLK2ClockFreq
RCC_GetSystemClockFreq
RCC_PLL_GetFreqDomain_48M
RCC_PLL_GetFreqDomain_ADC
RCC_PLL_GetFreqDomain_SYS
stm32g4xx_ll_rcc.h
__LL_RCC_CALC_PCLK1_FREQ
__LL_RCC_CALC_PCLK2_FREQ
__LL_RCC_CALC_PLLCLK_48M_FREQ
__LL_RCC_CALC_PLLCLK_ADC_FREQ
__LL_RCC_CALC_PLLCLK_FREQ
LL_RCC_ADC12_CLKSOURCE
LL_RCC_ADC12_CLKSOURCE_NONE
LL_RCC_ADC12_CLKSOURCE_PLL
LL_RCC_ADC12_CLKSOURCE_SYSCLK
LL_RCC_ADC345_CLKSOURCE
LL_RCC_ADC345_CLKSOURCE_NONE
LL_RCC_ADC345_CLKSOURCE_PLL
LL_RCC_ADC345_CLKSOURCE_SYSCLK
LL_RCC_APB1_DIV_1
LL_RCC_APB1_DIV_16
LL_RCC_APB1_DIV_2
LL_RCC_APB1_DIV_4
LL_RCC_APB1_DIV_8
LL_RCC_APB2_DIV_1
LL_RCC_APB2_DIV_16
LL_RCC_APB2_DIV_2
LL_RCC_APB2_DIV_4
LL_RCC_APB2_DIV_8
LL_RCC_CICR_CSSC
LL_RCC_CICR_HSERDYC
LL_RCC_CICR_HSI48RDYC
LL_RCC_CICR_HSIRDYC
LL_RCC_CICR_LSECSSC
LL_RCC_CICR_LSERDYC
LL_RCC_CICR_LSIRDYC
LL_RCC_CICR_PLLRDYC
LL_RCC_CIER_HSERDYIE
LL_RCC_CIER_HSI48RDYIE
LL_RCC_CIER_HSIRDYIE
LL_RCC_CIER_LSECSSIE
LL_RCC_CIER_LSERDYIE
LL_RCC_CIER_LSIRDYIE
LL_RCC_CIER_PLLRDYIE
LL_RCC_CIFR_CSSF
LL_RCC_CIFR_HSERDYF
LL_RCC_CIFR_HSI48RDYF
LL_RCC_CIFR_HSIRDYF
LL_RCC_CIFR_LSECSSF
LL_RCC_CIFR_LSERDYF
LL_RCC_CIFR_LSIRDYF
LL_RCC_CIFR_PLLRDYF
LL_RCC_CSR_BORRSTF
LL_RCC_CSR_IWDGRSTF
LL_RCC_CSR_LPWRRSTF
LL_RCC_CSR_OBLRSTF
LL_RCC_CSR_PINRSTF
LL_RCC_CSR_SFTRSTF
LL_RCC_CSR_WWDGRSTF
LL_RCC_FDCAN_CLKSOURCE
LL_RCC_FDCAN_CLKSOURCE_HSE
LL_RCC_FDCAN_CLKSOURCE_PCLK1
LL_RCC_FDCAN_CLKSOURCE_PLL
LL_RCC_I2C1_CLKSOURCE
LL_RCC_I2C1_CLKSOURCE_HSI
LL_RCC_I2C1_CLKSOURCE_PCLK1
LL_RCC_I2C1_CLKSOURCE_SYSCLK
LL_RCC_I2C2_CLKSOURCE
LL_RCC_I2C2_CLKSOURCE_HSI
LL_RCC_I2C2_CLKSOURCE_PCLK1
LL_RCC_I2C2_CLKSOURCE_SYSCLK
LL_RCC_I2C3_CLKSOURCE
LL_RCC_I2C3_CLKSOURCE_HSI
LL_RCC_I2C3_CLKSOURCE_PCLK1
LL_RCC_I2C3_CLKSOURCE_SYSCLK
LL_RCC_I2C4_CLKSOURCE
LL_RCC_I2C4_CLKSOURCE_HSI
LL_RCC_I2C4_CLKSOURCE_PCLK1
LL_RCC_I2C4_CLKSOURCE_SYSCLK
LL_RCC_I2S_CLKSOURCE
LL_RCC_I2S_CLKSOURCE_HSI
LL_RCC_I2S_CLKSOURCE_PIN
LL_RCC_I2S_CLKSOURCE_PLL
LL_RCC_I2S_CLKSOURCE_SYSCLK
LL_RCC_LPTIM1_CLKSOURCE
LL_RCC_LPTIM1_CLKSOURCE_HSI
LL_RCC_LPTIM1_CLKSOURCE_LSE
LL_RCC_LPTIM1_CLKSOURCE_LSI
LL_RCC_LPTIM1_CLKSOURCE_PCLK1
LL_RCC_LPUART1_CLKSOURCE
LL_RCC_LPUART1_CLKSOURCE_HSI
LL_RCC_LPUART1_CLKSOURCE_LSE
LL_RCC_LPUART1_CLKSOURCE_PCLK1
LL_RCC_LPUART1_CLKSOURCE_SYSCLK
LL_RCC_LSCO_CLKSOURCE_LSE
LL_RCC_LSCO_CLKSOURCE_LSI
LL_RCC_LSEDRIVE_HIGH
LL_RCC_LSEDRIVE_LOW
LL_RCC_LSEDRIVE_MEDIUMHIGH
LL_RCC_LSEDRIVE_MEDIUMLOW
LL_RCC_MCO1_DIV_1
LL_RCC_MCO1_DIV_16
LL_RCC_MCO1_DIV_2
LL_RCC_MCO1_DIV_4
LL_RCC_MCO1_DIV_8
LL_RCC_MCO1SOURCE_HSE
LL_RCC_MCO1SOURCE_HSI
LL_RCC_MCO1SOURCE_HSI48
LL_RCC_MCO1SOURCE_LSE
LL_RCC_MCO1SOURCE_LSI
LL_RCC_MCO1SOURCE_NOCLOCK
LL_RCC_MCO1SOURCE_PLLCLK
LL_RCC_MCO1SOURCE_SYSCLK
LL_RCC_PERIPH_FREQUENCY_NA
LL_RCC_PERIPH_FREQUENCY_NO
LL_RCC_PLLM_DIV_1
LL_RCC_PLLM_DIV_10
LL_RCC_PLLM_DIV_11
LL_RCC_PLLM_DIV_12
LL_RCC_PLLM_DIV_13
LL_RCC_PLLM_DIV_14
LL_RCC_PLLM_DIV_15
LL_RCC_PLLM_DIV_16
LL_RCC_PLLM_DIV_2
LL_RCC_PLLM_DIV_3
LL_RCC_PLLM_DIV_4
LL_RCC_PLLM_DIV_5
LL_RCC_PLLM_DIV_6
LL_RCC_PLLM_DIV_7
LL_RCC_PLLM_DIV_8
LL_RCC_PLLM_DIV_9
LL_RCC_PLLP_DIV_10
LL_RCC_PLLP_DIV_11
LL_RCC_PLLP_DIV_12
LL_RCC_PLLP_DIV_13
LL_RCC_PLLP_DIV_14
LL_RCC_PLLP_DIV_15
LL_RCC_PLLP_DIV_16
LL_RCC_PLLP_DIV_17
LL_RCC_PLLP_DIV_18
LL_RCC_PLLP_DIV_19
LL_RCC_PLLP_DIV_2
LL_RCC_PLLP_DIV_20
LL_RCC_PLLP_DIV_21
LL_RCC_PLLP_DIV_22
LL_RCC_PLLP_DIV_23
LL_RCC_PLLP_DIV_24
LL_RCC_PLLP_DIV_25
LL_RCC_PLLP_DIV_26
LL_RCC_PLLP_DIV_27
LL_RCC_PLLP_DIV_28
LL_RCC_PLLP_DIV_29
LL_RCC_PLLP_DIV_3
LL_RCC_PLLP_DIV_30
LL_RCC_PLLP_DIV_31
LL_RCC_PLLP_DIV_4
LL_RCC_PLLP_DIV_5
LL_RCC_PLLP_DIV_6
LL_RCC_PLLP_DIV_7
LL_RCC_PLLP_DIV_8
LL_RCC_PLLP_DIV_9
LL_RCC_PLLQ_DIV_2
LL_RCC_PLLQ_DIV_4
LL_RCC_PLLQ_DIV_6
LL_RCC_PLLQ_DIV_8
LL_RCC_PLLR_DIV_2
LL_RCC_PLLR_DIV_4
LL_RCC_PLLR_DIV_6
LL_RCC_PLLR_DIV_8
LL_RCC_PLLSOURCE_HSE
LL_RCC_PLLSOURCE_HSI
LL_RCC_PLLSOURCE_NONE
LL_RCC_QUADSPI_CLKSOURCE
LL_RCC_QUADSPI_CLKSOURCE_HSI
LL_RCC_QUADSPI_CLKSOURCE_PLL
LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
LL_RCC_ReadReg
LL_RCC_RNG_CLKSOURCE
LL_RCC_RNG_CLKSOURCE_HSI48
LL_RCC_RNG_CLKSOURCE_PLL
LL_RCC_RTC_CLKSOURCE_HSE_DIV32
LL_RCC_RTC_CLKSOURCE_LSE
LL_RCC_RTC_CLKSOURCE_LSI
LL_RCC_RTC_CLKSOURCE_NONE
LL_RCC_SAI1_CLKSOURCE
LL_RCC_SAI1_CLKSOURCE_HSI
LL_RCC_SAI1_CLKSOURCE_PIN
LL_RCC_SAI1_CLKSOURCE_PLL
LL_RCC_SAI1_CLKSOURCE_SYSCLK
LL_RCC_SYS_CLKSOURCE_HSE
LL_RCC_SYS_CLKSOURCE_HSI
LL_RCC_SYS_CLKSOURCE_PLL
LL_RCC_SYS_CLKSOURCE_STATUS_HSE
LL_RCC_SYS_CLKSOURCE_STATUS_HSI
LL_RCC_SYS_CLKSOURCE_STATUS_PLL
LL_RCC_SYSCLK_DIV_1
LL_RCC_SYSCLK_DIV_128
LL_RCC_SYSCLK_DIV_16
LL_RCC_SYSCLK_DIV_2
LL_RCC_SYSCLK_DIV_256
LL_RCC_SYSCLK_DIV_4
LL_RCC_SYSCLK_DIV_512
LL_RCC_SYSCLK_DIV_64
LL_RCC_SYSCLK_DIV_8
LL_RCC_UART4_CLKSOURCE
LL_RCC_UART4_CLKSOURCE_HSI
LL_RCC_UART4_CLKSOURCE_LSE
LL_RCC_UART4_CLKSOURCE_PCLK1
LL_RCC_UART4_CLKSOURCE_SYSCLK
LL_RCC_UART5_CLKSOURCE
LL_RCC_UART5_CLKSOURCE_HSI
LL_RCC_UART5_CLKSOURCE_LSE
LL_RCC_UART5_CLKSOURCE_PCLK1
LL_RCC_UART5_CLKSOURCE_SYSCLK
LL_RCC_USART1_CLKSOURCE
LL_RCC_USART1_CLKSOURCE_HSI
LL_RCC_USART1_CLKSOURCE_LSE
LL_RCC_USART1_CLKSOURCE_PCLK2
LL_RCC_USART1_CLKSOURCE_SYSCLK
LL_RCC_USART2_CLKSOURCE
LL_RCC_USART2_CLKSOURCE_HSI
LL_RCC_USART2_CLKSOURCE_LSE
LL_RCC_USART2_CLKSOURCE_PCLK1
LL_RCC_USART2_CLKSOURCE_SYSCLK
LL_RCC_USART3_CLKSOURCE
LL_RCC_USART3_CLKSOURCE_HSI
LL_RCC_USART3_CLKSOURCE_LSE
LL_RCC_USART3_CLKSOURCE_PCLK1
LL_RCC_USART3_CLKSOURCE_SYSCLK
LL_RCC_USB_CLKSOURCE
LL_RCC_USB_CLKSOURCE_HSI48
LL_RCC_USB_CLKSOURCE_PLL
LL_RCC_WriteReg
RCC_OFFSET_CCIPR
RCC_OFFSET_CCIPR2
LL_RCC_ClearFlag_HSECSS
LL_RCC_ClearFlag_HSERDY
LL_RCC_ClearFlag_HSI48RDY
LL_RCC_ClearFlag_HSIRDY
LL_RCC_ClearFlag_LSECSS
LL_RCC_ClearFlag_LSERDY
LL_RCC_ClearFlag_LSIRDY
LL_RCC_ClearFlag_PLLRDY
LL_RCC_ClearResetFlags
LL_RCC_ConfigMCO
LL_RCC_DeInit
LL_RCC_DisableIT_HSERDY
LL_RCC_DisableIT_HSI48RDY
LL_RCC_DisableIT_HSIRDY
LL_RCC_DisableIT_LSECSS
LL_RCC_DisableIT_LSERDY
LL_RCC_DisableIT_LSIRDY
LL_RCC_DisableIT_PLLRDY
LL_RCC_DisableRTC
LL_RCC_EnableIT_HSERDY
LL_RCC_EnableIT_HSI48RDY
LL_RCC_EnableIT_HSIRDY
LL_RCC_EnableIT_LSECSS
LL_RCC_EnableIT_LSERDY
LL_RCC_EnableIT_LSIRDY
LL_RCC_EnableIT_PLLRDY
LL_RCC_EnableRTC
LL_RCC_ForceBackupDomainReset
LL_RCC_GetADCClockFreq
LL_RCC_GetADCClockSource
LL_RCC_GetAHBPrescaler
LL_RCC_GetAPB1Prescaler
LL_RCC_GetAPB2Prescaler
LL_RCC_GetFDCANClockFreq
LL_RCC_GetFDCANClockSource
LL_RCC_GetI2CClockFreq
LL_RCC_GetI2CClockSource
LL_RCC_GetI2SClockFreq
LL_RCC_GetI2SClockSource
LL_RCC_GetLPTIMClockFreq
LL_RCC_GetLPTIMClockSource
LL_RCC_GetLPUARTClockFreq
LL_RCC_GetLPUARTClockSource
LL_RCC_GetQUADSPIClockFreq
LL_RCC_GetQUADSPIClockSource
LL_RCC_GetRNGClockFreq
LL_RCC_GetRNGClockSource
LL_RCC_GetRTCClockSource
LL_RCC_GetSAIClockFreq
LL_RCC_GetSAIClockSource
LL_RCC_GetSysClkSource
LL_RCC_GetSystemClocksFreq
LL_RCC_GetUARTClockFreq
LL_RCC_GetUARTClockSource
LL_RCC_GetUSARTClockFreq
LL_RCC_GetUSARTClockSource
LL_RCC_GetUSBClockFreq
LL_RCC_GetUSBClockSource
LL_RCC_HSE_Disable
LL_RCC_HSE_DisableBypass
LL_RCC_HSE_Enable
LL_RCC_HSE_EnableBypass
LL_RCC_HSE_EnableCSS
LL_RCC_HSE_IsReady
LL_RCC_HSI48_Disable
LL_RCC_HSI48_Enable
LL_RCC_HSI48_GetCalibration
LL_RCC_HSI48_IsReady
LL_RCC_HSI_Disable
LL_RCC_HSI_DisableInStopMode
LL_RCC_HSI_Enable
LL_RCC_HSI_EnableInStopMode
LL_RCC_HSI_GetCalibration
LL_RCC_HSI_GetCalibTrimming
LL_RCC_HSI_IsReady
LL_RCC_HSI_SetCalibTrimming
LL_RCC_IsActiveFlag_BORRST
LL_RCC_IsActiveFlag_HSECSS
LL_RCC_IsActiveFlag_HSERDY
LL_RCC_IsActiveFlag_HSI48RDY
LL_RCC_IsActiveFlag_HSIRDY
LL_RCC_IsActiveFlag_IWDGRST
LL_RCC_IsActiveFlag_LPWRRST
LL_RCC_IsActiveFlag_LSECSS
LL_RCC_IsActiveFlag_LSERDY
LL_RCC_IsActiveFlag_LSIRDY
LL_RCC_IsActiveFlag_OBLRST
LL_RCC_IsActiveFlag_PINRST
LL_RCC_IsActiveFlag_PLLRDY
LL_RCC_IsActiveFlag_SFTRST
LL_RCC_IsActiveFlag_WWDGRST
LL_RCC_IsEnabledIT_HSERDY
LL_RCC_IsEnabledIT_HSI48RDY
LL_RCC_IsEnabledIT_HSIRDY
LL_RCC_IsEnabledIT_LSECSS
LL_RCC_IsEnabledIT_LSERDY
LL_RCC_IsEnabledIT_LSIRDY
LL_RCC_IsEnabledIT_PLLRDY
LL_RCC_IsEnabledRTC
LL_RCC_LSCO_Disable
LL_RCC_LSCO_Enable
LL_RCC_LSCO_GetSource
LL_RCC_LSCO_SetSource
LL_RCC_LSE_Disable
LL_RCC_LSE_DisableBypass
LL_RCC_LSE_DisableCSS
LL_RCC_LSE_Enable
LL_RCC_LSE_EnableBypass
LL_RCC_LSE_EnableCSS
LL_RCC_LSE_GetDriveCapability
LL_RCC_LSE_IsCSSDetected
LL_RCC_LSE_IsReady
LL_RCC_LSE_SetDriveCapability
LL_RCC_LSI_Disable
LL_RCC_LSI_Enable
LL_RCC_LSI_IsReady
LL_RCC_PLL_ConfigDomain_48M
LL_RCC_PLL_ConfigDomain_ADC
LL_RCC_PLL_ConfigDomain_SYS
LL_RCC_PLL_Disable
LL_RCC_PLL_DisableDomain_48M
LL_RCC_PLL_DisableDomain_ADC
LL_RCC_PLL_DisableDomain_SYS
LL_RCC_PLL_Enable
LL_RCC_PLL_EnableDomain_48M
LL_RCC_PLL_EnableDomain_ADC
LL_RCC_PLL_EnableDomain_SYS
LL_RCC_PLL_GetDivider
LL_RCC_PLL_GetMainSource
LL_RCC_PLL_GetN
LL_RCC_PLL_GetP
LL_RCC_PLL_GetQ
LL_RCC_PLL_GetR
LL_RCC_PLL_IsEnabledDomain_48M
LL_RCC_PLL_IsEnabledDomain_ADC
LL_RCC_PLL_IsEnabledDomain_SYS
LL_RCC_PLL_IsReady
LL_RCC_PLL_SetMainSource
LL_RCC_ReleaseBackupDomainReset
LL_RCC_SetADCClockSource
LL_RCC_SetAHBPrescaler
LL_RCC_SetAPB1Prescaler
LL_RCC_SetAPB2Prescaler
LL_RCC_SetFDCANClockSource
LL_RCC_SetI2CClockSource
LL_RCC_SetI2SClockSource
LL_RCC_SetLPTIMClockSource
LL_RCC_SetLPUARTClockSource
LL_RCC_SetQUADSPIClockSource
LL_RCC_SetRNGClockSource
LL_RCC_SetRTCClockSource
LL_RCC_SetSAIClockSource
LL_RCC_SetSysClkSource
LL_RCC_SetUARTClockSource
LL_RCC_SetUSARTClockSource
LL_RCC_SetUSBClockSource
stm32g4xx_ll_rng.c
IS_LL_RNG_CED
LL_RNG_DeInit
LL_RNG_Init
LL_RNG_StructInit
stm32g4xx_ll_rng.h
LL_RNG_CED_ENABLE
LL_RNG_CR_IE
LL_RNG_ReadReg
LL_RNG_SR_CECS
LL_RNG_SR_CEIS
LL_RNG_SR_DRDY
LL_RNG_SR_SECS
LL_RNG_SR_SEIS
LL_RNG_WriteReg
LL_RNG_ClearFlag_CEIS
LL_RNG_ClearFlag_SEIS
LL_RNG_DeInit
LL_RNG_Disable
LL_RNG_DisableClkErrorDetect
LL_RNG_DisableIT
LL_RNG_Enable
LL_RNG_EnableClkErrorDetect
LL_RNG_EnableIT
LL_RNG_Init
LL_RNG_IsActiveFlag_CECS
LL_RNG_IsActiveFlag_CEIS
LL_RNG_IsActiveFlag_DRDY
LL_RNG_IsActiveFlag_SECS
LL_RNG_IsActiveFlag_SEIS
LL_RNG_IsEnabled
LL_RNG_IsEnabledClkErrorDetect
LL_RNG_IsEnabledIT
LL_RNG_ReadRandData32
LL_RNG_StructInit
stm32g4xx_ll_rtc.c
IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL
IS_LL_RTC_ALMA_MASK
IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL
IS_LL_RTC_ALMB_MASK
IS_LL_RTC_ASYNCH_PREDIV
IS_LL_RTC_DAY
IS_LL_RTC_FORMAT
IS_LL_RTC_HOUR12
IS_LL_RTC_HOUR24
IS_LL_RTC_HOURFORMAT
IS_LL_RTC_MINUTES
IS_LL_RTC_MONTH
IS_LL_RTC_SECONDS
IS_LL_RTC_SYNCH_PREDIV
IS_LL_RTC_TIME_FORMAT
IS_LL_RTC_WEEKDAY
IS_LL_RTC_YEAR
RTC_ASYNCH_PRESC_DEFAULT
RTC_INITMODE_TIMEOUT
RTC_SYNCH_PRESC_DEFAULT
RTC_SYNCHRO_TIMEOUT
LL_RTC_ALMA_Init
LL_RTC_ALMA_StructInit
LL_RTC_ALMB_Init
LL_RTC_ALMB_StructInit
LL_RTC_DATE_Init
LL_RTC_DATE_StructInit
LL_RTC_DeInit
LL_RTC_EnterInitMode
LL_RTC_ExitInitMode
LL_RTC_Init
LL_RTC_StructInit
LL_RTC_TIME_Init
LL_RTC_TIME_StructInit
LL_RTC_WaitForSynchro
stm32g4xx_ll_rtc.h
__LL_RTC_CONVERT_BIN2BCD
__LL_RTC_GET_DAY
__LL_RTC_GET_HOUR
__LL_RTC_GET_MINUTE
__LL_RTC_GET_MONTH
__LL_RTC_GET_SECOND
__LL_RTC_GET_WEEKDAY
__LL_RTC_GET_YEAR
LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
LL_RTC_ALARMOUT_ALMA
LL_RTC_ALARMOUT_ALMB
LL_RTC_ALARMOUT_DISABLE
LL_RTC_ALARMOUT_WAKEUP
LL_RTC_ALMA_DATEWEEKDAYSEL_DATE
LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY
LL_RTC_ALMA_MASK_ALL
LL_RTC_ALMA_MASK_DATEWEEKDAY
LL_RTC_ALMA_MASK_HOURS
LL_RTC_ALMA_MASK_MINUTES
LL_RTC_ALMA_MASK_NONE
LL_RTC_ALMA_MASK_SECONDS
LL_RTC_ALMA_TIME_FORMAT_AM
LL_RTC_ALMA_TIME_FORMAT_PM
LL_RTC_ALMB_DATEWEEKDAYSEL_DATE
LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY
LL_RTC_ALMB_MASK_ALL
LL_RTC_ALMB_MASK_DATEWEEKDAY
LL_RTC_ALMB_MASK_HOURS
LL_RTC_ALMB_MASK_MINUTES
LL_RTC_ALMB_MASK_NONE
LL_RTC_ALMB_MASK_SECONDS
LL_RTC_ALMB_TIME_FORMAT_AM
LL_RTC_ALMB_TIME_FORMAT_PM
LL_RTC_BKP_DR0
LL_RTC_BKP_DR1
LL_RTC_BKP_DR10
LL_RTC_BKP_DR11
LL_RTC_BKP_DR12
LL_RTC_BKP_DR13
LL_RTC_BKP_DR14
LL_RTC_BKP_DR15
LL_RTC_BKP_DR16
LL_RTC_BKP_DR17
LL_RTC_BKP_DR18
LL_RTC_BKP_DR19
LL_RTC_BKP_DR2
LL_RTC_BKP_DR20
LL_RTC_BKP_DR21
LL_RTC_BKP_DR22
LL_RTC_BKP_DR23
LL_RTC_BKP_DR24
LL_RTC_BKP_DR25
LL_RTC_BKP_DR26
LL_RTC_BKP_DR27
LL_RTC_BKP_DR28
LL_RTC_BKP_DR29
LL_RTC_BKP_DR3
LL_RTC_BKP_DR30
LL_RTC_BKP_DR31
LL_RTC_BKP_DR4
LL_RTC_BKP_DR5
LL_RTC_BKP_DR6
LL_RTC_BKP_DR7
LL_RTC_BKP_DR8
LL_RTC_BKP_DR9
LL_RTC_BKP_NUMBER
LL_RTC_CALIB_INSERTPULSE_NONE
LL_RTC_CALIB_INSERTPULSE_SET
LL_RTC_CALIB_OUTPUT_1HZ
LL_RTC_CALIB_OUTPUT_512HZ
LL_RTC_CALIB_OUTPUT_NONE
LL_RTC_CALIB_PERIOD_16SEC
LL_RTC_CALIB_PERIOD_32SEC
LL_RTC_CALIB_PERIOD_8SEC
LL_RTC_CR_ALRAIE
LL_RTC_CR_ALRBIE
LL_RTC_CR_TSIE
LL_RTC_CR_WUTIE
LL_RTC_CSR_ALRAF
LL_RTC_FORMAT_BCD
LL_RTC_FORMAT_BIN
LL_RTC_HOURFORMAT_24HOUR
LL_RTC_HOURFORMAT_AMPM
LL_RTC_ICSR_ALRAWF
LL_RTC_ICSR_ALRBWF
LL_RTC_ICSR_INITF
LL_RTC_ICSR_INITS
LL_RTC_ICSR_RECALPF
LL_RTC_ICSR_RSF
LL_RTC_ICSR_SHPF
LL_RTC_ICSR_WUTWF
LL_RTC_MONTH_APRIL
LL_RTC_MONTH_AUGUST
LL_RTC_MONTH_DECEMBER
LL_RTC_MONTH_FEBRUARY
LL_RTC_MONTH_JANUARY
LL_RTC_MONTH_JULY
LL_RTC_MONTH_JUNE
LL_RTC_MONTH_MARCH
LL_RTC_MONTH_MAY
LL_RTC_MONTH_NOVEMBER
LL_RTC_MONTH_OCTOBER
LL_RTC_MONTH_SEPTEMBER
LL_RTC_OUTPUTPOLARITY_PIN_HIGH
LL_RTC_OUTPUTPOLARITY_PIN_LOW
LL_RTC_SCR_ALRBF
LL_RTC_SCR_ITSF
LL_RTC_SCR_TSF
LL_RTC_SCR_TSOVF
LL_RTC_SCR_WUTF
LL_RTC_SHIFT_SECOND_ADVANCE
LL_RTC_SHIFT_SECOND_DELAY
LL_RTC_TAMPER_1
LL_RTC_TAMPER_2
LL_RTC_TAMPER_3
LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
LL_RTC_TAMPER_ACTIVELEVEL_TAMP3
LL_RTC_TAMPER_DURATION_1RTCCLK
LL_RTC_TAMPER_DURATION_2RTCCLK
LL_RTC_TAMPER_DURATION_4RTCCLK
LL_RTC_TAMPER_DURATION_8RTCCLK
LL_RTC_TAMPER_FILTER_2SAMPLE
LL_RTC_TAMPER_FILTER_4SAMPLE
LL_RTC_TAMPER_FILTER_8SAMPLE
LL_RTC_TAMPER_FILTER_DISABLE
LL_RTC_TAMPER_ITAMP1
LL_RTC_TAMPER_ITAMP3
LL_RTC_TAMPER_ITAMP4
LL_RTC_TAMPER_ITAMP5
LL_RTC_TAMPER_ITAMP6
LL_RTC_TAMPER_MASK_TAMPER1
LL_RTC_TAMPER_MASK_TAMPER2
LL_RTC_TAMPER_MASK_TAMPER3
LL_RTC_TAMPER_NOERASE_TAMPER1
LL_RTC_TAMPER_NOERASE_TAMPER2
LL_RTC_TAMPER_NOERASE_TAMPER3
LL_RTC_TAMPER_SAMPLFREQDIV_1024
LL_RTC_TAMPER_SAMPLFREQDIV_16384
LL_RTC_TAMPER_SAMPLFREQDIV_2048
LL_RTC_TAMPER_SAMPLFREQDIV_256
LL_RTC_TAMPER_SAMPLFREQDIV_32768
LL_RTC_TAMPER_SAMPLFREQDIV_4096
LL_RTC_TAMPER_SAMPLFREQDIV_512
LL_RTC_TAMPER_SAMPLFREQDIV_8192
LL_RTC_TIME_FORMAT_AM_OR_24
LL_RTC_TIME_FORMAT_PM
LL_RTC_TIMESTAMP_EDGE_FALLING
LL_RTC_TIMESTAMP_EDGE_RISING
LL_RTC_TS_TIME_FORMAT_AM
LL_RTC_TS_TIME_FORMAT_PM
LL_RTC_WAKEUPCLOCK_CKSPRE
LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
LL_RTC_WAKEUPCLOCK_DIV_16
LL_RTC_WAKEUPCLOCK_DIV_2
LL_RTC_WAKEUPCLOCK_DIV_4
LL_RTC_WAKEUPCLOCK_DIV_8
LL_RTC_WEEKDAY_FRIDAY
LL_RTC_WEEKDAY_MONDAY
LL_RTC_WEEKDAY_SATURDAY
LL_RTC_WEEKDAY_SUNDAY
LL_RTC_WEEKDAY_THURSDAY
LL_RTC_WEEKDAY_TUESDAY
LL_RTC_WEEKDAY_WEDNESDAY
RTC_LL_INIT_MASK
RTC_LL_RSF_MASK
RTC_OFFSET_DAY
RTC_OFFSET_HOUR
RTC_OFFSET_MINUTE
RTC_OFFSET_MONTH
RTC_OFFSET_WEEKDAY
RTC_WRITE_PROTECTION_DISABLE
RTC_WRITE_PROTECTION_ENABLE_1
RTC_WRITE_PROTECTION_ENABLE_2
LL_RTC_ALMA_ConfigTime
LL_RTC_ALMA_Disable
LL_RTC_ALMA_DisableWeekday
LL_RTC_ALMA_Enable
LL_RTC_ALMA_EnableWeekday
LL_RTC_ALMA_GetDay
LL_RTC_ALMA_GetHour
LL_RTC_ALMA_GetMask
LL_RTC_ALMA_GetMinute
LL_RTC_ALMA_GetSecond
LL_RTC_ALMA_GetSubSecond
LL_RTC_ALMA_GetSubSecondMask
LL_RTC_ALMA_GetTime
LL_RTC_ALMA_GetTimeFormat
LL_RTC_ALMA_GetWeekDay
LL_RTC_ALMA_Init
LL_RTC_ALMA_SetDay
LL_RTC_ALMA_SetHour
LL_RTC_ALMA_SetMask
LL_RTC_ALMA_SetMinute
LL_RTC_ALMA_SetSecond
LL_RTC_ALMA_SetSubSecond
LL_RTC_ALMA_SetSubSecondMask
LL_RTC_ALMA_SetTimeFormat
LL_RTC_ALMA_SetWeekDay
LL_RTC_ALMA_StructInit
LL_RTC_ALMB_ConfigTime
LL_RTC_ALMB_Disable
LL_RTC_ALMB_DisableWeekday
LL_RTC_ALMB_Enable
LL_RTC_ALMB_EnableWeekday
LL_RTC_ALMB_GetDay
LL_RTC_ALMB_GetHour
LL_RTC_ALMB_GetMask
LL_RTC_ALMB_GetMinute
LL_RTC_ALMB_GetSecond
LL_RTC_ALMB_GetSubSecond
LL_RTC_ALMB_GetSubSecondMask
LL_RTC_ALMB_GetTime
LL_RTC_ALMB_GetTimeFormat
LL_RTC_ALMB_GetWeekDay
LL_RTC_ALMB_Init
LL_RTC_ALMB_SetDay
LL_RTC_ALMB_SetHour
LL_RTC_ALMB_SetMask
LL_RTC_ALMB_SetMinute
LL_RTC_ALMB_SetSecond
LL_RTC_ALMB_SetSubSecond
LL_RTC_ALMB_SetSubSecondMask
LL_RTC_ALMB_SetTimeFormat
LL_RTC_ALMB_SetWeekDay
LL_RTC_ALMB_StructInit
LL_RTC_BKP_GetRegister
LL_RTC_BKP_SetRegister
LL_RTC_CAL_GetMinus
LL_RTC_CAL_GetOutputFreq
LL_RTC_CAL_GetPeriod
LL_RTC_CAL_IsPulseInserted
LL_RTC_CAL_SetMinus
LL_RTC_CAL_SetOutputFreq
LL_RTC_CAL_SetPeriod
LL_RTC_CAL_SetPulse
LL_RTC_ClearFlag_ALRA
LL_RTC_ClearFlag_ALRB
LL_RTC_ClearFlag_ITAMP3
LL_RTC_ClearFlag_ITAMP4
LL_RTC_ClearFlag_ITAMP5
LL_RTC_ClearFlag_ITAMP6
LL_RTC_ClearFlag_ITS
LL_RTC_ClearFlag_RS
LL_RTC_ClearFlag_TAMP1
LL_RTC_ClearFlag_TAMP2
LL_RTC_ClearFlag_TAMP3
LL_RTC_ClearFlag_TS
LL_RTC_ClearFlag_TSOV
LL_RTC_ClearFlag_WUT
LL_RTC_DATE_Config
LL_RTC_DATE_Get
LL_RTC_DATE_GetDay
LL_RTC_DATE_GetMonth
LL_RTC_DATE_GetWeekDay
LL_RTC_DATE_GetYear
LL_RTC_DATE_Init
LL_RTC_DATE_SetDay
LL_RTC_DATE_SetMonth
LL_RTC_DATE_SetWeekDay
LL_RTC_DATE_SetYear
LL_RTC_DATE_StructInit
LL_RTC_DeInit
LL_RTC_DisableAlarmPullUp
LL_RTC_DisableInitMode
LL_RTC_DisableIT_ALRA
LL_RTC_DisableIT_ALRB
LL_RTC_DisableIT_ITAMP3
LL_RTC_DisableIT_ITAMP4
LL_RTC_DisableIT_ITAMP5
LL_RTC_DisableIT_ITAMP6
LL_RTC_DisableIT_TAMP1
LL_RTC_DisableIT_TAMP2
LL_RTC_DisableIT_TAMP3
LL_RTC_DisableIT_TS
LL_RTC_DisableIT_WUT
LL_RTC_DisableOutput2
LL_RTC_DisableRefClock
LL_RTC_DisableShadowRegBypass
LL_RTC_DisableTamperOutput
LL_RTC_DisableWriteProtection
LL_RTC_EnableAlarmPullUp
LL_RTC_EnableInitMode
LL_RTC_EnableIT_ALRA
LL_RTC_EnableIT_ALRB
LL_RTC_EnableIT_ITAMP3
LL_RTC_EnableIT_ITAMP4
LL_RTC_EnableIT_ITAMP5
LL_RTC_EnableIT_ITAMP6
LL_RTC_EnableIT_TAMP1
LL_RTC_EnableIT_TAMP2
LL_RTC_EnableIT_TAMP3
LL_RTC_EnableIT_TS
LL_RTC_EnableIT_WUT
LL_RTC_EnableOutput2
LL_RTC_EnableRefClock
LL_RTC_EnableShadowRegBypass
LL_RTC_EnableTamperOutput
LL_RTC_EnableWriteProtection
LL_RTC_EnterInitMode
LL_RTC_ExitInitMode
LL_RTC_GetAlarmOutEvent
LL_RTC_GetAlarmOutputType
LL_RTC_GetAsynchPrescaler
LL_RTC_GetHourFormat
LL_RTC_GetOutputPolarity
LL_RTC_GetSynchPrescaler
LL_RTC_Init
LL_RTC_IsActiveFlag_ALRA
LL_RTC_IsActiveFlag_ALRAM
LL_RTC_IsActiveFlag_ALRAW
LL_RTC_IsActiveFlag_ALRB
LL_RTC_IsActiveFlag_ALRBM
LL_RTC_IsActiveFlag_ALRBW
LL_RTC_IsActiveFlag_INIT
LL_RTC_IsActiveFlag_INITS
LL_RTC_IsActiveFlag_ITAMP3
LL_RTC_IsActiveFlag_ITAMP3M
LL_RTC_IsActiveFlag_ITAMP4
LL_RTC_IsActiveFlag_ITAMP4M
LL_RTC_IsActiveFlag_ITAMP5
LL_RTC_IsActiveFlag_ITAMP5M
LL_RTC_IsActiveFlag_ITAMP6
LL_RTC_IsActiveFlag_ITAMP6M
LL_RTC_IsActiveFlag_ITS
LL_RTC_IsActiveFlag_ITSM
LL_RTC_IsActiveFlag_RECALP
LL_RTC_IsActiveFlag_RS
LL_RTC_IsActiveFlag_SHP
LL_RTC_IsActiveFlag_TAMP1
LL_RTC_IsActiveFlag_TAMP1M
LL_RTC_IsActiveFlag_TAMP2
LL_RTC_IsActiveFlag_TAMP2M
LL_RTC_IsActiveFlag_TAMP3
LL_RTC_IsActiveFlag_TAMP3M
LL_RTC_IsActiveFlag_TS
LL_RTC_IsActiveFlag_TSM
LL_RTC_IsActiveFlag_TSOV
LL_RTC_IsActiveFlag_TSOVM
LL_RTC_IsActiveFlag_WUT
LL_RTC_IsActiveFlag_WUTM
LL_RTC_IsActiveFlag_WUTW
LL_RTC_IsAlarmPullUpEnabled
LL_RTC_IsEnabledIT_ALRA
LL_RTC_IsEnabledIT_ALRB
LL_RTC_IsEnabledIT_ITAMP3
LL_RTC_IsEnabledIT_ITAMP4
LL_RTC_IsEnabledIT_ITAMP5
LL_RTC_IsEnabledIT_ITAMP6
LL_RTC_IsEnabledIT_TAMP1
LL_RTC_IsEnabledIT_TAMP2
LL_RTC_IsEnabledIT_TAMP3
LL_RTC_IsEnabledIT_TS
LL_RTC_IsEnabledIT_WUT
LL_RTC_IsOutput2Enabled
LL_RTC_IsShadowRegBypassEnabled
LL_RTC_IsTamperOutputEnabled
LL_RTC_SetAlarmOutEvent
LL_RTC_SetAlarmOutputType
LL_RTC_SetAsynchPrescaler
LL_RTC_SetHourFormat
LL_RTC_SetOutputPolarity
LL_RTC_SetSynchPrescaler
LL_RTC_StructInit
LL_RTC_TAMPER_Disable
LL_RTC_TAMPER_DisableActiveLevel
LL_RTC_TAMPER_DisableEraseBKP
LL_RTC_TAMPER_DisableMask
LL_RTC_TAMPER_DisablePullUp
LL_RTC_TAMPER_Enable
LL_RTC_TAMPER_EnableActiveLevel
LL_RTC_TAMPER_EnableEraseBKP
LL_RTC_TAMPER_EnableMask
LL_RTC_TAMPER_EnablePullUp
LL_RTC_TAMPER_GetFilterCount
LL_RTC_TAMPER_GetPrecharge
LL_RTC_TAMPER_GetSamplingFreq
LL_RTC_TAMPER_ITAMP_Disable
LL_RTC_TAMPER_ITAMP_Enable
LL_RTC_TAMPER_SetFilterCount
LL_RTC_TAMPER_SetPrecharge
LL_RTC_TAMPER_SetSamplingFreq
LL_RTC_TIME_Config
LL_RTC_TIME_DecHour
LL_RTC_TIME_DisableDayLightStore
LL_RTC_TIME_EnableDayLightStore
LL_RTC_TIME_Get
LL_RTC_TIME_GetFormat
LL_RTC_TIME_GetHour
LL_RTC_TIME_GetMinute
LL_RTC_TIME_GetSecond
LL_RTC_TIME_GetSubSecond
LL_RTC_TIME_IncHour
LL_RTC_TIME_Init
LL_RTC_TIME_IsDayLightStoreEnabled
LL_RTC_TIME_SetFormat
LL_RTC_TIME_SetHour
LL_RTC_TIME_SetMinute
LL_RTC_TIME_SetSecond
LL_RTC_TIME_StructInit
LL_RTC_TIME_Synchronize
LL_RTC_TS_Disable
LL_RTC_TS_DisableInternalEvent
LL_RTC_TS_DisableOnTamper
LL_RTC_TS_Enable
LL_RTC_TS_EnableInternalEvent
LL_RTC_TS_EnableOnTamper
LL_RTC_TS_GetActiveEdge
LL_RTC_TS_GetDate
LL_RTC_TS_GetDay
LL_RTC_TS_GetHour
LL_RTC_TS_GetMinute
LL_RTC_TS_GetMonth
LL_RTC_TS_GetSecond
LL_RTC_TS_GetSubSecond
LL_RTC_TS_GetTime
LL_RTC_TS_GetTimeFormat
LL_RTC_TS_GetWeekDay
LL_RTC_TS_SetActiveEdge
LL_RTC_WaitForSynchro
LL_RTC_WAKEUP_Disable
LL_RTC_WAKEUP_Enable
LL_RTC_WAKEUP_GetAutoReload
LL_RTC_WAKEUP_GetClock
LL_RTC_WAKEUP_IsEnabled
LL_RTC_WAKEUP_SetAutoReload
LL_RTC_WAKEUP_SetClock
stm32g4xx_ll_spi.c
I2S_I2SCFGR_CLEAR_MASK
I2S_I2SPR_CLEAR_MASK
IS_LL_I2S_AUDIO_FREQ
IS_LL_I2S_CPOL
IS_LL_I2S_DATAFORMAT
IS_LL_I2S_MCLK_OUTPUT
IS_LL_I2S_MODE
IS_LL_I2S_PRESCALER_LINEAR
IS_LL_I2S_PRESCALER_PARITY
IS_LL_I2S_STANDARD
IS_LL_SPI_BAUDRATE
IS_LL_SPI_BITORDER
IS_LL_SPI_CRC_POLYNOMIAL
IS_LL_SPI_CRCCALCULATION
IS_LL_SPI_DATAWIDTH
IS_LL_SPI_MODE
IS_LL_SPI_NSS
IS_LL_SPI_PHASE
IS_LL_SPI_POLARITY
IS_LL_SPI_TRANSFER_DIRECTION
SPI_CR1_CLEAR_MASK
LL_I2S_ConfigPrescaler
LL_I2S_DeInit
LL_I2S_Init
LL_I2S_StructInit
LL_SPI_DeInit
LL_SPI_Init
LL_SPI_StructInit
stm32g4xx_ll_spi.h
LL_I2S_AUDIOFREQ_16K
LL_I2S_AUDIOFREQ_192K
LL_I2S_AUDIOFREQ_22K
LL_I2S_AUDIOFREQ_32K
LL_I2S_AUDIOFREQ_44K
LL_I2S_AUDIOFREQ_48K
LL_I2S_AUDIOFREQ_8K
LL_I2S_AUDIOFREQ_96K
LL_I2S_AUDIOFREQ_DEFAULT
LL_I2S_CR2_ERRIE
LL_I2S_CR2_RXNEIE
LL_I2S_CR2_TXEIE
LL_I2S_DATAFORMAT_16B
LL_I2S_DATAFORMAT_16B_EXTENDED
LL_I2S_DATAFORMAT_24B
LL_I2S_DATAFORMAT_32B
LL_I2S_MCLK_OUTPUT_DISABLE
LL_I2S_MCLK_OUTPUT_ENABLE
LL_I2S_MODE_MASTER_RX
LL_I2S_MODE_MASTER_TX
LL_I2S_MODE_SLAVE_RX
LL_I2S_MODE_SLAVE_TX
LL_I2S_POLARITY_HIGH
LL_I2S_POLARITY_LOW
LL_I2S_PRESCALER_PARITY_EVEN
LL_I2S_PRESCALER_PARITY_ODD
LL_I2S_ReadReg
LL_I2S_SR_BSY
LL_I2S_SR_FRE
LL_I2S_SR_OVR
LL_I2S_SR_RXNE
LL_I2S_SR_TXE
LL_I2S_SR_UDR
LL_I2S_STANDARD_LSB
LL_I2S_STANDARD_MSB
LL_I2S_STANDARD_PCM_LONG
LL_I2S_STANDARD_PCM_SHORT
LL_I2S_STANDARD_PHILIPS
LL_I2S_WriteReg
LL_SPI_BAUDRATEPRESCALER_DIV128
LL_SPI_BAUDRATEPRESCALER_DIV16
LL_SPI_BAUDRATEPRESCALER_DIV2
LL_SPI_BAUDRATEPRESCALER_DIV256
LL_SPI_BAUDRATEPRESCALER_DIV32
LL_SPI_BAUDRATEPRESCALER_DIV4
LL_SPI_BAUDRATEPRESCALER_DIV64
LL_SPI_BAUDRATEPRESCALER_DIV8
LL_SPI_CR2_ERRIE
LL_SPI_CR2_RXNEIE
LL_SPI_CR2_TXEIE
LL_SPI_CRC_16BIT
LL_SPI_CRC_8BIT
LL_SPI_CRCCALCULATION_DISABLE
LL_SPI_CRCCALCULATION_ENABLE
LL_SPI_DATAWIDTH_10BIT
LL_SPI_DATAWIDTH_11BIT
LL_SPI_DATAWIDTH_12BIT
LL_SPI_DATAWIDTH_13BIT
LL_SPI_DATAWIDTH_14BIT
LL_SPI_DATAWIDTH_15BIT
LL_SPI_DATAWIDTH_16BIT
LL_SPI_DATAWIDTH_4BIT
LL_SPI_DATAWIDTH_5BIT
LL_SPI_DATAWIDTH_6BIT
LL_SPI_DATAWIDTH_7BIT
LL_SPI_DATAWIDTH_8BIT
LL_SPI_DATAWIDTH_9BIT
LL_SPI_DMA_PARITY_EVEN
LL_SPI_DMA_PARITY_ODD
LL_SPI_FULL_DUPLEX
LL_SPI_HALF_DUPLEX_RX
LL_SPI_HALF_DUPLEX_TX
LL_SPI_LSB_FIRST
LL_SPI_MODE_MASTER
LL_SPI_MODE_SLAVE
LL_SPI_MSB_FIRST
LL_SPI_NSS_HARD_INPUT
LL_SPI_NSS_HARD_OUTPUT
LL_SPI_NSS_SOFT
LL_SPI_PHASE_1EDGE
LL_SPI_PHASE_2EDGE
LL_SPI_POLARITY_HIGH
LL_SPI_POLARITY_LOW
LL_SPI_PROTOCOL_MOTOROLA
LL_SPI_PROTOCOL_TI
LL_SPI_ReadReg
LL_SPI_RX_FIFO_EMPTY
LL_SPI_RX_FIFO_FULL
LL_SPI_RX_FIFO_HALF_FULL
LL_SPI_RX_FIFO_QUARTER_FULL
LL_SPI_RX_FIFO_TH_HALF
LL_SPI_RX_FIFO_TH_QUARTER
LL_SPI_SIMPLEX_RX
LL_SPI_SR_BSY
LL_SPI_SR_CRCERR
LL_SPI_SR_FRE
LL_SPI_SR_MODF
LL_SPI_SR_OVR
LL_SPI_SR_RXNE
LL_SPI_SR_TXE
LL_SPI_TX_FIFO_EMPTY
LL_SPI_TX_FIFO_FULL
LL_SPI_TX_FIFO_HALF_FULL
LL_SPI_TX_FIFO_QUARTER_FULL
LL_SPI_WriteReg
LL_I2S_ClearFlag_FRE
LL_I2S_ClearFlag_OVR
LL_I2S_ClearFlag_UDR
LL_I2S_ConfigPrescaler
LL_I2S_DeInit
LL_I2S_Disable
LL_I2S_DisableAsyncStart
LL_I2S_DisableDMAReq_RX
LL_I2S_DisableDMAReq_TX
LL_I2S_DisableIT_ERR
LL_I2S_DisableIT_RXNE
LL_I2S_DisableIT_TXE
LL_I2S_DisableMasterClock
LL_I2S_Enable
LL_I2S_EnableAsyncStart
LL_I2S_EnableDMAReq_RX
LL_I2S_EnableDMAReq_TX
LL_I2S_EnableIT_ERR
LL_I2S_EnableIT_RXNE
LL_I2S_EnableIT_TXE
LL_I2S_EnableMasterClock
LL_I2S_GetClockPolarity
LL_I2S_GetDataFormat
LL_I2S_GetPrescalerLinear
LL_I2S_GetPrescalerParity
LL_I2S_GetStandard
LL_I2S_GetTransferMode
LL_I2S_Init
LL_I2S_IsActiveFlag_BSY
LL_I2S_IsActiveFlag_CHSIDE
LL_I2S_IsActiveFlag_FRE
LL_I2S_IsActiveFlag_OVR
LL_I2S_IsActiveFlag_RXNE
LL_I2S_IsActiveFlag_TXE
LL_I2S_IsActiveFlag_UDR
LL_I2S_IsEnabled
LL_I2S_IsEnabledAsyncStart
LL_I2S_IsEnabledDMAReq_RX
LL_I2S_IsEnabledDMAReq_TX
LL_I2S_IsEnabledIT_ERR
LL_I2S_IsEnabledIT_RXNE
LL_I2S_IsEnabledIT_TXE
LL_I2S_IsEnabledMasterClock
LL_I2S_ReceiveData16
LL_I2S_SetClockPolarity
LL_I2S_SetDataFormat
LL_I2S_SetPrescalerLinear
LL_I2S_SetPrescalerParity
LL_I2S_SetStandard
LL_I2S_SetTransferMode
LL_I2S_StructInit
LL_I2S_TransmitData16
LL_SPI_ClearFlag_CRCERR
LL_SPI_ClearFlag_FRE
LL_SPI_ClearFlag_MODF
LL_SPI_ClearFlag_OVR
LL_SPI_DeInit
LL_SPI_Disable
LL_SPI_DisableCRC
LL_SPI_DisableDMAReq_RX
LL_SPI_DisableDMAReq_TX
LL_SPI_DisableIT_ERR
LL_SPI_DisableIT_RXNE
LL_SPI_DisableIT_TXE
LL_SPI_DisableNSSPulseMgt
LL_SPI_DMA_GetRegAddr
LL_SPI_Enable
LL_SPI_EnableCRC
LL_SPI_EnableDMAReq_RX
LL_SPI_EnableDMAReq_TX
LL_SPI_EnableIT_ERR
LL_SPI_EnableIT_RXNE
LL_SPI_EnableIT_TXE
LL_SPI_EnableNSSPulseMgt
LL_SPI_GetBaudRatePrescaler
LL_SPI_GetClockPhase
LL_SPI_GetClockPolarity
LL_SPI_GetCRCPolynomial
LL_SPI_GetCRCWidth
LL_SPI_GetDataWidth
LL_SPI_GetDMAParity_RX
LL_SPI_GetDMAParity_TX
LL_SPI_GetMode
LL_SPI_GetNSSMode
LL_SPI_GetRxCRC
LL_SPI_GetRxFIFOLevel
LL_SPI_GetRxFIFOThreshold
LL_SPI_GetStandard
LL_SPI_GetTransferBitOrder
LL_SPI_GetTransferDirection
LL_SPI_GetTxCRC
LL_SPI_GetTxFIFOLevel
LL_SPI_Init
LL_SPI_IsActiveFlag_BSY
LL_SPI_IsActiveFlag_CRCERR
LL_SPI_IsActiveFlag_FRE
LL_SPI_IsActiveFlag_MODF
LL_SPI_IsActiveFlag_OVR
LL_SPI_IsActiveFlag_RXNE
LL_SPI_IsActiveFlag_TXE
LL_SPI_IsEnabled
LL_SPI_IsEnabledCRC
LL_SPI_IsEnabledDMAReq_RX
LL_SPI_IsEnabledDMAReq_TX
LL_SPI_IsEnabledIT_ERR
LL_SPI_IsEnabledIT_RXNE
LL_SPI_IsEnabledIT_TXE
LL_SPI_IsEnabledNSSPulse
LL_SPI_ReceiveData16
LL_SPI_ReceiveData8
LL_SPI_SetBaudRatePrescaler
LL_SPI_SetClockPhase
LL_SPI_SetClockPolarity
LL_SPI_SetCRCNext
LL_SPI_SetCRCPolynomial
LL_SPI_SetCRCWidth
LL_SPI_SetDataWidth
LL_SPI_SetDMAParity_RX
LL_SPI_SetDMAParity_TX
LL_SPI_SetMode
LL_SPI_SetNSSMode
LL_SPI_SetRxFIFOThreshold
LL_SPI_SetStandard
LL_SPI_SetTransferBitOrder
LL_SPI_SetTransferDirection
LL_SPI_StructInit
LL_SPI_TransmitData16
LL_SPI_TransmitData8
stm32g4xx_ll_system.h
FLASH_PDKEY1
FLASH_PDKEY2
LL_DBGMCU_APB1_GRP1_I2C1_STOP
LL_DBGMCU_APB1_GRP1_I2C2_STOP
LL_DBGMCU_APB1_GRP1_I2C3_STOP
LL_DBGMCU_APB1_GRP1_IWDG_STOP
LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
LL_DBGMCU_APB1_GRP1_RTC_STOP
LL_DBGMCU_APB1_GRP1_TIM2_STOP
LL_DBGMCU_APB1_GRP1_TIM3_STOP
LL_DBGMCU_APB1_GRP1_TIM4_STOP
LL_DBGMCU_APB1_GRP1_TIM5_STOP
LL_DBGMCU_APB1_GRP1_TIM6_STOP
LL_DBGMCU_APB1_GRP1_TIM7_STOP
LL_DBGMCU_APB1_GRP1_WWDG_STOP
LL_DBGMCU_APB1_GRP2_I2C4_STOP
LL_DBGMCU_APB2_GRP1_HRTIM1_STOP
LL_DBGMCU_APB2_GRP1_TIM15_STOP
LL_DBGMCU_APB2_GRP1_TIM16_STOP
LL_DBGMCU_APB2_GRP1_TIM17_STOP
LL_DBGMCU_APB2_GRP1_TIM1_STOP
LL_DBGMCU_APB2_GRP1_TIM20_STOP
LL_DBGMCU_APB2_GRP1_TIM8_STOP
LL_DBGMCU_TRACE_ASYNCH
LL_DBGMCU_TRACE_NONE
LL_DBGMCU_TRACE_SYNCH_SIZE1
LL_DBGMCU_TRACE_SYNCH_SIZE2
LL_DBGMCU_TRACE_SYNCH_SIZE4
LL_FLASH_LATENCY_0
LL_FLASH_LATENCY_1
LL_FLASH_LATENCY_10
LL_FLASH_LATENCY_11
LL_FLASH_LATENCY_12
LL_FLASH_LATENCY_13
LL_FLASH_LATENCY_14
LL_FLASH_LATENCY_15
LL_FLASH_LATENCY_2
LL_FLASH_LATENCY_3
LL_FLASH_LATENCY_4
LL_FLASH_LATENCY_5
LL_FLASH_LATENCY_6
LL_FLASH_LATENCY_7
LL_FLASH_LATENCY_8
LL_FLASH_LATENCY_9
LL_SYSCFG_BANKMODE_BANK1
LL_SYSCFG_BANKMODE_BANK2
LL_SYSCFG_CCMSRAMWRP_PAGE0
LL_SYSCFG_CCMSRAMWRP_PAGE1
LL_SYSCFG_CCMSRAMWRP_PAGE10
LL_SYSCFG_CCMSRAMWRP_PAGE11
LL_SYSCFG_CCMSRAMWRP_PAGE12
LL_SYSCFG_CCMSRAMWRP_PAGE13
LL_SYSCFG_CCMSRAMWRP_PAGE14
LL_SYSCFG_CCMSRAMWRP_PAGE15
LL_SYSCFG_CCMSRAMWRP_PAGE16
LL_SYSCFG_CCMSRAMWRP_PAGE17
LL_SYSCFG_CCMSRAMWRP_PAGE18
LL_SYSCFG_CCMSRAMWRP_PAGE19
LL_SYSCFG_CCMSRAMWRP_PAGE2
LL_SYSCFG_CCMSRAMWRP_PAGE20
LL_SYSCFG_CCMSRAMWRP_PAGE21
LL_SYSCFG_CCMSRAMWRP_PAGE22
LL_SYSCFG_CCMSRAMWRP_PAGE23
LL_SYSCFG_CCMSRAMWRP_PAGE24
LL_SYSCFG_CCMSRAMWRP_PAGE25
LL_SYSCFG_CCMSRAMWRP_PAGE26
LL_SYSCFG_CCMSRAMWRP_PAGE27
LL_SYSCFG_CCMSRAMWRP_PAGE28
LL_SYSCFG_CCMSRAMWRP_PAGE29
LL_SYSCFG_CCMSRAMWRP_PAGE3
LL_SYSCFG_CCMSRAMWRP_PAGE30
LL_SYSCFG_CCMSRAMWRP_PAGE31
LL_SYSCFG_CCMSRAMWRP_PAGE4
LL_SYSCFG_CCMSRAMWRP_PAGE5
LL_SYSCFG_CCMSRAMWRP_PAGE6
LL_SYSCFG_CCMSRAMWRP_PAGE7
LL_SYSCFG_CCMSRAMWRP_PAGE8
LL_SYSCFG_CCMSRAMWRP_PAGE9
LL_SYSCFG_EXTI_LINE0
LL_SYSCFG_EXTI_LINE1
LL_SYSCFG_EXTI_LINE10
LL_SYSCFG_EXTI_LINE11
LL_SYSCFG_EXTI_LINE12
LL_SYSCFG_EXTI_LINE13
LL_SYSCFG_EXTI_LINE14
LL_SYSCFG_EXTI_LINE15
LL_SYSCFG_EXTI_LINE2
LL_SYSCFG_EXTI_LINE3
LL_SYSCFG_EXTI_LINE4
LL_SYSCFG_EXTI_LINE5
LL_SYSCFG_EXTI_LINE6
LL_SYSCFG_EXTI_LINE7
LL_SYSCFG_EXTI_LINE8
LL_SYSCFG_EXTI_LINE9
LL_SYSCFG_EXTI_PORTA
LL_SYSCFG_EXTI_PORTB
LL_SYSCFG_EXTI_PORTC
LL_SYSCFG_EXTI_PORTD
LL_SYSCFG_EXTI_PORTE
LL_SYSCFG_EXTI_PORTF
LL_SYSCFG_EXTI_PORTG
LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
LL_SYSCFG_I2C_FASTMODEPLUS_PB6
LL_SYSCFG_I2C_FASTMODEPLUS_PB7
LL_SYSCFG_I2C_FASTMODEPLUS_PB8
LL_SYSCFG_I2C_FASTMODEPLUS_PB9
LL_SYSCFG_REMAP_FLASH
LL_SYSCFG_REMAP_FMC
LL_SYSCFG_REMAP_QUADSPI
LL_SYSCFG_REMAP_SRAM
LL_SYSCFG_REMAP_SYSTEMFLASH
LL_SYSCFG_TIMBREAK_ECC
LL_SYSCFG_TIMBREAK_LOCKUP
LL_SYSCFG_TIMBREAK_PVD
LL_SYSCFG_TIMBREAK_SRAM_PARITY
LL_VREFBUF_VOLTAGE_SCALE0
LL_VREFBUF_VOLTAGE_SCALE1
LL_VREFBUF_VOLTAGE_SCALE2
LL_DBGMCU_APB1_GRP1_FreezePeriph
LL_DBGMCU_APB1_GRP1_UnFreezePeriph
LL_DBGMCU_APB1_GRP2_FreezePeriph
LL_DBGMCU_APB1_GRP2_UnFreezePeriph
LL_DBGMCU_APB2_GRP1_FreezePeriph
LL_DBGMCU_APB2_GRP1_UnFreezePeriph
LL_DBGMCU_DisableDBGSleepMode
LL_DBGMCU_DisableDBGStandbyMode
LL_DBGMCU_DisableDBGStopMode
LL_DBGMCU_EnableDBGSleepMode
LL_DBGMCU_EnableDBGStandbyMode
LL_DBGMCU_EnableDBGStopMode
LL_DBGMCU_GetDeviceID
LL_DBGMCU_GetRevisionID
LL_DBGMCU_GetTracePinAssignment
LL_DBGMCU_SetTracePinAssignment
LL_FLASH_DisableDataCache
LL_FLASH_DisableDataCacheReset
LL_FLASH_DisableInstCache
LL_FLASH_DisableInstCacheReset
LL_FLASH_DisablePrefetch
LL_FLASH_DisableRunPowerDown
LL_FLASH_DisableSleepPowerDown
LL_FLASH_EnableDataCache
LL_FLASH_EnableDataCacheReset
LL_FLASH_EnableInstCache
LL_FLASH_EnableInstCacheReset
LL_FLASH_EnablePrefetch
LL_FLASH_EnableRunPowerDown
LL_FLASH_EnableSleepPowerDown
LL_FLASH_GetLatency
LL_FLASH_IsPrefetchEnabled
LL_FLASH_SetLatency
LL_SYSCFG_ClearFlag_SP
LL_SYSCFG_DisableAnalogBooster
LL_SYSCFG_DisableFastModePlus
LL_SYSCFG_DisableIT_FPU_DZC
LL_SYSCFG_DisableIT_FPU_IDC
LL_SYSCFG_DisableIT_FPU_IOC
LL_SYSCFG_DisableIT_FPU_IXC
LL_SYSCFG_DisableIT_FPU_OFC
LL_SYSCFG_DisableIT_FPU_UFC
LL_SYSCFG_EnableAnalogBooster
LL_SYSCFG_EnableCCMSRAMErase
LL_SYSCFG_EnableCCMSRAMPageWRP
LL_SYSCFG_EnableFastModePlus
LL_SYSCFG_EnableIT_FPU_DZC
LL_SYSCFG_EnableIT_FPU_IDC
LL_SYSCFG_EnableIT_FPU_IOC
LL_SYSCFG_EnableIT_FPU_IXC
LL_SYSCFG_EnableIT_FPU_OFC
LL_SYSCFG_EnableIT_FPU_UFC
LL_SYSCFG_GetEXTISource
LL_SYSCFG_GetFlashBankMode
LL_SYSCFG_GetRemapMemory
LL_SYSCFG_GetTIMBreakInputs
LL_SYSCFG_IsActiveFlag_SP
LL_SYSCFG_IsCCMSRAMEraseOngoing
LL_SYSCFG_IsEnabledIT_FPU_DZC
LL_SYSCFG_IsEnabledIT_FPU_IDC
LL_SYSCFG_IsEnabledIT_FPU_IOC
LL_SYSCFG_IsEnabledIT_FPU_IXC
LL_SYSCFG_IsEnabledIT_FPU_OFC
LL_SYSCFG_IsEnabledIT_FPU_UFC
LL_SYSCFG_LockCCMSRAMWRP
LL_SYSCFG_SetEXTISource
LL_SYSCFG_SetFlashBankMode
LL_SYSCFG_SetRemapMemory
LL_SYSCFG_SetTIMBreakInputs
LL_SYSCFG_UnlockCCMSRAMWRP
LL_VREFBUF_Disable
LL_VREFBUF_DisableHIZ
LL_VREFBUF_Enable
LL_VREFBUF_EnableHIZ
LL_VREFBUF_GetTrimming
LL_VREFBUF_GetVoltageScaling
LL_VREFBUF_IsVREFReady
LL_VREFBUF_SetTrimming
LL_VREFBUF_SetVoltageScaling
stm32g4xx_ll_tim.c
IS_LL_TIM_ACTIVEINPUT
IS_LL_TIM_AUTOMATIC_OUTPUT_STATE
IS_LL_TIM_BREAK2_AFMODE
IS_LL_TIM_BREAK2_FILTER
IS_LL_TIM_BREAK2_POLARITY
IS_LL_TIM_BREAK2_STATE
IS_LL_TIM_BREAK_AFMODE
IS_LL_TIM_BREAK_FILTER
IS_LL_TIM_BREAK_POLARITY
IS_LL_TIM_BREAK_STATE
IS_LL_TIM_CLOCKDIVISION
IS_LL_TIM_COUNTERMODE
IS_LL_TIM_ENCODERMODE
IS_LL_TIM_IC_FILTER
IS_LL_TIM_IC_POLARITY
IS_LL_TIM_IC_POLARITY_ENCODER
IS_LL_TIM_ICPSC
IS_LL_TIM_LOCK_LEVEL
IS_LL_TIM_OCIDLESTATE
IS_LL_TIM_OCMODE
IS_LL_TIM_OCPOLARITY
IS_LL_TIM_OCSTATE
IS_LL_TIM_OSSI_STATE
IS_LL_TIM_OSSR_STATE
IC1Config
IC2Config
IC3Config
IC4Config
LL_TIM_BDTR_Init
LL_TIM_BDTR_StructInit
LL_TIM_DeInit
LL_TIM_ENCODER_Init
LL_TIM_ENCODER_StructInit
LL_TIM_HALLSENSOR_Init
LL_TIM_HALLSENSOR_StructInit
LL_TIM_IC_Init
LL_TIM_IC_StructInit
LL_TIM_Init
LL_TIM_OC_Init
LL_TIM_OC_StructInit
LL_TIM_StructInit
OC1Config
OC2Config
OC3Config
OC4Config
OC5Config
OC6Config
stm32g4xx_ll_tim.h
__LL_TIM_CALC_ARR_DITHER
__LL_TIM_CALC_DEADTIME
__LL_TIM_CALC_DELAY
__LL_TIM_CALC_DELAY_DITHER
__LL_TIM_CALC_PSC
__LL_TIM_CALC_PULSE
__LL_TIM_CALC_PULSE_DITHER
__LL_TIM_GET_ICPSC_RATIO
__LL_TIM_GETFLAG_UIFCPY
DT_DELAY_1
DT_DELAY_2
DT_DELAY_3
DT_DELAY_4
DT_RANGE_1
DT_RANGE_2
DT_RANGE_3
DT_RANGE_4
LL_TIM_ACTIVEINPUT_DIRECTTI
LL_TIM_ACTIVEINPUT_INDIRECTTI
LL_TIM_ACTIVEINPUT_TRC
LL_TIM_AUTOMATICOUTPUT_DISABLE
LL_TIM_AUTOMATICOUTPUT_ENABLE
LL_TIM_BKIN_POLARITY_HIGH
LL_TIM_BKIN_POLARITY_LOW
LL_TIM_BKIN_SOURCE_BKCOMP1
LL_TIM_BKIN_SOURCE_BKCOMP2
LL_TIM_BKIN_SOURCE_BKCOMP3
LL_TIM_BKIN_SOURCE_BKCOMP4
LL_TIM_BKIN_SOURCE_BKCOMP5
LL_TIM_BKIN_SOURCE_BKCOMP6
LL_TIM_BKIN_SOURCE_BKCOMP7
LL_TIM_BKIN_SOURCE_BKIN
LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
LL_TIM_BREAK2_AFMODE_INPUT
LL_TIM_BREAK2_DISABLE
LL_TIM_BREAK2_ENABLE
LL_TIM_BREAK2_FILTER_FDIV1
LL_TIM_BREAK2_FILTER_FDIV16_N5
LL_TIM_BREAK2_FILTER_FDIV16_N6
LL_TIM_BREAK2_FILTER_FDIV16_N8
LL_TIM_BREAK2_FILTER_FDIV1_N2
LL_TIM_BREAK2_FILTER_FDIV1_N4
LL_TIM_BREAK2_FILTER_FDIV1_N8
LL_TIM_BREAK2_FILTER_FDIV2_N6
LL_TIM_BREAK2_FILTER_FDIV2_N8
LL_TIM_BREAK2_FILTER_FDIV32_N5
LL_TIM_BREAK2_FILTER_FDIV32_N6
LL_TIM_BREAK2_FILTER_FDIV32_N8
LL_TIM_BREAK2_FILTER_FDIV4_N6
LL_TIM_BREAK2_FILTER_FDIV4_N8
LL_TIM_BREAK2_FILTER_FDIV8_N6
LL_TIM_BREAK2_FILTER_FDIV8_N8
LL_TIM_BREAK2_POLARITY_HIGH
LL_TIM_BREAK2_POLARITY_LOW
LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
LL_TIM_BREAK_AFMODE_INPUT
LL_TIM_BREAK_DISABLE
LL_TIM_BREAK_ENABLE
LL_TIM_BREAK_FILTER_FDIV1
LL_TIM_BREAK_FILTER_FDIV16_N5
LL_TIM_BREAK_FILTER_FDIV16_N6
LL_TIM_BREAK_FILTER_FDIV16_N8
LL_TIM_BREAK_FILTER_FDIV1_N2
LL_TIM_BREAK_FILTER_FDIV1_N4
LL_TIM_BREAK_FILTER_FDIV1_N8
LL_TIM_BREAK_FILTER_FDIV2_N6
LL_TIM_BREAK_FILTER_FDIV2_N8
LL_TIM_BREAK_FILTER_FDIV32_N5
LL_TIM_BREAK_FILTER_FDIV32_N6
LL_TIM_BREAK_FILTER_FDIV32_N8
LL_TIM_BREAK_FILTER_FDIV4_N6
LL_TIM_BREAK_FILTER_FDIV4_N8
LL_TIM_BREAK_FILTER_FDIV8_N6
LL_TIM_BREAK_FILTER_FDIV8_N8
LL_TIM_BREAK_INPUT_BKIN
LL_TIM_BREAK_INPUT_BKIN2
LL_TIM_BREAK_POLARITY_HIGH
LL_TIM_BREAK_POLARITY_LOW
LL_TIM_CCDMAREQUEST_CC
LL_TIM_CCDMAREQUEST_UPDATE
LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
LL_TIM_CCUPDATESOURCE_COMG_ONLY
LL_TIM_CHANNEL_CH1
LL_TIM_CHANNEL_CH1N
LL_TIM_CHANNEL_CH2
LL_TIM_CHANNEL_CH2N
LL_TIM_CHANNEL_CH3
LL_TIM_CHANNEL_CH3N
LL_TIM_CHANNEL_CH4
LL_TIM_CHANNEL_CH4N
LL_TIM_CHANNEL_CH5
LL_TIM_CHANNEL_CH6
LL_TIM_CLOCKDIVISION_DIV1
LL_TIM_CLOCKDIVISION_DIV2
LL_TIM_CLOCKDIVISION_DIV4
LL_TIM_CLOCKSOURCE_EXT_MODE1
LL_TIM_CLOCKSOURCE_EXT_MODE2
LL_TIM_CLOCKSOURCE_INTERNAL
LL_TIM_COUNTERDIRECTION_DOWN
LL_TIM_COUNTERDIRECTION_UP
LL_TIM_COUNTERMODE_CENTER_DOWN
LL_TIM_COUNTERMODE_CENTER_UP
LL_TIM_COUNTERMODE_CENTER_UP_DOWN
LL_TIM_COUNTERMODE_DOWN
LL_TIM_COUNTERMODE_UP
LL_TIM_DIER_BIE
LL_TIM_DIER_CC1IE
LL_TIM_DIER_CC2IE
LL_TIM_DIER_CC3IE
LL_TIM_DIER_CC4IE
LL_TIM_DIER_COMIE
LL_TIM_DIER_DIRIE
LL_TIM_DIER_IDXIE
LL_TIM_DIER_IERRIE
LL_TIM_DIER_TERRIE
LL_TIM_DIER_TIE
LL_TIM_DIER_UIE
LL_TIM_DMABURST_BASEADDR_AF1
LL_TIM_DMABURST_BASEADDR_AF2
LL_TIM_DMABURST_BASEADDR_ARR
LL_TIM_DMABURST_BASEADDR_BDTR
LL_TIM_DMABURST_BASEADDR_CCER
LL_TIM_DMABURST_BASEADDR_CCMR1
LL_TIM_DMABURST_BASEADDR_CCMR2
LL_TIM_DMABURST_BASEADDR_CCMR3
LL_TIM_DMABURST_BASEADDR_CCR1
LL_TIM_DMABURST_BASEADDR_CCR2
LL_TIM_DMABURST_BASEADDR_CCR3
LL_TIM_DMABURST_BASEADDR_CCR4
LL_TIM_DMABURST_BASEADDR_CCR5
LL_TIM_DMABURST_BASEADDR_CCR6
LL_TIM_DMABURST_BASEADDR_CNT
LL_TIM_DMABURST_BASEADDR_CR1
LL_TIM_DMABURST_BASEADDR_CR2
LL_TIM_DMABURST_BASEADDR_DIER
LL_TIM_DMABURST_BASEADDR_DTR2
LL_TIM_DMABURST_BASEADDR_ECR
LL_TIM_DMABURST_BASEADDR_EGR
LL_TIM_DMABURST_BASEADDR_OR
LL_TIM_DMABURST_BASEADDR_PSC
LL_TIM_DMABURST_BASEADDR_RCR
LL_TIM_DMABURST_BASEADDR_SMCR
LL_TIM_DMABURST_BASEADDR_SR
LL_TIM_DMABURST_BASEADDR_TISEL
LL_TIM_DMABURST_LENGTH_10TRANSFERS
LL_TIM_DMABURST_LENGTH_11TRANSFERS
LL_TIM_DMABURST_LENGTH_12TRANSFERS
LL_TIM_DMABURST_LENGTH_13TRANSFERS
LL_TIM_DMABURST_LENGTH_14TRANSFERS
LL_TIM_DMABURST_LENGTH_15TRANSFERS
LL_TIM_DMABURST_LENGTH_16TRANSFERS
LL_TIM_DMABURST_LENGTH_17TRANSFERS
LL_TIM_DMABURST_LENGTH_18TRANSFERS
LL_TIM_DMABURST_LENGTH_19TRANSFERS
LL_TIM_DMABURST_LENGTH_1TRANSFER
LL_TIM_DMABURST_LENGTH_20TRANSFERS
LL_TIM_DMABURST_LENGTH_21TRANSFERS
LL_TIM_DMABURST_LENGTH_22TRANSFERS
LL_TIM_DMABURST_LENGTH_23TRANSFERS
LL_TIM_DMABURST_LENGTH_24TRANSFERS
LL_TIM_DMABURST_LENGTH_25TRANSFERS
LL_TIM_DMABURST_LENGTH_26TRANSFERS
LL_TIM_DMABURST_LENGTH_2TRANSFERS
LL_TIM_DMABURST_LENGTH_3TRANSFERS
LL_TIM_DMABURST_LENGTH_4TRANSFERS
LL_TIM_DMABURST_LENGTH_5TRANSFERS
LL_TIM_DMABURST_LENGTH_6TRANSFERS
LL_TIM_DMABURST_LENGTH_7TRANSFERS
LL_TIM_DMABURST_LENGTH_8TRANSFERS
LL_TIM_DMABURST_LENGTH_9TRANSFERS
LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
LL_TIM_ENCODERMODE_X1_TI1
LL_TIM_ENCODERMODE_X1_TI2
LL_TIM_ENCODERMODE_X2_TI1
LL_TIM_ENCODERMODE_X2_TI2
LL_TIM_ENCODERMODE_X4_TI12
LL_TIM_ETR_FILTER_FDIV1
LL_TIM_ETR_FILTER_FDIV16_N5
LL_TIM_ETR_FILTER_FDIV16_N6
LL_TIM_ETR_FILTER_FDIV16_N8
LL_TIM_ETR_FILTER_FDIV1_N2
LL_TIM_ETR_FILTER_FDIV1_N4
LL_TIM_ETR_FILTER_FDIV1_N8
LL_TIM_ETR_FILTER_FDIV2_N6
LL_TIM_ETR_FILTER_FDIV2_N8
LL_TIM_ETR_FILTER_FDIV32_N5
LL_TIM_ETR_FILTER_FDIV32_N6
LL_TIM_ETR_FILTER_FDIV32_N8
LL_TIM_ETR_FILTER_FDIV4_N6
LL_TIM_ETR_FILTER_FDIV4_N8
LL_TIM_ETR_FILTER_FDIV8_N6
LL_TIM_ETR_FILTER_FDIV8_N8
LL_TIM_ETR_POLARITY_INVERTED
LL_TIM_ETR_POLARITY_NONINVERTED
LL_TIM_ETR_PRESCALER_DIV1
LL_TIM_ETR_PRESCALER_DIV2
LL_TIM_ETR_PRESCALER_DIV4
LL_TIM_ETR_PRESCALER_DIV8
LL_TIM_GROUPCH5_NONE
LL_TIM_GROUPCH5_OC1REFC
LL_TIM_GROUPCH5_OC2REFC
LL_TIM_GROUPCH5_OC3REFC
LL_TIM_HSE_32_NOT_REQUEST
LL_TIM_HSE_32_REQUEST
LL_TIM_IC_FILTER_FDIV1
LL_TIM_IC_FILTER_FDIV16_N5
LL_TIM_IC_FILTER_FDIV16_N6
LL_TIM_IC_FILTER_FDIV16_N8
LL_TIM_IC_FILTER_FDIV1_N2
LL_TIM_IC_FILTER_FDIV1_N4
LL_TIM_IC_FILTER_FDIV1_N8
LL_TIM_IC_FILTER_FDIV2_N6
LL_TIM_IC_FILTER_FDIV2_N8
LL_TIM_IC_FILTER_FDIV32_N5
LL_TIM_IC_FILTER_FDIV32_N6
LL_TIM_IC_FILTER_FDIV32_N8
LL_TIM_IC_FILTER_FDIV4_N6
LL_TIM_IC_FILTER_FDIV4_N8
LL_TIM_IC_FILTER_FDIV8_N6
LL_TIM_IC_FILTER_FDIV8_N8
LL_TIM_IC_POLARITY_BOTHEDGE
LL_TIM_IC_POLARITY_FALLING
LL_TIM_IC_POLARITY_RISING
LL_TIM_ICPSC_DIV1
LL_TIM_ICPSC_DIV2
LL_TIM_ICPSC_DIV4
LL_TIM_ICPSC_DIV8
LL_TIM_INDEX_ALL
LL_TIM_INDEX_DOWN
LL_TIM_INDEX_FIRST_ONLY
LL_TIM_INDEX_POSITION_DOWN
LL_TIM_INDEX_POSITION_DOWN_DOWN
LL_TIM_INDEX_POSITION_DOWN_UP
LL_TIM_INDEX_POSITION_UP
LL_TIM_INDEX_POSITION_UP_DOWN
LL_TIM_INDEX_POSITION_UP_UP
LL_TIM_INDEX_UP
LL_TIM_INDEX_UP_DOWN
LL_TIM_LOCKLEVEL_1
LL_TIM_LOCKLEVEL_2
LL_TIM_LOCKLEVEL_3
LL_TIM_LOCKLEVEL_OFF
LL_TIM_OCIDLESTATE_HIGH
LL_TIM_OCIDLESTATE_LOW
LL_TIM_OCMODE_ACTIVE
LL_TIM_OCMODE_ASYMMETRIC_PWM1
LL_TIM_OCMODE_ASYMMETRIC_PWM2
LL_TIM_OCMODE_COMBINED_PWM1
LL_TIM_OCMODE_COMBINED_PWM2
LL_TIM_OCMODE_DIRECTION_OUTPUT
LL_TIM_OCMODE_FORCED_ACTIVE
LL_TIM_OCMODE_FORCED_INACTIVE
LL_TIM_OCMODE_FROZEN
LL_TIM_OCMODE_INACTIVE
LL_TIM_OCMODE_PULSE_ON_COMPARE
LL_TIM_OCMODE_PWM1
LL_TIM_OCMODE_PWM2
LL_TIM_OCMODE_RETRIG_OPM1
LL_TIM_OCMODE_RETRIG_OPM2
LL_TIM_OCMODE_TOGGLE
LL_TIM_OCPOLARITY_HIGH
LL_TIM_OCPOLARITY_LOW
LL_TIM_OCREF_CLR_INT_COMP1
LL_TIM_OCREF_CLR_INT_COMP2
LL_TIM_OCREF_CLR_INT_COMP3
LL_TIM_OCREF_CLR_INT_COMP4
LL_TIM_OCREF_CLR_INT_COMP5
LL_TIM_OCREF_CLR_INT_COMP6
LL_TIM_OCREF_CLR_INT_COMP7
LL_TIM_OCREF_CLR_INT_ETR
LL_TIM_OCSTATE_DISABLE
LL_TIM_OCSTATE_ENABLE
LL_TIM_ONEPULSEMODE_REPETITIVE
LL_TIM_ONEPULSEMODE_SINGLE
LL_TIM_OSSI_DISABLE
LL_TIM_OSSI_ENABLE
LL_TIM_OSSR_DISABLE
LL_TIM_OSSR_ENABLE
LL_TIM_PWPRSC_X1
LL_TIM_PWPRSC_X128
LL_TIM_PWPRSC_X16
LL_TIM_PWPRSC_X2
LL_TIM_PWPRSC_X32
LL_TIM_PWPRSC_X4
LL_TIM_PWPRSC_X64
LL_TIM_PWPRSC_X8
LL_TIM_ReadReg
LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
LL_TIM_SLAVEMODE_DISABLED
LL_TIM_SLAVEMODE_GATED
LL_TIM_SLAVEMODE_RESET
LL_TIM_SLAVEMODE_TRIGGER
LL_TIM_SMSPS_INDEX
LL_TIM_SMSPS_TIMUPDATE
LL_TIM_SR_B2IF
LL_TIM_SR_BIF
LL_TIM_SR_CC1IF
LL_TIM_SR_CC1OF
LL_TIM_SR_CC2IF
LL_TIM_SR_CC2OF
LL_TIM_SR_CC3IF
LL_TIM_SR_CC3OF
LL_TIM_SR_CC4IF
LL_TIM_SR_CC4OF
LL_TIM_SR_CC5IF
LL_TIM_SR_CC6IF
LL_TIM_SR_COMIF
LL_TIM_SR_DIRF
LL_TIM_SR_IDXF
LL_TIM_SR_IERRF
LL_TIM_SR_SBIF
LL_TIM_SR_TERRF
LL_TIM_SR_TIF
LL_TIM_SR_UIF
LL_TIM_TIM15_TI1_RMP_COMP1
LL_TIM_TIM15_TI1_RMP_COMP2
LL_TIM_TIM15_TI1_RMP_COMP5
LL_TIM_TIM15_TI1_RMP_COMP7
LL_TIM_TIM15_TI1_RMP_GPIO
LL_TIM_TIM15_TI1_RMP_LSE
LL_TIM_TIM15_TI2_RMP_COMP2
LL_TIM_TIM15_TI2_RMP_COMP3
LL_TIM_TIM15_TI2_RMP_COMP6
LL_TIM_TIM15_TI2_RMP_COMP7
LL_TIM_TIM15_TI2_RMP_GPIO
LL_TIM_TIM16_TI1_RMP_COMP6
LL_TIM_TIM16_TI1_RMP_GPIO
LL_TIM_TIM16_TI1_RMP_HSE_32
LL_TIM_TIM16_TI1_RMP_LSE
LL_TIM_TIM16_TI1_RMP_LSI
LL_TIM_TIM16_TI1_RMP_MCO
LL_TIM_TIM16_TI1_RMP_RTC_WK
LL_TIM_TIM17_TI1_RMP_COMP5
LL_TIM_TIM17_TI1_RMP_GPIO
LL_TIM_TIM17_TI1_RMP_HSE_32
LL_TIM_TIM17_TI1_RMP_LSE
LL_TIM_TIM17_TI1_RMP_LSI
LL_TIM_TIM17_TI1_RMP_MCO
LL_TIM_TIM17_TI1_RMP_RTC_WK
LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
LL_TIM_TIM1_ETRSOURCE_COMP1
LL_TIM_TIM1_ETRSOURCE_COMP2
LL_TIM_TIM1_ETRSOURCE_COMP3
LL_TIM_TIM1_ETRSOURCE_COMP4
LL_TIM_TIM1_ETRSOURCE_COMP5
LL_TIM_TIM1_ETRSOURCE_COMP6
LL_TIM_TIM1_ETRSOURCE_COMP7
LL_TIM_TIM1_ETRSOURCE_GPIO
LL_TIM_TIM1_TI1_RMP_COMP1
LL_TIM_TIM1_TI1_RMP_COMP2
LL_TIM_TIM1_TI1_RMP_COMP3
LL_TIM_TIM1_TI1_RMP_COMP4
LL_TIM_TIM1_TI1_RMP_GPIO
LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1
LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2
LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2
LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3
LL_TIM_TIM20_ETRSOURCE_COMP1
LL_TIM_TIM20_ETRSOURCE_COMP2
LL_TIM_TIM20_ETRSOURCE_COMP3
LL_TIM_TIM20_ETRSOURCE_COMP4
LL_TIM_TIM20_ETRSOURCE_COMP5
LL_TIM_TIM20_ETRSOURCE_COMP6
LL_TIM_TIM20_ETRSOURCE_COMP7
LL_TIM_TIM20_ETRSOURCE_GPIO
LL_TIM_TIM20_TI1_RMP_COMP1
LL_TIM_TIM20_TI1_RMP_COMP2
LL_TIM_TIM20_TI1_RMP_COMP3
LL_TIM_TIM20_TI1_RMP_COMP4
LL_TIM_TIM20_TI1_RMP_GPIO
LL_TIM_TIM2_ETRSOURCE_COMP1
LL_TIM_TIM2_ETRSOURCE_COMP2
LL_TIM_TIM2_ETRSOURCE_COMP3
LL_TIM_TIM2_ETRSOURCE_COMP4
LL_TIM_TIM2_ETRSOURCE_COMP5
LL_TIM_TIM2_ETRSOURCE_COMP6
LL_TIM_TIM2_ETRSOURCE_COMP7
LL_TIM_TIM2_ETRSOURCE_GPIO
LL_TIM_TIM2_ETRSOURCE_LSE
LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
LL_TIM_TIM2_TI1_RMP_COMP1
LL_TIM_TIM2_TI1_RMP_COMP2
LL_TIM_TIM2_TI1_RMP_COMP3
LL_TIM_TIM2_TI1_RMP_COMP4
LL_TIM_TIM2_TI1_RMP_COMP5
LL_TIM_TIM2_TI1_RMP_GPIO
LL_TIM_TIM2_TI2_RMP_COMP1
LL_TIM_TIM2_TI2_RMP_COMP2
LL_TIM_TIM2_TI2_RMP_COMP3
LL_TIM_TIM2_TI2_RMP_COMP4
LL_TIM_TIM2_TI2_RMP_COMP6
LL_TIM_TIM2_TI2_RMP_GPIO
LL_TIM_TIM2_TI3_RMP_COMP4
LL_TIM_TIM2_TI3_RMP_GPIO
LL_TIM_TIM2_TI4_RMP_COMP1
LL_TIM_TIM2_TI4_RMP_COMP2
LL_TIM_TIM2_TI4_RMP_GPIO
LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
LL_TIM_TIM3_ETRSOURCE_COMP1
LL_TIM_TIM3_ETRSOURCE_COMP2
LL_TIM_TIM3_ETRSOURCE_COMP3
LL_TIM_TIM3_ETRSOURCE_COMP4
LL_TIM_TIM3_ETRSOURCE_COMP5
LL_TIM_TIM3_ETRSOURCE_COMP6
LL_TIM_TIM3_ETRSOURCE_COMP7
LL_TIM_TIM3_ETRSOURCE_GPIO
LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
LL_TIM_TIM3_TI1_RMP_COMP1
LL_TIM_TIM3_TI1_RMP_COMP2
LL_TIM_TIM3_TI1_RMP_COMP3
LL_TIM_TIM3_TI1_RMP_COMP4
LL_TIM_TIM3_TI1_RMP_COMP5
LL_TIM_TIM3_TI1_RMP_COMP6
LL_TIM_TIM3_TI1_RMP_COMP7
LL_TIM_TIM3_TI1_RMP_GPIO
LL_TIM_TIM3_TI2_RMP_COMP1
LL_TIM_TIM3_TI2_RMP_COMP2
LL_TIM_TIM3_TI2_RMP_COMP3
LL_TIM_TIM3_TI2_RMP_COMP4
LL_TIM_TIM3_TI2_RMP_COMP5
LL_TIM_TIM3_TI2_RMP_COMP6
LL_TIM_TIM3_TI2_RMP_COMP7
LL_TIM_TIM3_TI2_RMP_GPIO
LL_TIM_TIM3_TI3_RMP_COMP3
LL_TIM_TIM3_TI3_RMP_GPIO
LL_TIM_TIM4_ETRSOURCE_COMP1
LL_TIM_TIM4_ETRSOURCE_COMP2
LL_TIM_TIM4_ETRSOURCE_COMP3
LL_TIM_TIM4_ETRSOURCE_COMP4
LL_TIM_TIM4_ETRSOURCE_COMP5
LL_TIM_TIM4_ETRSOURCE_COMP6
LL_TIM_TIM4_ETRSOURCE_COMP7
LL_TIM_TIM4_ETRSOURCE_GPIO
LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
LL_TIM_TIM4_TI1_RMP_COMP1
LL_TIM_TIM4_TI1_RMP_COMP2
LL_TIM_TIM4_TI1_RMP_COMP3
LL_TIM_TIM4_TI1_RMP_COMP4
LL_TIM_TIM4_TI1_RMP_COMP5
LL_TIM_TIM4_TI1_RMP_COMP6
LL_TIM_TIM4_TI1_RMP_COMP7
LL_TIM_TIM4_TI1_RMP_GPIO
LL_TIM_TIM4_TI2_RMP_COMP1
LL_TIM_TIM4_TI2_RMP_COMP2
LL_TIM_TIM4_TI2_RMP_COMP3
LL_TIM_TIM4_TI2_RMP_COMP4
LL_TIM_TIM4_TI2_RMP_COMP5
LL_TIM_TIM4_TI2_RMP_COMP6
LL_TIM_TIM4_TI2_RMP_COMP7
LL_TIM_TIM4_TI2_RMP_GPIO
LL_TIM_TIM4_TI3_RMP_COMP5
LL_TIM_TIM4_TI3_RMP_GPIO
LL_TIM_TIM4_TI4_RMP_COMP6
LL_TIM_TIM4_TI4_RMP_GPIO
LL_TIM_TIM5_ETRSOURCE_COMP1
LL_TIM_TIM5_ETRSOURCE_COMP2
LL_TIM_TIM5_ETRSOURCE_COMP3
LL_TIM_TIM5_ETRSOURCE_COMP4
LL_TIM_TIM5_ETRSOURCE_COMP5
LL_TIM_TIM5_ETRSOURCE_COMP6
LL_TIM_TIM5_ETRSOURCE_COMP7
LL_TIM_TIM5_ETRSOURCE_GPIO
LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
LL_TIM_TIM5_TI1_RMP_COMP1
LL_TIM_TIM5_TI1_RMP_COMP2
LL_TIM_TIM5_TI1_RMP_COMP3
LL_TIM_TIM5_TI1_RMP_COMP4
LL_TIM_TIM5_TI1_RMP_COMP5
LL_TIM_TIM5_TI1_RMP_COMP6
LL_TIM_TIM5_TI1_RMP_COMP7
LL_TIM_TIM5_TI1_RMP_GPIO
LL_TIM_TIM5_TI1_RMP_LSE
LL_TIM_TIM5_TI1_RMP_LSI
LL_TIM_TIM5_TI1_RMP_RTC_WK
LL_TIM_TIM5_TI2_RMP_COMP1
LL_TIM_TIM5_TI2_RMP_COMP2
LL_TIM_TIM5_TI2_RMP_COMP3
LL_TIM_TIM5_TI2_RMP_COMP4
LL_TIM_TIM5_TI2_RMP_COMP5
LL_TIM_TIM5_TI2_RMP_COMP6
LL_TIM_TIM5_TI2_RMP_COMP7
LL_TIM_TIM5_TI2_RMP_GPIO
LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2
LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3
LL_TIM_TIM8_ETRSOURCE_COMP1
LL_TIM_TIM8_ETRSOURCE_COMP2
LL_TIM_TIM8_ETRSOURCE_COMP3
LL_TIM_TIM8_ETRSOURCE_COMP4
LL_TIM_TIM8_ETRSOURCE_COMP5
LL_TIM_TIM8_ETRSOURCE_COMP6
LL_TIM_TIM8_ETRSOURCE_COMP7
LL_TIM_TIM8_ETRSOURCE_GPIO
LL_TIM_TIM8_TI1_RMP_COMP1
LL_TIM_TIM8_TI1_RMP_COMP2
LL_TIM_TIM8_TI1_RMP_COMP3
LL_TIM_TIM8_TI1_RMP_COMP4
LL_TIM_TIM8_TI1_RMP_GPIO
LL_TIM_TRGO2_CC1F
LL_TIM_TRGO2_ENABLE
LL_TIM_TRGO2_OC1
LL_TIM_TRGO2_OC2
LL_TIM_TRGO2_OC3
LL_TIM_TRGO2_OC4
LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
LL_TIM_TRGO2_OC4_RISING_OC6_RISING
LL_TIM_TRGO2_OC4_RISINGFALLING
LL_TIM_TRGO2_OC5
LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
LL_TIM_TRGO2_OC5_RISING_OC6_RISING
LL_TIM_TRGO2_OC6
LL_TIM_TRGO2_OC6_RISINGFALLING
LL_TIM_TRGO2_RESET
LL_TIM_TRGO2_UPDATE
LL_TIM_TRGO_CC1IF
LL_TIM_TRGO_ENABLE
LL_TIM_TRGO_ENCODERCLK
LL_TIM_TRGO_OC1REF
LL_TIM_TRGO_OC2REF
LL_TIM_TRGO_OC3REF
LL_TIM_TRGO_OC4REF
LL_TIM_TRGO_RESET
LL_TIM_TRGO_UPDATE
LL_TIM_TS_ETRF
LL_TIM_TS_ITR0
LL_TIM_TS_ITR1
LL_TIM_TS_ITR10
LL_TIM_TS_ITR11
LL_TIM_TS_ITR2
LL_TIM_TS_ITR3
LL_TIM_TS_ITR4
LL_TIM_TS_ITR5
LL_TIM_TS_ITR6
LL_TIM_TS_ITR7
LL_TIM_TS_ITR8
LL_TIM_TS_ITR9
LL_TIM_TS_TI1F_ED
LL_TIM_TS_TI1FP1
LL_TIM_TS_TI2FP2
LL_TIM_UPDATESOURCE_COUNTER
LL_TIM_UPDATESOURCE_REGULAR
LL_TIM_WriteReg
OCREF_CLEAR_SELECT_Msk
OCREF_CLEAR_SELECT_Pos
TIM_CALC_DTS
TIM_GET_CHANNEL_INDEX
TIM_POSITION_BRK_SOURCE
TIMx_AF1_BKINP
TIMx_AF1_ETRSEL
LL_TIM_BDTR_Init
LL_TIM_BDTR_StructInit
LL_TIM_CC_DisableChannel
LL_TIM_CC_DisablePreload
LL_TIM_CC_EnableChannel
LL_TIM_CC_EnablePreload
LL_TIM_CC_GetDMAReqTrigger
LL_TIM_CC_IsEnabledChannel
LL_TIM_CC_IsEnabledPreload
LL_TIM_CC_SetDMAReqTrigger
LL_TIM_CC_SetLockLevel
LL_TIM_CC_SetUpdate
LL_TIM_ClearFlag_BRK
LL_TIM_ClearFlag_BRK2
LL_TIM_ClearFlag_CC1
LL_TIM_ClearFlag_CC1OVR
LL_TIM_ClearFlag_CC2
LL_TIM_ClearFlag_CC2OVR
LL_TIM_ClearFlag_CC3
LL_TIM_ClearFlag_CC3OVR
LL_TIM_ClearFlag_CC4
LL_TIM_ClearFlag_CC4OVR
LL_TIM_ClearFlag_CC5
LL_TIM_ClearFlag_CC6
LL_TIM_ClearFlag_COM
LL_TIM_ClearFlag_DIR
LL_TIM_ClearFlag_IDX
LL_TIM_ClearFlag_IERR
LL_TIM_ClearFlag_SYSBRK
LL_TIM_ClearFlag_TERR
LL_TIM_ClearFlag_TRIG
LL_TIM_ClearFlag_UPDATE
LL_TIM_ConfigBRK
LL_TIM_ConfigBRK2
LL_TIM_ConfigDMABurst
LL_TIM_ConfigETR
LL_TIM_ConfigIDX
LL_TIM_DeInit
LL_TIM_DisableAllOutputs
LL_TIM_DisableARRPreload
LL_TIM_DisableAsymmetricalDeadTime
LL_TIM_DisableAutomaticOutput
LL_TIM_DisableBreakInputSource
LL_TIM_DisableBRK
LL_TIM_DisableBRK2
LL_TIM_DisableCounter
LL_TIM_DisableDeadTimePreload
LL_TIM_DisableDithering
LL_TIM_DisableDMAReq_CC1
LL_TIM_DisableDMAReq_CC2
LL_TIM_DisableDMAReq_CC3
LL_TIM_DisableDMAReq_CC4
LL_TIM_DisableDMAReq_COM
LL_TIM_DisableDMAReq_TRIG
LL_TIM_DisableDMAReq_UPDATE
LL_TIM_DisableEncoderIndex
LL_TIM_DisableExternalClock
LL_TIM_DisableFirstIndex
LL_TIM_DisableHSE32
LL_TIM_DisableIT_BRK
LL_TIM_DisableIT_CC1
LL_TIM_DisableIT_CC2
LL_TIM_DisableIT_CC3
LL_TIM_DisableIT_CC4
LL_TIM_DisableIT_COM
LL_TIM_DisableIT_DIR
LL_TIM_DisableIT_IDX
LL_TIM_DisableIT_IERR
LL_TIM_DisableIT_TERR
LL_TIM_DisableIT_TRIG
LL_TIM_DisableIT_UPDATE
LL_TIM_DisableMasterSlaveMode
LL_TIM_DisableSMSPreload
LL_TIM_DisableUIFRemap
LL_TIM_DisableUpdateEvent
LL_TIM_DisarmBRK
LL_TIM_DisarmBRK2
LL_TIM_EnableAllOutputs
LL_TIM_EnableARRPreload
LL_TIM_EnableAsymmetricalDeadTime
LL_TIM_EnableAutomaticOutput
LL_TIM_EnableBreakInputSource
LL_TIM_EnableBRK
LL_TIM_EnableBRK2
LL_TIM_EnableCounter
LL_TIM_EnableDeadTimePreload
LL_TIM_EnableDithering
LL_TIM_EnableDMAReq_CC1
LL_TIM_EnableDMAReq_CC2
LL_TIM_EnableDMAReq_CC3
LL_TIM_EnableDMAReq_CC4
LL_TIM_EnableDMAReq_COM
LL_TIM_EnableDMAReq_TRIG
LL_TIM_EnableDMAReq_UPDATE
LL_TIM_EnableEncoderIndex
LL_TIM_EnableExternalClock
LL_TIM_EnableFirstIndex
LL_TIM_EnableHSE32
LL_TIM_EnableIT_BRK
LL_TIM_EnableIT_CC1
LL_TIM_EnableIT_CC2
LL_TIM_EnableIT_CC3
LL_TIM_EnableIT_CC4
LL_TIM_EnableIT_COM
LL_TIM_EnableIT_DIR
LL_TIM_EnableIT_IDX
LL_TIM_EnableIT_IERR
LL_TIM_EnableIT_TERR
LL_TIM_EnableIT_TRIG
LL_TIM_EnableIT_UPDATE
LL_TIM_EnableMasterSlaveMode
LL_TIM_EnableSMSPreload
LL_TIM_EnableUIFRemap
LL_TIM_EnableUpdateEvent
LL_TIM_ENCODER_Init
LL_TIM_ENCODER_StructInit
LL_TIM_GenerateEvent_BRK
LL_TIM_GenerateEvent_BRK2
LL_TIM_GenerateEvent_CC1
LL_TIM_GenerateEvent_CC2
LL_TIM_GenerateEvent_CC3
LL_TIM_GenerateEvent_CC4
LL_TIM_GenerateEvent_COM
LL_TIM_GenerateEvent_TRIG
LL_TIM_GenerateEvent_UPDATE
LL_TIM_GetAutoReload
LL_TIM_GetClockDivision
LL_TIM_GetCounter
LL_TIM_GetCounterMode
LL_TIM_GetDirection
LL_TIM_GetFallingDeadTime
LL_TIM_GetIndexDirection
LL_TIM_GetIndexPositionning
LL_TIM_GetOnePulseMode
LL_TIM_GetPrescaler
LL_TIM_GetRepetitionCounter
LL_TIM_GetSMSPreloadSource
LL_TIM_GetUpdateSource
LL_TIM_HALLSENSOR_Init
LL_TIM_HALLSENSOR_StructInit
LL_TIM_IC_Config
LL_TIM_IC_DisableXORCombination
LL_TIM_IC_EnableXORCombination
LL_TIM_IC_GetActiveInput
LL_TIM_IC_GetCaptureCH1
LL_TIM_IC_GetCaptureCH2
LL_TIM_IC_GetCaptureCH3
LL_TIM_IC_GetCaptureCH4
LL_TIM_IC_GetFilter
LL_TIM_IC_GetPolarity
LL_TIM_IC_GetPrescaler
LL_TIM_IC_Init
LL_TIM_IC_IsEnabledXORCombination
LL_TIM_IC_SetActiveInput
LL_TIM_IC_SetFilter
LL_TIM_IC_SetPolarity
LL_TIM_IC_SetPrescaler
LL_TIM_IC_StructInit
LL_TIM_Init
LL_TIM_IsActiveFlag_BRK
LL_TIM_IsActiveFlag_BRK2
LL_TIM_IsActiveFlag_CC1
LL_TIM_IsActiveFlag_CC1OVR
LL_TIM_IsActiveFlag_CC2
LL_TIM_IsActiveFlag_CC2OVR
LL_TIM_IsActiveFlag_CC3
LL_TIM_IsActiveFlag_CC3OVR
LL_TIM_IsActiveFlag_CC4
LL_TIM_IsActiveFlag_CC4OVR
LL_TIM_IsActiveFlag_CC5
LL_TIM_IsActiveFlag_CC6
LL_TIM_IsActiveFlag_COM
LL_TIM_IsActiveFlag_DIR
LL_TIM_IsActiveFlag_IDX
LL_TIM_IsActiveFlag_IERR
LL_TIM_IsActiveFlag_SYSBRK
LL_TIM_IsActiveFlag_TERR
LL_TIM_IsActiveFlag_TRIG
LL_TIM_IsActiveFlag_UPDATE
LL_TIM_IsActiveUIFCPY
LL_TIM_IsEnabledAllOutputs
LL_TIM_IsEnabledARRPreload
LL_TIM_IsEnabledAsymmetricalDeadTime
LL_TIM_IsEnabledAutomaticOutput
LL_TIM_IsEnabledCounter
LL_TIM_IsEnabledDeadTimePreload
LL_TIM_IsEnabledDithering
LL_TIM_IsEnabledDMAReq_CC1
LL_TIM_IsEnabledDMAReq_CC2
LL_TIM_IsEnabledDMAReq_CC3
LL_TIM_IsEnabledDMAReq_CC4
LL_TIM_IsEnabledDMAReq_COM
LL_TIM_IsEnabledDMAReq_TRIG
LL_TIM_IsEnabledDMAReq_UPDATE
LL_TIM_IsEnabledEncoderIndex
LL_TIM_IsEnabledExternalClock
LL_TIM_IsEnabledFirstIndex
LL_TIM_IsEnabledHSE32
LL_TIM_IsEnabledIT_BRK
LL_TIM_IsEnabledIT_CC1
LL_TIM_IsEnabledIT_CC2
LL_TIM_IsEnabledIT_CC3
LL_TIM_IsEnabledIT_CC4
LL_TIM_IsEnabledIT_COM
LL_TIM_IsEnabledIT_DIR
LL_TIM_IsEnabledIT_IDX
LL_TIM_IsEnabledIT_IERR
LL_TIM_IsEnabledIT_TERR
LL_TIM_IsEnabledIT_TRIG
LL_TIM_IsEnabledIT_UPDATE
LL_TIM_IsEnabledMasterSlaveMode
LL_TIM_IsEnabledSMSPreload
LL_TIM_IsEnabledUpdateEvent
LL_TIM_OC_ConfigOutput
LL_TIM_OC_DisableClear
LL_TIM_OC_DisableFast
LL_TIM_OC_DisablePreload
LL_TIM_OC_EnableClear
LL_TIM_OC_EnableFast
LL_TIM_OC_EnablePreload
LL_TIM_OC_GetCompareCH1
LL_TIM_OC_GetCompareCH2
LL_TIM_OC_GetCompareCH3
LL_TIM_OC_GetCompareCH4
LL_TIM_OC_GetCompareCH5
LL_TIM_OC_GetCompareCH6
LL_TIM_OC_GetIdleState
LL_TIM_OC_GetMode
LL_TIM_OC_GetPolarity
LL_TIM_OC_GetPulseWidth
LL_TIM_OC_GetPulseWidthPrescaler
LL_TIM_OC_Init
LL_TIM_OC_IsEnabledClear
LL_TIM_OC_IsEnabledFast
LL_TIM_OC_IsEnabledPreload
LL_TIM_OC_SetCompareCH1
LL_TIM_OC_SetCompareCH2
LL_TIM_OC_SetCompareCH3
LL_TIM_OC_SetCompareCH4
LL_TIM_OC_SetCompareCH5
LL_TIM_OC_SetCompareCH6
LL_TIM_OC_SetDeadTime
LL_TIM_OC_SetIdleState
LL_TIM_OC_SetMode
LL_TIM_OC_SetPolarity
LL_TIM_OC_SetPulseWidth
LL_TIM_OC_SetPulseWidthPrescaler
LL_TIM_OC_StructInit
LL_TIM_SetAutoReload
LL_TIM_SetBreakInputSourcePolarity
LL_TIM_SetCH5CombinedChannels
LL_TIM_SetClockDivision
LL_TIM_SetClockSource
LL_TIM_SetCounter
LL_TIM_SetCounterMode
LL_TIM_SetEncoderMode
LL_TIM_SetETRSource
LL_TIM_SetFallingDeadTime
LL_TIM_SetIndexDirection
LL_TIM_SetIndexPositionning
LL_TIM_SetOCRefClearInputSource
LL_TIM_SetOffStates
LL_TIM_SetOnePulseMode
LL_TIM_SetPrescaler
LL_TIM_SetRemap
LL_TIM_SetRepetitionCounter
LL_TIM_SetSlaveMode
LL_TIM_SetSMSPreloadSource
LL_TIM_SetTriggerInput
LL_TIM_SetTriggerOutput
LL_TIM_SetTriggerOutput2
LL_TIM_SetUpdateSource
LL_TIM_StructInit
OFFSET_TAB_CCMRx
SHIFT_TAB_CCxP
SHIFT_TAB_ICxx
SHIFT_TAB_OCxx
SHIFT_TAB_OISx
stm32g4xx_ll_ucpd.c
LL_UCPD_DeInit
LL_UCPD_Init
LL_UCPD_StructInit
stm32g4xx_ll_ucpd.h
LL_UCPD_CCENABLE_CC1CC2
LL_UCPD_CCENABLE_CC2
LL_UCPD_CCENABLE_NONE
LL_UCPD_CCPIN_CC1
LL_UCPD_CCPIN_CC2
LL_UCPD_EOP
LL_UCPD_IMR_FRSEVT
LL_UCPD_IMR_HRSTDISC
LL_UCPD_IMR_HRSTSENT
LL_UCPD_IMR_RXHRSTDET
LL_UCPD_IMR_RXMSGEND
LL_UCPD_IMR_RXNE
LL_UCPD_IMR_RXORDDET
LL_UCPD_IMR_RXOVR
LL_UCPD_IMR_TXIS
LL_UCPD_IMR_TXMSGABT
LL_UCPD_IMR_TXMSGDISC
LL_UCPD_IMR_TXMSGSENT
LL_UCPD_IMR_TXUND
LL_UCPD_IMR_TYPECEVT1
LL_UCPD_IMR_TYPECEVT2
LL_UCPD_ORDERED_SET_CABLE_RESET
LL_UCPD_ORDERED_SET_HARD_RESET
LL_UCPD_ORDERED_SET_SOP
LL_UCPD_ORDERED_SET_SOP1
LL_UCPD_ORDERED_SET_SOP1_DEBUG
LL_UCPD_ORDERED_SET_SOP2
LL_UCPD_ORDERED_SET_SOP2_DEBUG
LL_UCPD_ORDERSET_CABLERST
LL_UCPD_ORDERSET_HARDRST
LL_UCPD_ORDERSET_SOP
LL_UCPD_ORDERSET_SOP1
LL_UCPD_ORDERSET_SOP1_DEBUG
LL_UCPD_ORDERSET_SOP2
LL_UCPD_ORDERSET_SOP2_DEBUG
LL_UCPD_ORDERSET_SOP_EXT1
LL_UCPD_ORDERSET_SOP_EXT2
LL_UCPD_PSC_DIV1
LL_UCPD_PSC_DIV16
LL_UCPD_PSC_DIV2
LL_UCPD_PSC_DIV4
LL_UCPD_PSC_DIV8
LL_UCPD_ReadReg
LL_UCPD_RESISTOR_1_5A
LL_UCPD_RESISTOR_3_0A
LL_UCPD_RESISTOR_DEFAULT
LL_UCPD_RESISTOR_NONE
LL_UCPD_ROLE_SNK
LL_UCPD_ROLE_SRC
LL_UCPD_RST1
LL_UCPD_RST2
LL_UCPD_RXMODE_BIST_TEST_DATA
LL_UCPD_RXMODE_NORMAL
LL_UCPD_RXORDSET_CABLE_RESET
LL_UCPD_RXORDSET_SOP
LL_UCPD_RXORDSET_SOP1
LL_UCPD_RXORDSET_SOP1_DEBUG
LL_UCPD_RXORDSET_SOP2
LL_UCPD_RXORDSET_SOP2_DEBUG
LL_UCPD_RXORDSET_SOPEXT1
LL_UCPD_RXORDSET_SOPEXT2
LL_UCPD_SNK_CC1_VOPEN
LL_UCPD_SNK_CC1_VRP
LL_UCPD_SNK_CC1_VRP15A
LL_UCPD_SNK_CC1_VRP30A
LL_UCPD_SNK_CC2_VOPEN
LL_UCPD_SNK_CC2_VRP
LL_UCPD_SNK_CC2_VRP15A
LL_UCPD_SNK_CC2_VRP30A
LL_UCPD_SR_FRSEVT
LL_UCPD_SR_HRSTDISC
LL_UCPD_SR_HRSTSENT
LL_UCPD_SR_RXERR
LL_UCPD_SR_RXHRSTDET
LL_UCPD_SR_RXMSGEND
LL_UCPD_SR_RXNE
LL_UCPD_SR_RXORDDET
LL_UCPD_SR_RXOVR
LL_UCPD_SR_TXIS
LL_UCPD_SR_TXMSGABT
LL_UCPD_SR_TXMSGDISC
LL_UCPD_SR_TXMSGSENT
LL_UCPD_SR_TXUND
LL_UCPD_SR_TYPEC_VSTATE_CC1
LL_UCPD_SR_TYPEC_VSTATE_CC2
LL_UCPD_SR_TYPECEVT1
LL_UCPD_SR_TYPECEVT2
LL_UCPD_SRC_CC1_OPEN
LL_UCPD_SRC_CC1_VRA
LL_UCPD_SRC_CC1_VRD
LL_UCPD_SRC_CC2_OPEN
LL_UCPD_SRC_CC2_VRA
LL_UCPD_SRC_CC2_VRD
LL_UCPD_SYNC1
LL_UCPD_SYNC2
LL_UCPD_SYNC3
LL_UCPD_TXMODE_BIST_CARRIER2
LL_UCPD_TXMODE_CABLE_RESET
LL_UCPD_TXMODE_NORMAL
LL_UCPD_WriteReg
LL_UCPD_ClearFlag_FRS
LL_UCPD_ClearFlag_RxHRST
LL_UCPD_ClearFlag_RxMsgEnd
LL_UCPD_ClearFlag_RxOrderSet
LL_UCPD_ClearFlag_RxOvr
LL_UCPD_ClearFlag_TxHRSTDISC
LL_UCPD_ClearFlag_TxHRSTSENT
LL_UCPD_ClearFlag_TxMSGABT
LL_UCPD_ClearFlag_TxMSGDISC
LL_UCPD_ClearFlag_TxMSGSENT
LL_UCPD_ClearFlag_TxUND
LL_UCPD_ClearFlag_TypeCEventCC1
LL_UCPD_ClearFlag_TypeCEventCC2
LL_UCPD_DeInit
LL_UCPD_Disable
LL_UCPD_DisableIT_FRS
LL_UCPD_DisableIT_RxHRST
LL_UCPD_DisableIT_RxMsgEnd
LL_UCPD_DisableIT_RxNE
LL_UCPD_DisableIT_RxOrderSet
LL_UCPD_DisableIT_RxOvr
LL_UCPD_DisableIT_TxHRSTDISC
LL_UCPD_DisableIT_TxHRSTSENT
LL_UCPD_DisableIT_TxIS
LL_UCPD_DisableIT_TxMSGABT
LL_UCPD_DisableIT_TxMSGDISC
LL_UCPD_DisableIT_TxMSGSENT
LL_UCPD_DisableIT_TxUND
LL_UCPD_DisableIT_TypeCEventCC1
LL_UCPD_DisableIT_TypeCEventCC2
LL_UCPD_Enable
LL_UCPD_EnableIT_FRS
LL_UCPD_EnableIT_RxHRST
LL_UCPD_EnableIT_RxMsgEnd
LL_UCPD_EnableIT_RxNE
LL_UCPD_EnableIT_RxOrderSet
LL_UCPD_EnableIT_RxOvr
LL_UCPD_EnableIT_TxHRSTDISC
LL_UCPD_EnableIT_TxHRSTSENT
LL_UCPD_EnableIT_TxIS
LL_UCPD_EnableIT_TxMSGABT
LL_UCPD_EnableIT_TxMSGDISC
LL_UCPD_EnableIT_TxMSGSENT
LL_UCPD_EnableIT_TxUND
LL_UCPD_EnableIT_TypeCEventCC1
LL_UCPD_EnableIT_TypeCEventCC2
LL_UCPD_ForceClockDisable
LL_UCPD_ForceClockEnable
LL_UCPD_FRSDetectionDisable
LL_UCPD_FRSDetectionEnable
LL_UCPD_GetRole
LL_UCPD_GetTypeCVstateCC1
LL_UCPD_GetTypeCVstateCC2
LL_UCPD_Init
LL_UCPD_IsActiveFlag_FRS
LL_UCPD_IsActiveFlag_RxErr
LL_UCPD_IsActiveFlag_RxHRST
LL_UCPD_IsActiveFlag_RxMsgEnd
LL_UCPD_IsActiveFlag_RxNE
LL_UCPD_IsActiveFlag_RxOrderSet
LL_UCPD_IsActiveFlag_RxOvr
LL_UCPD_IsActiveFlag_TxHRSTDISC
LL_UCPD_IsActiveFlag_TxHRSTSENT
LL_UCPD_IsActiveFlag_TxIS
LL_UCPD_IsActiveFlag_TxMSGABT
LL_UCPD_IsActiveFlag_TxMSGDISC
LL_UCPD_IsActiveFlag_TxMSGSENT
LL_UCPD_IsActiveFlag_TxUND
LL_UCPD_IsActiveFlag_TypeCEventCC1
LL_UCPD_IsActiveFlag_TypeCEventCC2
LL_UCPD_IsEnabled
LL_UCPD_IsEnabledRxDMA
LL_UCPD_IsEnabledTxDMA
LL_UCPD_IsEnableIT_FRS
LL_UCPD_IsEnableIT_RxHRST
LL_UCPD_IsEnableIT_RxMsgEnd
LL_UCPD_IsEnableIT_RxNE
LL_UCPD_IsEnableIT_RxOrderSet
LL_UCPD_IsEnableIT_RxOvr
LL_UCPD_IsEnableIT_TxHRSTDISC
LL_UCPD_IsEnableIT_TxHRSTSENT
LL_UCPD_IsEnableIT_TxIS
LL_UCPD_IsEnableIT_TxMSGABT
LL_UCPD_IsEnableIT_TxMSGDISC
LL_UCPD_IsEnableIT_TxMSGSENT
LL_UCPD_IsEnableIT_TxUND
LL_UCPD_IsEnableIT_TypeCEventCC1
LL_UCPD_IsEnableIT_TypeCEventCC2
LL_UCPD_ReadData
LL_UCPD_ReadRxOrderSet
LL_UCPD_ReadRxPaySize
LL_UCPD_RxDisable
LL_UCPD_RxDMADisable
LL_UCPD_RxDMAEnable
LL_UCPD_RxEnable
LL_UCPD_RxFilterDisable
LL_UCPD_RxFilterEnable
LL_UCPD_SendHardReset
LL_UCPD_SendMessage
LL_UCPD_SetccEnable
LL_UCPD_SetCCPin
LL_UCPD_SetHbitClockDiv
LL_UCPD_SetIfrGap
LL_UCPD_SetPSCClk
LL_UCPD_SetRpResistor
LL_UCPD_SetRxMode
LL_UCPD_SetRxOrderSet
LL_UCPD_SetRxOrdExt1
LL_UCPD_SetRxOrdExt2
LL_UCPD_SetSNKRole
LL_UCPD_SetSRCRole
LL_UCPD_SetTransWin
LL_UCPD_SetTxMode
LL_UCPD_SignalFRSTX
LL_UCPD_StructInit
LL_UCPD_TxDMADisable
LL_UCPD_TxDMAEnable
LL_UCPD_TypeCDetectionCC1Disable
LL_UCPD_TypeCDetectionCC1Enable
LL_UCPD_TypeCDetectionCC2Disable
LL_UCPD_TypeCDetectionCC2Enable
LL_UCPD_VconnDischargeDisable
LL_UCPD_VconnDischargeEnable
LL_UCPD_WakeUpDisable
LL_UCPD_WakeUpEnable
LL_UCPD_WriteData
LL_UCPD_WriteTxOrderSet
LL_UCPD_WriteTxPaySize
stm32g4xx_ll_usart.c
IS_LL_USART_BAUDRATE
IS_LL_USART_BRR_MIN
IS_LL_USART_CLOCKOUTPUT
IS_LL_USART_CLOCKPHASE
IS_LL_USART_CLOCKPOLARITY
IS_LL_USART_DATAWIDTH
IS_LL_USART_DIRECTION
IS_LL_USART_HWCONTROL
IS_LL_USART_LASTBITCLKOUTPUT
IS_LL_USART_OVERSAMPLING
IS_LL_USART_PARITY
IS_LL_USART_PRESCALER
IS_LL_USART_STOPBITS
USART_DEFAULT_BAUDRATE
LL_USART_ClockInit
LL_USART_ClockStructInit
LL_USART_DeInit
LL_USART_Init
LL_USART_StructInit
stm32g4xx_ll_usart.h
__LL_USART_DIV_SAMPLING8
LL_USART_ADDRESS_DETECT_4B
LL_USART_ADDRESS_DETECT_7B
LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
LL_USART_BINARY_LOGIC_NEGATIVE
LL_USART_BINARY_LOGIC_POSITIVE
LL_USART_BITORDER_LSBFIRST
LL_USART_BITORDER_MSBFIRST
LL_USART_CLOCK_DISABLE
LL_USART_CLOCK_ENABLE
LL_USART_CR1_CMIE
LL_USART_CR1_EOBIE
LL_USART_CR1_IDLEIE
LL_USART_CR1_PEIE
LL_USART_CR1_RTOIE
LL_USART_CR1_RXFFIE
LL_USART_CR1_RXNEIE_RXFNEIE
LL_USART_CR1_TCIE
LL_USART_CR1_TXEIE_TXFNFIE
LL_USART_CR1_TXFEIE
LL_USART_CR2_LBDIE
LL_USART_CR3_CTSIE
LL_USART_CR3_EIE
LL_USART_CR3_RXFTIE
LL_USART_CR3_TCBGTIE
LL_USART_CR3_TXFTIE
LL_USART_CR3_WUFIE
LL_USART_DATAWIDTH_7B
LL_USART_DATAWIDTH_8B
LL_USART_DATAWIDTH_9B
LL_USART_DE_POLARITY_HIGH
LL_USART_DE_POLARITY_LOW
LL_USART_DIRECTION_NONE
LL_USART_DIRECTION_RX
LL_USART_DIRECTION_TX
LL_USART_DIRECTION_TX_RX
LL_USART_DisableIT_RXNE
LL_USART_DisableIT_TXE
LL_USART_DMA_REG_DATA_RECEIVE
LL_USART_DMA_REG_DATA_TRANSMIT
LL_USART_EnableIT_RXNE
LL_USART_EnableIT_TXE
LL_USART_FIFOTHRESHOLD_1_2
LL_USART_FIFOTHRESHOLD_1_4
LL_USART_FIFOTHRESHOLD_1_8
LL_USART_FIFOTHRESHOLD_3_4
LL_USART_FIFOTHRESHOLD_7_8
LL_USART_FIFOTHRESHOLD_8_8
LL_USART_HWCONTROL_CTS
LL_USART_HWCONTROL_NONE
LL_USART_HWCONTROL_RTS
LL_USART_HWCONTROL_RTS_CTS
LL_USART_ICR_CMCF
LL_USART_ICR_CTSCF
LL_USART_ICR_EOBCF
LL_USART_ICR_FECF
LL_USART_ICR_IDLECF
LL_USART_ICR_LBDCF
LL_USART_ICR_NECF
LL_USART_ICR_ORECF
LL_USART_ICR_PECF
LL_USART_ICR_RTOCF
LL_USART_ICR_TCBGTCF
LL_USART_ICR_TCCF
LL_USART_ICR_TXFECF
LL_USART_ICR_UDRCF
LL_USART_ICR_WUCF
LL_USART_IRDA_POWER_LOW
LL_USART_IRDA_POWER_NORMAL
LL_USART_IsActiveFlag_RXNE
LL_USART_IsActiveFlag_TXE
LL_USART_IsEnabledIT_RXNE
LL_USART_IsEnabledIT_TXE
LL_USART_ISR_ABRE
LL_USART_ISR_ABRF
LL_USART_ISR_BUSY
LL_USART_ISR_CMF
LL_USART_ISR_CTS
LL_USART_ISR_CTSIF
LL_USART_ISR_EOBF
LL_USART_ISR_FE
LL_USART_ISR_IDLE
LL_USART_ISR_LBDF
LL_USART_ISR_NE
LL_USART_ISR_ORE
LL_USART_ISR_PE
LL_USART_ISR_REACK
LL_USART_ISR_RTOF
LL_USART_ISR_RWU
LL_USART_ISR_RXFF
LL_USART_ISR_RXFT
LL_USART_ISR_RXNE_RXFNE
LL_USART_ISR_SBKF
LL_USART_ISR_TC
LL_USART_ISR_TCBGT
LL_USART_ISR_TEACK
LL_USART_ISR_TXE_TXFNF
LL_USART_ISR_TXFE
LL_USART_ISR_TXFT
LL_USART_ISR_UDR
LL_USART_ISR_WUF
LL_USART_LASTCLKPULSE_NO_OUTPUT
LL_USART_LASTCLKPULSE_OUTPUT
LL_USART_LINBREAK_DETECT_10B
LL_USART_LINBREAK_DETECT_11B
LL_USART_OVERSAMPLING_16
LL_USART_OVERSAMPLING_8
LL_USART_PARITY_EVEN
LL_USART_PARITY_NONE
LL_USART_PARITY_ODD
LL_USART_PHASE_1EDGE
LL_USART_PHASE_2EDGE
LL_USART_POLARITY_HIGH
LL_USART_POLARITY_LOW
LL_USART_PRESCALER_DIV1
LL_USART_PRESCALER_DIV10
LL_USART_PRESCALER_DIV12
LL_USART_PRESCALER_DIV128
LL_USART_PRESCALER_DIV16
LL_USART_PRESCALER_DIV2
LL_USART_PRESCALER_DIV256
LL_USART_PRESCALER_DIV32
LL_USART_PRESCALER_DIV4
LL_USART_PRESCALER_DIV6
LL_USART_PRESCALER_DIV64
LL_USART_PRESCALER_DIV8
LL_USART_ReadReg
LL_USART_RXPIN_LEVEL_INVERTED
LL_USART_RXPIN_LEVEL_STANDARD
LL_USART_STOPBITS_0_5
LL_USART_STOPBITS_1
LL_USART_STOPBITS_1_5
LL_USART_STOPBITS_2
LL_USART_TXPIN_LEVEL_INVERTED
LL_USART_TXPIN_LEVEL_STANDARD
LL_USART_TXRX_STANDARD
LL_USART_TXRX_SWAPPED
LL_USART_WAKEUP_ADDRESSMARK
LL_USART_WAKEUP_IDLELINE
LL_USART_WAKEUP_ON_ADDRESS
LL_USART_WAKEUP_ON_RXNE
LL_USART_WAKEUP_ON_STARTBIT
LL_USART_WriteReg
LL_USART_ClearFlag_CM
LL_USART_ClearFlag_EOB
LL_USART_ClearFlag_FE
LL_USART_ClearFlag_IDLE
LL_USART_ClearFlag_LBD
LL_USART_ClearFlag_nCTS
LL_USART_ClearFlag_NE
LL_USART_ClearFlag_ORE
LL_USART_ClearFlag_PE
LL_USART_ClearFlag_RTO
LL_USART_ClearFlag_TC
LL_USART_ClearFlag_TCBGT
LL_USART_ClearFlag_TXFE
LL_USART_ClearFlag_UDR
LL_USART_ClearFlag_WKUP
LL_USART_ClockInit
LL_USART_ClockStructInit
LL_USART_ConfigAsyncMode
LL_USART_ConfigCharacter
LL_USART_ConfigClock
LL_USART_ConfigFIFOsThreshold
LL_USART_ConfigHalfDuplexMode
LL_USART_ConfigIrdaMode
LL_USART_ConfigLINMode
LL_USART_ConfigMultiProcessMode
LL_USART_ConfigNodeAddress
LL_USART_ConfigSmartcardMode
LL_USART_ConfigSyncMode
LL_USART_DeInit
LL_USART_Disable
LL_USART_DisableAutoBaudRate
LL_USART_DisableCTSHWFlowCtrl
LL_USART_DisableDEMode
LL_USART_DisableDirectionRx
LL_USART_DisableDirectionTx
LL_USART_DisableDMADeactOnRxErr
LL_USART_DisableDMAReq_RX
LL_USART_DisableDMAReq_TX
LL_USART_DisableFIFO
LL_USART_DisableHalfDuplex
LL_USART_DisableInStopMode
LL_USART_DisableIrda
LL_USART_DisableIT_CM
LL_USART_DisableIT_CTS
LL_USART_DisableIT_EOB
LL_USART_DisableIT_ERROR
LL_USART_DisableIT_IDLE
LL_USART_DisableIT_LBD
LL_USART_DisableIT_PE
LL_USART_DisableIT_RTO
LL_USART_DisableIT_RXFF
LL_USART_DisableIT_RXFT
LL_USART_DisableIT_RXNE_RXFNE
LL_USART_DisableIT_TC
LL_USART_DisableIT_TCBGT
LL_USART_DisableIT_TXE_TXFNF
LL_USART_DisableIT_TXFE
LL_USART_DisableIT_TXFT
LL_USART_DisableIT_WKUP
LL_USART_DisableLIN
LL_USART_DisableMuteMode
LL_USART_DisableOneBitSamp
LL_USART_DisableOverrunDetect
LL_USART_DisableRTSHWFlowCtrl
LL_USART_DisableRxTimeout
LL_USART_DisableSCLKOutput
LL_USART_DisableSmartcard
LL_USART_DisableSmartcardNACK
LL_USART_DisableSPISlave
LL_USART_DisableSPISlaveSelect
LL_USART_DMA_GetRegAddr
LL_USART_Enable
LL_USART_EnableAutoBaudRate
LL_USART_EnableCTSHWFlowCtrl
LL_USART_EnableDEMode
LL_USART_EnableDirectionRx
LL_USART_EnableDirectionTx
LL_USART_EnableDMADeactOnRxErr
LL_USART_EnableDMAReq_RX
LL_USART_EnableDMAReq_TX
LL_USART_EnableFIFO
LL_USART_EnableHalfDuplex
LL_USART_EnableInStopMode
LL_USART_EnableIrda
LL_USART_EnableIT_CM
LL_USART_EnableIT_CTS
LL_USART_EnableIT_EOB
LL_USART_EnableIT_ERROR
LL_USART_EnableIT_IDLE
LL_USART_EnableIT_LBD
LL_USART_EnableIT_PE
LL_USART_EnableIT_RTO
LL_USART_EnableIT_RXFF
LL_USART_EnableIT_RXFT
LL_USART_EnableIT_RXNE_RXFNE
LL_USART_EnableIT_TC
LL_USART_EnableIT_TCBGT
LL_USART_EnableIT_TXE_TXFNF
LL_USART_EnableIT_TXFE
LL_USART_EnableIT_TXFT
LL_USART_EnableIT_WKUP
LL_USART_EnableLIN
LL_USART_EnableMuteMode
LL_USART_EnableOneBitSamp
LL_USART_EnableOverrunDetect
LL_USART_EnableRTSHWFlowCtrl
LL_USART_EnableRxTimeout
LL_USART_EnableSCLKOutput
LL_USART_EnableSmartcard
LL_USART_EnableSmartcardNACK
LL_USART_EnableSPISlave
LL_USART_EnableSPISlaveSelect
LL_USART_GetAutoBaudRateMode
LL_USART_GetBaudRate
LL_USART_GetBinaryDataLogic
LL_USART_GetBlockLength
LL_USART_GetClockPhase
LL_USART_GetClockPolarity
LL_USART_GetDataWidth
LL_USART_GetDEAssertionTime
LL_USART_GetDEDeassertionTime
LL_USART_GetDESignalPolarity
LL_USART_GetHWFlowCtrl
LL_USART_GetIrdaPowerMode
LL_USART_GetIrdaPrescaler
LL_USART_GetLastClkPulseOutput
LL_USART_GetLINBrkDetectionLen
LL_USART_GetNodeAddress
LL_USART_GetNodeAddressLen
LL_USART_GetOverSampling
LL_USART_GetParity
LL_USART_GetPrescaler
LL_USART_GetRXFIFOThreshold
LL_USART_GetRXPinLevel
LL_USART_GetRxTimeout
LL_USART_GetSmartcardAutoRetryCount
LL_USART_GetSmartcardGuardTime
LL_USART_GetSmartcardPrescaler
LL_USART_GetStopBitsLength
LL_USART_GetTransferBitOrder
LL_USART_GetTransferDirection
LL_USART_GetTXFIFOThreshold
LL_USART_GetTXPinLevel
LL_USART_GetTXRXSwap
LL_USART_GetWakeUpMethod
LL_USART_GetWKUPType
LL_USART_Init
LL_USART_IsActiveFlag_ABR
LL_USART_IsActiveFlag_ABRE
LL_USART_IsActiveFlag_BUSY
LL_USART_IsActiveFlag_CM
LL_USART_IsActiveFlag_CTS
LL_USART_IsActiveFlag_EOB
LL_USART_IsActiveFlag_FE
LL_USART_IsActiveFlag_IDLE
LL_USART_IsActiveFlag_LBD
LL_USART_IsActiveFlag_nCTS
LL_USART_IsActiveFlag_NE
LL_USART_IsActiveFlag_ORE
LL_USART_IsActiveFlag_PE
LL_USART_IsActiveFlag_REACK
LL_USART_IsActiveFlag_RTO
LL_USART_IsActiveFlag_RWU
LL_USART_IsActiveFlag_RXFF
LL_USART_IsActiveFlag_RXFT
LL_USART_IsActiveFlag_RXNE_RXFNE
LL_USART_IsActiveFlag_SBK
LL_USART_IsActiveFlag_TC
LL_USART_IsActiveFlag_TCBGT
LL_USART_IsActiveFlag_TEACK
LL_USART_IsActiveFlag_TXE_TXFNF
LL_USART_IsActiveFlag_TXFE
LL_USART_IsActiveFlag_TXFT
LL_USART_IsActiveFlag_UDR
LL_USART_IsActiveFlag_WKUP
LL_USART_IsEnabled
LL_USART_IsEnabledAutoBaud
LL_USART_IsEnabledDEMode
LL_USART_IsEnabledDMADeactOnRxErr
LL_USART_IsEnabledDMAReq_RX
LL_USART_IsEnabledDMAReq_TX
LL_USART_IsEnabledFIFO
LL_USART_IsEnabledHalfDuplex
LL_USART_IsEnabledInStopMode
LL_USART_IsEnabledIrda
LL_USART_IsEnabledIT_CM
LL_USART_IsEnabledIT_CTS
LL_USART_IsEnabledIT_EOB
LL_USART_IsEnabledIT_ERROR
LL_USART_IsEnabledIT_IDLE
LL_USART_IsEnabledIT_LBD
LL_USART_IsEnabledIT_PE
LL_USART_IsEnabledIT_RTO
LL_USART_IsEnabledIT_RXFF
LL_USART_IsEnabledIT_RXFT
LL_USART_IsEnabledIT_RXNE_RXFNE
LL_USART_IsEnabledIT_TC
LL_USART_IsEnabledIT_TCBGT
LL_USART_IsEnabledIT_TXE_TXFNF
LL_USART_IsEnabledIT_TXFE
LL_USART_IsEnabledIT_TXFT
LL_USART_IsEnabledIT_WKUP
LL_USART_IsEnabledLIN
LL_USART_IsEnabledMuteMode
LL_USART_IsEnabledOneBitSamp
LL_USART_IsEnabledOverrunDetect
LL_USART_IsEnabledRxTimeout
LL_USART_IsEnabledSCLKOutput
LL_USART_IsEnabledSmartcard
LL_USART_IsEnabledSmartcardNACK
LL_USART_IsEnabledSPISlave
LL_USART_IsEnabledSPISlaveSelect
LL_USART_ReceiveData8
LL_USART_ReceiveData9
LL_USART_RequestAutoBaudRate
LL_USART_RequestBreakSending
LL_USART_RequestEnterMuteMode
LL_USART_RequestRxDataFlush
LL_USART_RequestTxDataFlush
LL_USART_SetAutoBaudRateMode
LL_USART_SetBaudRate
LL_USART_SetBinaryDataLogic
LL_USART_SetBlockLength
LL_USART_SetClockPhase
LL_USART_SetClockPolarity
LL_USART_SetDataWidth
LL_USART_SetDEAssertionTime
LL_USART_SetDEDeassertionTime
LL_USART_SetDESignalPolarity
LL_USART_SetHWFlowCtrl
LL_USART_SetIrdaPowerMode
LL_USART_SetIrdaPrescaler
LL_USART_SetLastClkPulseOutput
LL_USART_SetLINBrkDetectionLen
LL_USART_SetOverSampling
LL_USART_SetParity
LL_USART_SetPrescaler
LL_USART_SetRXFIFOThreshold
LL_USART_SetRXPinLevel
LL_USART_SetRxTimeout
LL_USART_SetSmartcardAutoRetryCount
LL_USART_SetSmartcardGuardTime
LL_USART_SetSmartcardPrescaler
LL_USART_SetStopBitsLength
LL_USART_SetTransferBitOrder
LL_USART_SetTransferDirection
LL_USART_SetTXFIFOThreshold
LL_USART_SetTXPinLevel
LL_USART_SetTXRXSwap
LL_USART_SetWakeUpMethod
LL_USART_SetWKUPType
LL_USART_StructInit
LL_USART_TransmitData8
LL_USART_TransmitData9
USART_PRESCALER_TAB
stm32g4xx_ll_utils.c
IS_LL_UTILS_APB1_DIV
IS_LL_UTILS_APB2_DIV
IS_LL_UTILS_HSE_BYPASS
IS_LL_UTILS_HSE_FREQUENCY
IS_LL_UTILS_PLL_FREQUENCY
IS_LL_UTILS_PLLM_VALUE
IS_LL_UTILS_PLLN_VALUE
IS_LL_UTILS_PLLR_VALUE
IS_LL_UTILS_PLLVCO_INPUT
IS_LL_UTILS_PLLVCO_OUTPUT
IS_LL_UTILS_SYSCLK_DIV
UTILS_HSE_FREQUENCY_MAX
UTILS_HSE_FREQUENCY_MIN
UTILS_MAX_FREQUENCY_SCALE1
UTILS_MAX_FREQUENCY_SCALE2
UTILS_PLLVCO_INPUT_MAX
UTILS_PLLVCO_INPUT_MIN
UTILS_PLLVCO_OUTPUT_MAX
UTILS_PLLVCO_OUTPUT_MIN
UTILS_SCALE1_LATENCY1_BOOST_FREQ
UTILS_SCALE1_LATENCY1_FREQ
UTILS_SCALE1_LATENCY2_BOOST_FREQ
UTILS_SCALE1_LATENCY2_FREQ
UTILS_SCALE1_LATENCY3_BOOST_FREQ
UTILS_SCALE1_LATENCY3_FREQ
UTILS_SCALE1_LATENCY4_BOOST_FREQ
UTILS_SCALE1_LATENCY4_FREQ
UTILS_SCALE1_LATENCY5_BOOST_FREQ
UTILS_SCALE1_LATENCY5_FREQ
UTILS_SCALE2_LATENCY1_FREQ
UTILS_SCALE2_LATENCY2_FREQ
UTILS_SCALE2_LATENCY3_FREQ
LL_Init1msTick
LL_mDelay
LL_PLL_ConfigSystemClock_HSE
LL_PLL_ConfigSystemClock_HSI
LL_SetFlashLatency
LL_SetSystemCoreClock
UTILS_EnablePLLAndSwitchSystem
UTILS_GetPLLOutputFrequency
UTILS_PLL_IsBusy
stm32g4xx_ll_utils.h
LL_MAX_DELAY
LL_UTILS_HSEBYPASS_OFF
LL_UTILS_HSEBYPASS_ON
LL_UTILS_PACKAGETYPE_LQFP100
LL_UTILS_PACKAGETYPE_LQFP100_LQFP80
LL_UTILS_PACKAGETYPE_LQFP128
LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121
LL_UTILS_PACKAGETYPE_LQFP32
LL_UTILS_PACKAGETYPE_LQFP48
LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
LL_UTILS_PACKAGETYPE_LQFP64
LL_UTILS_PACKAGETYPE_TFBGA100
LL_UTILS_PACKAGETYPE_UFBGA100
LL_UTILS_PACKAGETYPE_UFBGA64
LL_UTILS_PACKAGETYPE_UFQFPN32
LL_UTILS_PACKAGETYPE_UFQFPN48
LL_UTILS_PACKAGETYPE_WLCSP49
LL_UTILS_PACKAGETYPE_WLCSP64
LL_UTILS_PACKAGETYPE_WLCSP81
PACKAGE_BASE_ADDRESS
UID_BASE_ADDRESS
LL_GetFlashSize
LL_GetPackageType
LL_GetUID_Word0
LL_GetUID_Word1
LL_GetUID_Word2
LL_Init1msTick
LL_InitTick
LL_mDelay
LL_PLL_ConfigSystemClock_HSE
LL_PLL_ConfigSystemClock_HSI
LL_SetFlashLatency
LL_SetSystemCoreClock
stm32g4xx_ll_wwdg.h
LL_WWDG_PRESCALER_1
LL_WWDG_PRESCALER_128
LL_WWDG_PRESCALER_16
LL_WWDG_PRESCALER_2
LL_WWDG_PRESCALER_32
LL_WWDG_PRESCALER_4
LL_WWDG_PRESCALER_64
LL_WWDG_PRESCALER_8
LL_WWDG_ReadReg
LL_WWDG_WriteReg
LL_WWDG_ClearFlag_EWKUP
LL_WWDG_Enable
LL_WWDG_EnableIT_EWKUP
LL_WWDG_GetCounter
LL_WWDG_GetPrescaler
LL_WWDG_GetWindow
LL_WWDG_IsActiveFlag_EWKUP
LL_WWDG_IsEnabled
LL_WWDG_IsEnabledIT_EWKUP
LL_WWDG_SetCounter
LL_WWDG_SetPrescaler
LL_WWDG_SetWindow
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Directories
stm32g4xx_hal_adc.h
stm32g4xx_hal_adc_ex.h
stm32g4xx_hal_comp.h
stm32g4xx_hal_cordic.h
stm32g4xx_hal_cortex.h
stm32g4xx_hal_crc.h
stm32g4xx_hal_crc_ex.h
stm32g4xx_hal_cryp.h
stm32g4xx_hal_cryp_ex.h
stm32g4xx_hal_dac.h
stm32g4xx_hal_dac_ex.h
stm32g4xx_hal_dma.h
stm32g4xx_hal_dma_ex.h
stm32g4xx_hal_exti.h
stm32g4xx_hal_fdcan.h
stm32g4xx_hal_flash.h
stm32g4xx_hal_flash_ex.h
stm32g4xx_hal_flash_ramfunc.h
stm32g4xx_hal_fmac.h
stm32g4xx_hal_gpio.h
stm32g4xx_hal_gpio_ex.h
stm32g4xx_hal_hrtim.h
stm32g4xx_hal_i2c.h
stm32g4xx_hal_i2c_ex.h
stm32g4xx_hal_i2s.h
stm32g4xx_hal_irda.h
stm32g4xx_hal_irda_ex.h
stm32g4xx_hal_iwdg.h
stm32g4xx_hal_lptim.h
stm32g4xx_hal_nand.h
stm32g4xx_hal_nor.h
stm32g4xx_hal_opamp.h
stm32g4xx_hal_opamp_ex.h
stm32g4xx_hal_pcd.h
stm32g4xx_hal_pcd_ex.h
stm32g4xx_hal_pwr.h
stm32g4xx_hal_pwr_ex.h
stm32g4xx_hal_qspi.h
stm32g4xx_hal_rcc.h
stm32g4xx_hal_rcc_ex.h
stm32g4xx_hal_rng.h
stm32g4xx_hal_rtc.h
stm32g4xx_hal_rtc_ex.h
stm32g4xx_hal_sai.h
stm32g4xx_hal_sai_ex.h
stm32g4xx_hal_smartcard.h
stm32g4xx_hal_smartcard_ex.h
stm32g4xx_hal_smbus.h
stm32g4xx_hal_smbus_ex.h
stm32g4xx_hal_spi.h
stm32g4xx_hal_spi_ex.h
stm32g4xx_hal_sram.h
stm32g4xx_hal_tim.h
stm32g4xx_hal_tim_ex.h
stm32g4xx_hal_uart.h
stm32g4xx_hal_uart_ex.h
stm32g4xx_hal_usart.h
stm32g4xx_hal_usart_ex.h
stm32g4xx_hal_wwdg.h
stm32g4xx_ll_adc.h
stm32g4xx_ll_bus.h
stm32g4xx_ll_comp.h
stm32g4xx_ll_cordic.h
stm32g4xx_ll_cortex.h
stm32g4xx_ll_crc.h
stm32g4xx_ll_crs.h
stm32g4xx_ll_dac.h
stm32g4xx_ll_dma.h
stm32g4xx_ll_dmamux.h
stm32g4xx_ll_exti.h
stm32g4xx_ll_fmac.h
stm32g4xx_ll_gpio.h
stm32g4xx_ll_hrtim.h
stm32g4xx_ll_i2c.h
stm32g4xx_ll_iwdg.h
stm32g4xx_ll_lptim.h
stm32g4xx_ll_lpuart.h
stm32g4xx_ll_opamp.h
stm32g4xx_ll_pwr.h
stm32g4xx_ll_rcc.h
stm32g4xx_ll_rng.h
stm32g4xx_ll_rtc.h
stm32g4xx_ll_spi.h
stm32g4xx_ll_system.h
stm32g4xx_ll_tim.h
stm32g4xx_ll_ucpd.h
stm32g4xx_ll_usart.h
stm32g4xx_ll_utils.h
stm32g4xx_ll_wwdg.h
Src
stm32g4xx_hal_adc.c
stm32g4xx_hal_adc_ex.c
stm32g4xx_hal_comp.c
stm32g4xx_hal_cordic.c
stm32g4xx_hal_cortex.c
stm32g4xx_hal_crc.c
stm32g4xx_hal_crc_ex.c
stm32g4xx_hal_cryp.c
stm32g4xx_hal_cryp_ex.c
stm32g4xx_hal_dac.c
stm32g4xx_hal_dac_ex.c
stm32g4xx_hal_dma.c
stm32g4xx_hal_dma_ex.c
stm32g4xx_hal_exti.c
stm32g4xx_hal_fdcan.c
stm32g4xx_hal_flash.c
stm32g4xx_hal_flash_ex.c
stm32g4xx_hal_flash_ramfunc.c
stm32g4xx_hal_fmac.c
stm32g4xx_hal_gpio.c
stm32g4xx_hal_hrtim.c
stm32g4xx_hal_i2c.c
stm32g4xx_hal_i2c_ex.c
stm32g4xx_hal_i2s.c
stm32g4xx_hal_irda.c
stm32g4xx_hal_iwdg.c
stm32g4xx_hal_lptim.c
stm32g4xx_hal_nand.c
stm32g4xx_hal_nor.c
stm32g4xx_hal_opamp.c
stm32g4xx_hal_opamp_ex.c
stm32g4xx_hal_pcd.c
stm32g4xx_hal_pcd_ex.c
stm32g4xx_hal_pwr.c
stm32g4xx_hal_pwr_ex.c
stm32g4xx_hal_qspi.c
stm32g4xx_hal_rcc.c
stm32g4xx_hal_rcc_ex.c
stm32g4xx_hal_rng.c
stm32g4xx_hal_rtc.c
stm32g4xx_hal_rtc_ex.c
stm32g4xx_hal_sai.c
stm32g4xx_hal_sai_ex.c
stm32g4xx_hal_smartcard.c
stm32g4xx_hal_smartcard_ex.c
stm32g4xx_hal_smbus.c
stm32g4xx_hal_smbus_ex.c
stm32g4xx_hal_spi.c
stm32g4xx_hal_spi_ex.c
stm32g4xx_hal_sram.c
stm32g4xx_hal_tim.c
stm32g4xx_hal_tim_ex.c
stm32g4xx_hal_uart.c
stm32g4xx_hal_uart_ex.c
stm32g4xx_hal_usart.c
stm32g4xx_hal_usart_ex.c
stm32g4xx_hal_wwdg.c
stm32g4xx_ll_adc.c
stm32g4xx_ll_comp.c
stm32g4xx_ll_cordic.c
stm32g4xx_ll_crc.c
stm32g4xx_ll_crs.c
stm32g4xx_ll_dac.c
stm32g4xx_ll_dma.c
stm32g4xx_ll_exti.c
stm32g4xx_ll_fmac.c
stm32g4xx_ll_gpio.c
stm32g4xx_ll_hrtim.c
stm32g4xx_ll_i2c.c
stm32g4xx_ll_lptim.c
stm32g4xx_ll_lpuart.c
stm32g4xx_ll_opamp.c
stm32g4xx_ll_pwr.c
stm32g4xx_ll_rcc.c
stm32g4xx_ll_rng.c
stm32g4xx_ll_rtc.c
stm32g4xx_ll_spi.c
stm32g4xx_ll_tim.c
stm32g4xx_ll_ucpd.c
stm32g4xx_ll_usart.c
stm32g4xx_ll_utils.c