stm32g4xx_ll_rcc.h 文件参考

RCC LL模块的头文件。 更多...

#include "stm32g4xx.h"

查看此文件的源代码。

数据结构
struct	LL_RCC_ClocksTypeDef
	RCC时钟频率结构体。 更多...
宏定义
#define	RCC_OFFSET_CCIPR   0U
#define	RCC_OFFSET_CCIPR2   0x14U
#define	LL_RCC_CICR_LSIRDYC   RCC_CICR_LSIRDYC
#define	LL_RCC_CICR_LSERDYC   RCC_CICR_LSERDYC
#define	LL_RCC_CICR_HSIRDYC   RCC_CICR_HSIRDYC
#define	LL_RCC_CICR_HSERDYC   RCC_CICR_HSERDYC
#define	LL_RCC_CICR_PLLRDYC   RCC_CICR_PLLRDYC
#define	LL_RCC_CICR_HSI48RDYC   RCC_CICR_HSI48RDYC
#define	LL_RCC_CICR_LSECSSC   RCC_CICR_LSECSSC
#define	LL_RCC_CICR_CSSC   RCC_CICR_CSSC
#define	LL_RCC_CIFR_LSIRDYF   RCC_CIFR_LSIRDYF
#define	LL_RCC_CIFR_LSERDYF   RCC_CIFR_LSERDYF
#define	LL_RCC_CIFR_HSIRDYF   RCC_CIFR_HSIRDYF
#define	LL_RCC_CIFR_HSERDYF   RCC_CIFR_HSERDYF
#define	LL_RCC_CIFR_PLLRDYF   RCC_CIFR_PLLRDYF
#define	LL_RCC_CIFR_HSI48RDYF   RCC_CIFR_HSI48RDYF
#define	LL_RCC_CIFR_LSECSSF   RCC_CIFR_LSECSSF
#define	LL_RCC_CIFR_CSSF   RCC_CIFR_CSSF
#define	LL_RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF
#define	LL_RCC_CSR_OBLRSTF   RCC_CSR_OBLRSTF
#define	LL_RCC_CSR_PINRSTF   RCC_CSR_PINRSTF
#define	LL_RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF
#define	LL_RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF
#define	LL_RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF
#define	LL_RCC_CSR_BORRSTF   RCC_CSR_BORRSTF
#define	LL_RCC_CIER_LSIRDYIE   RCC_CIER_LSIRDYIE
#define	LL_RCC_CIER_LSERDYIE   RCC_CIER_LSERDYIE
#define	LL_RCC_CIER_HSIRDYIE   RCC_CIER_HSIRDYIE
#define	LL_RCC_CIER_HSERDYIE   RCC_CIER_HSERDYIE
#define	LL_RCC_CIER_PLLRDYIE   RCC_CIER_PLLRDYIE
#define	LL_RCC_CIER_HSI48RDYIE   RCC_CIER_HSI48RDYIE
#define	LL_RCC_CIER_LSECSSIE   RCC_CIER_LSECSSIE
#define	LL_RCC_LSEDRIVE_LOW   0x00000000U
#define	LL_RCC_LSEDRIVE_MEDIUMLOW   RCC_BDCR_LSEDRV_0
#define	LL_RCC_LSEDRIVE_MEDIUMHIGH   RCC_BDCR_LSEDRV_1
#define	LL_RCC_LSEDRIVE_HIGH   RCC_BDCR_LSEDRV
#define	LL_RCC_LSCO_CLKSOURCE_LSI   0x00000000U
#define	LL_RCC_LSCO_CLKSOURCE_LSE   RCC_BDCR_LSCOSEL
#define	LL_RCC_SYS_CLKSOURCE_HSI   RCC_CFGR_SW_HSI
#define	LL_RCC_SYS_CLKSOURCE_HSE   RCC_CFGR_SW_HSE
#define	LL_RCC_SYS_CLKSOURCE_PLL   RCC_CFGR_SW_PLL
#define	LL_RCC_SYS_CLKSOURCE_STATUS_HSI   RCC_CFGR_SWS_HSI
#define	LL_RCC_SYS_CLKSOURCE_STATUS_HSE   RCC_CFGR_SWS_HSE
#define	LL_RCC_SYS_CLKSOURCE_STATUS_PLL   RCC_CFGR_SWS_PLL
#define	LL_RCC_SYSCLK_DIV_1   RCC_CFGR_HPRE_DIV1
#define	LL_RCC_SYSCLK_DIV_2   RCC_CFGR_HPRE_DIV2
#define	LL_RCC_SYSCLK_DIV_4   RCC_CFGR_HPRE_DIV4
#define	LL_RCC_SYSCLK_DIV_8   RCC_CFGR_HPRE_DIV8
#define	LL_RCC_SYSCLK_DIV_16   RCC_CFGR_HPRE_DIV16
#define	LL_RCC_SYSCLK_DIV_64   RCC_CFGR_HPRE_DIV64
#define	LL_RCC_SYSCLK_DIV_128   RCC_CFGR_HPRE_DIV128
#define	LL_RCC_SYSCLK_DIV_256   RCC_CFGR_HPRE_DIV256
#define	LL_RCC_SYSCLK_DIV_512   RCC_CFGR_HPRE_DIV512
#define	LL_RCC_APB1_DIV_1   RCC_CFGR_PPRE1_DIV1
#define	LL_RCC_APB1_DIV_2   RCC_CFGR_PPRE1_DIV2
#define	LL_RCC_APB1_DIV_4   RCC_CFGR_PPRE1_DIV4
#define	LL_RCC_APB1_DIV_8   RCC_CFGR_PPRE1_DIV8
#define	LL_RCC_APB1_DIV_16   RCC_CFGR_PPRE1_DIV16
#define	LL_RCC_APB2_DIV_1   RCC_CFGR_PPRE2_DIV1
#define