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STM32G474xx HAL 用户手册
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TIM HAL 模块的头文件。 更多...
数据结构 | |
| struct | TIM_Base_InitTypeDef |
| TIM 时基配置结构体定义。 更多... | |
| struct | TIM_OC_InitTypeDef |
| TIM 输出比较配置结构体定义。 更多... | |
| struct | TIM_OnePulse_InitTypeDef |
| TIM 单脉冲模式配置结构体定义。 更多... | |
| struct | TIM_IC_InitTypeDef |
| TIM 输入捕获配置结构体定义。 更多... | |
| struct | TIM_Encoder_InitTypeDef |
| TIM 编码器配置结构体定义。 更多... | |
| struct | TIM_ClockConfigTypeDef |
| 时钟配置句柄结构体定义。 更多... | |
| struct | TIM_ClearInputConfigTypeDef |
| TIM 清除输入配置句柄结构体定义。 更多... | |
| struct | TIM_MasterConfigTypeDef |
| TIM 主配置结构体定义。 更多... | |
| struct | TIM_SlaveConfigTypeDef |
| TIM 从配置结构体定义。 更多... | |
| struct | TIM_BreakDeadTimeConfigTypeDef |
| TIM 刹车输入和死区时间配置结构体定义。 更多... | |
| struct | __TIM_HandleTypeDef |
| TIM 时基句柄结构体定义。 更多... | |
定义 | |
| #define | TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU |
| #define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U |
| #define | TIM_CLEARINPUTSOURCE_COMP1 0x00000000U |
| #define | TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 |
| #define | TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 |
| #define | TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) |
| #define | TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 |
| #define | TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) |
| #define | TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) |
| #define | TIM_DMABASE_CR1 0x00000000U |
| #define | TIM_DMABASE_CR2 0x00000001U |
| #define | TIM_DMABASE_SMCR 0x00000002U |
| #define | TIM_DMABASE_DIER 0x00000003U |
| #define | TIM_DMABASE_SR 0x00000004U |
| #define | TIM_DMABASE_EGR 0x00000005U |
| #define | TIM_DMABASE_CCMR1 0x00000006U |
| #define | TIM_DMABASE_CCMR2 0x00000007U |
| #define | TIM_DMABASE_CCER 0x00000008U |
| #define | TIM_DMABASE_CNT 0x00000009U |
| #define | TIM_DMABASE_PSC 0x0000000AU |
| #define | TIM_DMABASE_ARR 0x0000000BU |
| #define | TIM_DMABASE_RCR 0x0000000CU |
| #define | TIM_DMABASE_CCR1 0x0000000DU |
| #define | TIM_DMABASE_CCR2 0x0000000EU |
| #define | TIM_DMABASE_CCR3 0x0000000FU |
| #define | TIM_DMABASE_CCR4 0x00000010U |
| #define | TIM_DMABASE_BDTR 0x00000011U |
| #define | TIM_DMABASE_CCR5 0x00000012U |
| #define | TIM_DMABASE_CCR6 0x00000013U |
| #define | TIM_DMABASE_CCMR3 0x00000014U |
| #define | TIM_DMABASE_DTR2 0x00000015U |
| #define | TIM_DMABASE_ECR 0x00000016U |
| #define | TIM_DMABASE_TISEL 0x00000017U |
| #define | TIM_DMABASE_AF1 0x00000018U |
| #define | TIM_DMABASE_AF2 0x00000019U |
| #define | TIM_DMABASE_OR 0x0000001AU |
| #define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
| #define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
| #define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
| #define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
| #define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
| #define | TIM_EVENTSOURCE_COM TIM_EGR_COMG |
| #define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
| #define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
| #define | TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G |
| #define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U |
| #define | TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P |
| #define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) |
| #define | TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP |
| #define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U |
| #define | TIM_ETRPRESCALER_DIV1 0x00000000U |
| #define | TIM_ETRPRESCALER_DIV2 &# |