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STM32G474xx HAL用户手册
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宏定义 | |
| #define | TIM_TIM1_ETR_GPIO 0x00000000U |
| #define | TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 |
| #define | TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) |
| #define | TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM2_ETR_GPIO 0x00000000U |
| #define | TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 |
| #define | TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_GPIO 0x00000000U |
| #define | TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 |
| #define | TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) |
| #define | TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM4_ETR_GPIO 0x00000000U |
| #define | TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 |
| #define | TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM5_ETR_GPIO 0x00000000U |
| #define | TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) |
| #define | TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 |
| #define | TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM8_ETR_GPIO 0x00000000U |
| #define | TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 |
| #define | TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 |
| #define | TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) |
| #define | TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 |
| #define | TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0 |