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STM32G474xx HAL 用户手册
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QSPI HAL 模块的头文件。 更多...
#include "stm32g4xx_hal_def.h"数据结构 | |
| struct | QSPI_InitTypeDef |
| QSPI 初始化结构体定义。 更多... | |
| struct | __QSPI_HandleTypeDef |
| QSPI 句柄结构体定义。 更多... | |
| struct | QSPI_CommandTypeDef |
| QSPI 命令结构体定义。 更多... | |
| struct | QSPI_AutoPollingTypeDef |
| QSPI 自动轮询模式配置结构体定义。 更多... | |
| struct | QSPI_MemoryMappedTypeDef |
| QSPI 内存映射模式配置结构体定义。 更多... | |
宏定义 | |
| #define | HAL_QSPI_ERROR_NONE 0x00000000U |
| #define | HAL_QSPI_ERROR_TIMEOUT 0x00000001U |
| #define | HAL_QSPI_ERROR_TRANSFER 0x00000002U |
| #define | HAL_QSPI_ERROR_DMA 0x00000004U |
| #define | HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U |
| #define | HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U |
| #define | QSPI_SAMPLE_SHIFTING_NONE 0x00000000U |
| #define | QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) |
| #define | QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U |
| #define | QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) |
| #define | QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) |
| #define | QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) |
| #define | QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) |
| #define | QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) |
| #define | QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) |
| #define | QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) |
| #define | QSPI_CLOCK_MODE_0 0x00000000U |
| #define | QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) |
| #define | QSPI_FLASH_ID_1 0x00000000U |
| #define | QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) |
| #define | QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) |
| #define | QSPI_DUALFLASH_DISABLE 0x00000000U |
| #define | QSPI_ADDRESS_8_BITS 0x00000000U |
| #define | QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) |
| #define | QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) |
| #define | QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) |
| #define | QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U |
| #define | QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) |
| #define | QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) |
| #define | QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) |
| #define | QSPI_INSTRUCTION_NONE 0x00000000U |
| #define | QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) |
| #define | QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) |
| #define | QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) |
| #define | QSPI_ADDRESS_NONE 0x00000000U |
| #define | QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) |
| #define | QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) |
| #define | QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) |
| #define | QSPI_ALTERNATE_BYTES_NONE 0x00000000U |
| #define | QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) |
| #define | QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) |
| #define | QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) |
| #define | QSPI_DATA_NONE 0x00000000U |
| #define | QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) |
| #define | QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) |
| #define | |