|
STM32G474xx HAL用户手册
|
宏定义 | |
| #define | TIM_TIM1_TI1_GPIO 0x00000000U |
| #define | TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 |
| #define | TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 |
| #define | TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2 |
| #define | TIM_TIM2_TI1_GPIO 0x00000000U |
| #define | TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 |
| #define | TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 |
| #define | TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2 |
| #define | TIM_TIM2_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM2_TI2_GPIO 0x00000000U |
| #define | TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 |
| #define | TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 |
| #define | TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2 |
| #define | TIM_TIM2_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM2_TI3_GPIO 0x00000000U |
| #define | TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0 |
| #define | TIM_TIM2_TI4_GPIO 0x00000000U |
| #define | TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 |
| #define | TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 |
| #define | TIM_TIM3_TI1_GPIO 0x00000000U |
| #define | TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 |
| #define | TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 |
| #define | TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2 |
| #define | TIM_TIM3_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM3_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) |
| #define | TIM_TIM3_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM3_TI2_GPIO 0x00000000U |
| #define | TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 |
| #define | TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 |
| #define | TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2 |
| #define | TIM_TIM3_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM3_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) |
| #define | TIM_TIM3_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM3_TI3_GPIO 0x00000000U |
| #define | TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0 |
| #define | TIM_TIM4_TI1_GPIO 0x00000000U |
| #define | TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 |
| #define | TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 |
| #define | TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2 |
| #define | TIM_TIM4_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM4_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) |
| #define | TIM_TIM4_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM4_TI2_GPIO 0x00000000U |
| #define | TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 |
| #define | TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 |
| #define | TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2 |
| #define | TIM_TIM4_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM4_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) |
| #define | TIM_TIM4_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) |
| #define | TIM_TIM4_TI3_GPIO 0x00000000U |
| #define | TIM_TIM4_TI3_COMP5 TIM_TISEL_TI3SEL_0 |
| #define | TIM_TIM4_TI4_GPIO 0x00000000U |
| #define | TIM_TIM4_TI4_COMP6 TIM_TISEL_TI4SEL_0 |
| #define | TIM_TIM5_TI1_GPIO 0x00000000U |
| #define | TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 |
| #define | TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 |
| #define | TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 |
| #define | TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) |
| #define | TIM_TIM5_TI1_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) |
| #define | TIM |