|
STM32G474xx HAL用户手册
|
UCPD LL模块的头文件。 更多...
#include "stm32g4xx.h"数据结构 | |
| struct | LL_UCPD_InitTypeDef |
| UCPD初始化结构体定义。 更多... | |
宏定义 | |
| #define | LL_UCPD_SR_TXIS UCPD_SR_TXIS |
| #define | LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC |
| #define | LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT |
| #define | LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT |
| #define | LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC |
| #define | LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT |
| #define | LL_UCPD_SR_TXUND UCPD_SR_TXUND |
| #define | LL_UCPD_SR_RXNE UCPD_SR_RXNE |
| #define | LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET |
| #define | LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET |
| #define | LL_UCPD_SR_RXOVR UCPD_SR_RXOVR |
| #define | LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND |
| #define | LL_UCPD_SR_RXERR UCPD_SR_RXERR |
| #define | LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 |
| #define | LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 |
| #define | LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 |
| #define | LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 |
| #define | LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT |
| #define | LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE |
| #define | LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE |
| #define | LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE |
| #define | LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE |
| #define | LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE |
| #define | LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE |
| #define | LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE |
| #define | LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE |
| #define | LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE |
| #define | LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE |
| #define | LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE |
| #define | LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE |
| #define | LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE |
| #define | LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE |
| #define | LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE |
| #define | LL_UCPD_SYNC1 0x18u |
| #define | LL_UCPD_SYNC2 0x11u |
| #define | LL_UCPD_SYNC3 0x06u |
| #define | LL_UCPD_RST1 0x07u |
| #define | LL_UCPD_RST2 0x19u |
| #define | LL_UCPD_EOP 0x0Du |
| #define | LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) |
| #define | LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) |
| #define | LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) |
| #define | LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) |
| #define | LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) |
| #define | LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) |
| #define | LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) |
| #define | LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE |
| #define | LL_UCPD_ROLE_SRC 0x0U |
| #define | LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 |
| #define | LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 |
| #define | LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE |
| #define | LL_UCPD_RESISTOR_NONE 0x0U |
| #define | LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 |
| #define | LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 |
| #define | LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 |
| #define | |