宏定义
#define	FDCAN_TIMEOUT_VALUE 10U
#define	FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL \| FDCAN_IR_TEFF \| FDCAN_IR_TEFN)
#define	FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L \| FDCAN_IR_RF0F \| FDCAN_IR_RF0N)
#define	FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L \| FDCAN_IR_RF1F \| FDCAN_IR_RF1N)
#define	FDCAN_ERROR_MASK (FDCAN_IR_ELO \| FDCAN_IR_WDI \| FDCAN_IR_PEA \| FDCAN_IR_PED \| FDCAN_IR_ARA)
#define	FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP \| FDCAN_IR_EW \| FDCAN_IR_BO)
#define	FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define	FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define	FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define	FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define	FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define	FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define	FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define	FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define	FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define	FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define	FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define	FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define	FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define	FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define	SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define	SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define	SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define	SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define	SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define	SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define	SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define	SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define	SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define	SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define	SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define	SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define	SRAMCAN_FLSSA
#define	SRAMCAN_FLESA
#define	SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define	SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define	SRAMCAN_TEFSA
#define	SRAMCAN_TFQSA
#define	SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */