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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_utils.c 00004 * @author MCD Application Team 00005 * @brief UTILS LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Includes ------------------------------------------------------------------*/ 00020 #include "stm32g4xx_ll_utils.h" 00021 #include "stm32g4xx_ll_rcc.h" 00022 #include "stm32g4xx_ll_system.h" 00023 #include "stm32g4xx_ll_pwr.h" 00024 #ifdef USE_FULL_ASSERT 00025 #include "stm32_assert.h" 00026 #else 00027 #define assert_param(expr) ((void)0U) 00028 #endif /* USE_FULL_ASSERT */ 00029 00030 /** @addtogroup STM32G4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup UTILS_LL 00035 * @{ 00036 */ 00037 00038 /* Private types -------------------------------------------------------------*/ 00039 /* Private variables ---------------------------------------------------------*/ 00040 /* Private constants ---------------------------------------------------------*/ 00041 /** @addtogroup UTILS_LL_Private_Constants 00042 * @{ 00043 */ 00044 #define UTILS_MAX_FREQUENCY_SCALE1 170000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ 00045 #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ 00046 00047 /* Defines used for PLL range */ 00048 #define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */ 00049 #define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */ 00050 #define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */ 00051 #define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */ 00052 00053 /* Defines used for HSE range */ 00054 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ 00055 #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ 00056 00057 /* Defines used for FLASH latency according to HCLK Frequency */ 00058 #define UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ 00059 #define UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ 00060 #define UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ 00061 #define UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ 00062 #define UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ 00063 00064 #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 normal mode */ 00065 #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 normal mode */ 00066 #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 normal mode */ 00067 #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 normal mode */ 00068 #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 normal mode */ 00069 00070 #define UTILS_SCALE2_LATENCY1_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ 00071 #define UTILS_SCALE2_LATENCY2_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ 00072 #define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ 00073 /** 00074 * @} 00075 */ 00076 00077 /* Private macros ------------------------------------------------------------*/ 00078 /** @addtogroup UTILS_LL_Private_Macros 00079 * @{ 00080 */ 00081 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ 00082 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ 00083 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ 00084 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ 00085 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ 00086 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ 00087 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ 00088 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ 00089 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) 00090 00091 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ 00092 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ 00093 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ 00094 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ 00095 || ((__VALUE__) == LL_RCC_APB1_DIV_16)) 00096 00097 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ 00098 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ 00099 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ 00100 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ 00101 || ((__VALUE__) == LL_RCC_APB2_DIV_16)) 00102 00103 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \ 00104 || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \ 00105 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ 00106 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ 00107 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ 00108 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ 00109 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ 00110 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ 00111 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ 00112 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ 00113 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ 00114 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ 00115 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ 00116 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ 00117 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ 00118 || ((__VALUE__) == LL_RCC_PLLM_DIV_16)) 00119 00120 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 00121 00122 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ 00123 || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ 00124 || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \ 00125 || ((__VALUE__) == LL_RCC_PLLR_DIV_8)) 00126 00127 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) 00128 00129 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) 00130 00131 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ 00132 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) 00133 00134 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ 00135 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) 00136 00137 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) 00138 <