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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_rcc.c 00004 * @author MCD Application Team 00005 * @brief RCC LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 ****************************************************************************** 00016 */ 00017 #if defined(USE_FULL_LL_DRIVER) 00018 00019 /* Includes ------------------------------------------------------------------*/ 00020 #include "stm32g4xx_ll_rcc.h" 00021 #ifdef USE_FULL_ASSERT 00022 #include "stm32_assert.h" 00023 #else 00024 #define assert_param(expr) ((void)0U) 00025 #endif 00026 /** @addtogroup STM32G4xx_LL_Driver 00027 * @{ 00028 */ 00029 00030 /** @addtogroup RCC_LL 00031 * @{ 00032 */ 00033 00034 /* Private types -------------------------------------------------------------*/ 00035 /* Private variables ---------------------------------------------------------*/ 00036 /* Private constants ---------------------------------------------------------*/ 00037 /* Private macros ------------------------------------------------------------*/ 00038 /** @addtogroup RCC_LL_Private_Macros 00039 * @{ 00040 */ 00041 #if defined(RCC_CCIPR_USART3SEL) 00042 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ 00043 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ 00044 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) 00045 #else 00046 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ 00047 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) 00048 #endif /* RCC_CCIPR_USART3SEL*/ 00049 00050 #if defined(RCC_ CCIPR_UART5SEL) 00051 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ 00052 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) 00053 #elif defined(RCC_CC IPR_UART4SEL) 00054 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE) 00055 #endif /* RCC_CC IPR_UART5SEL*/ 00056 00057 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) 00058 00059 #if defined(RCC_ CCIPR2_I2C4SEL) 00060 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00061 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ 00062 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ 00063 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) 00064 #elif defined(RCC_CC IPR_I2C3SEL) 00065 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00066 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ 00067 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) 00068 #else 00069 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00070 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) 00071 00072 #endif /* RCC_CC IPR2_I2C4SEL */ 00073 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) 00074 00075 #if defined(SAI1) 00076 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) 00077 #endif /* SAI1 */ 00078 00079 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE) 00080 00081 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) 00082 00083 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) 00084 00085 #if defined(ADC345_COMMON) 00086 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \ 00087 || ((__VALUE__) == LL_RCC_ADC345_CLKSOURCE)) 00088 #else 00089 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE)) 00090 #endif /* ADC345_COMMON */ 00091 00092 #if defined(QUADSPI) 00093 #define IS_LL_RCC_QUADSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_QUADSPI_CLKSOURCE)) 00094 #endif /* QUADSPI */ 00095 00096 #if defined(FDCAN1) 00097 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)) 00098 #endif /* FDCAN1 */ 00099 00100 /** 00101 * @} 00102 */ 00103 00104 /* Private function prototypes -----------------------------------------------*/ 00105 /** @defgroup RCC_LL_Private_Functions RCC Private functions 00106 * @{ 00107 */ 00108 static uint32_t RCC_GetSystemClockFreq(void); 00109 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); 00110 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); 00111 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); 00112 static uint32_t RCC_PLL_GetFreqDomain_SYS(void); 00113 static uint32_t RCC_PLL_GetFreqDomain_ADC(void); 00114 static uint32_t RCC_PLL_GetFreqDomain_48M(void); 00115 /** 00116 * @} 00117 */ 00118 00119 00120 /* Exported functions --------------------------------------------------------*/ 00121 /** @addtogroup RCC_LL_Exported_Functions 00122 * @{ 00123 */ 00124 00125 /** @addtogroup RCC_LL_EF_Init 00126 * @{ 00127 */ 00128 00129 /** 00130 * @brief Reset the RCC clock configuration to the default reset state. 00131 * @note The default reset state of the clock configuration is given below: 00132 * - HSI ON and used as system clock source 00133 * - HSE and PLL OFF 00134 * - AHB, APB1 and APB2 prescaler set to 1. 00135 * - CSS, MCO OFF 00136 * - All interrupts disabled 00137 * @note This function doesn't modify the configuration of the 00138 * - Peripheral clocks 00139 * - LSI, LSE and RTC clocks 00140 * @retval An ErrorStatus enumeration value: 00141 * - SUCCESS: RCC registers are de-initialized 00142 * - ERROR: not applicable 00143 */ 00144 ErrorStatus LL_RCC_DeInit(void) 00145 { 00146 uint32_t vl_mask; 00147 00148 /* Set HSION bit and wait for HSI READY bit */ 00149 LL_RCC_HSI_Enable(); 00150 while (LL_RCC_HSI_IsReady() == 0U)