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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef __STM32G4xx_HAL_DMA_H 00021 #define __STM32G4xx_HAL_DMA_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32g4xx_hal_def.h" 00029 00030 /** @addtogroup STM32G4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup DMA 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup DMA_Exported_Types DMA Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief DMA Configuration Structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Request; /*!< Specifies the request selected for the specified channel. 00049 This parameter can be a value of @ref DMA_request */ 00050 00051 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00052 from memory to memory or from peripheral to memory. 00053 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00054 00055 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00056 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00057 00058 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00059 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00060 00061 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00062 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00063 00064 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00065 This parameter can be a value of @ref DMA_Memory_data_size */ 00066 00067 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 00068 This parameter can be a value of @ref DMA_mode 00069 @note The circular buffer mode cannot be used if the memory-to-memory 00070 data transfer is configured on the selected Channel */ 00071 00072 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 00073 This parameter can be a value of @ref DMA_Priority_level */ 00074 } DMA_InitTypeDef; 00075 00076 /** 00077 * @brief HAL DMA State structures definition 00078 */ 00079 typedef enum 00080 { 00081 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00082 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00083 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00084 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 00085 } HAL_DMA_StateTypeDef; 00086 00087 /** 00088 * @brief HAL DMA Error Code structure definition 00089 */ 00090 typedef enum 00091 { 00092 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00093 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00094 } HAL_DMA_LevelCompleteTypeDef; 00095 00096 00097 /** 00098 * @brief HAL DMA Callback ID structure definition 00099 */ 00100 typedef enum 00101 { 00102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 00104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 00105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 00106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 00107 00108 } HAL_DMA_CallbackIDTypeDef; 00109 00110 /** 00111 * @brief DMA handle Structure definition 00112 */ 00113 typedef struct __DMA_HandleTypeDef 00114 { 00115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 00116 00117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00117 00118 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00119 00120 00121 00121 /*!< DMA communication parameters */ 00122 00123 00123 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00124 00125 00125 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00126 00127 00127 void *Parent; /*!< Parent object state */ 00128 00129 00129 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 00130 00131 00131 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 00132 00133 00133 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 00134 00135 00135 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 00136 00137 00137 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00138 00139 00139 DMA_TypeDef *