stm32g4xx_ll_hrtim.h

转到此文件的文档。

/**
  ******************************************************************************
  * @file    stm32g4xx_ll_hrtim.h
  * @author  MCD 应用团队
  * @brief   HRTIM 低级驱动模块的头文件。
  ******************************************************************************
  * @attention
  *
  * 版权所有 (c) 2019 STMicroelectronics。
  * 保留所有权利。
  *
  * 本软件根据可在本软件组件根目录的 LICENSE 文件中找到的条款进行许可。
  * 如果本软件没有附带 LICENSE 文件，则按“原样”提供。
  *
  ******************************************************************************
  */


/* 定义以防止递归包含 -------------------------------------*/
#ifndef STM32G4xx_LL_HRTIM_H
#define STM32G4xx_LL_HRTIM_H

#ifdef __cplusplus
extern "C" {
#endif

/* 包含 ------------------------------------------------------------------*/
#include "stm32g4xx.h"

/** @addtogroup STM32G4xx_LL_Driver
  * @{
  */

#if defined (HRTIM1)

/** @defgroup HRTIM_LL HRTIM
  * @{
  */

/* 私有类型 -------------------------------------------------------------*/
/* 私有变量 ---------------------------------------------------------*/
/** @defgroup HRTIM_LL_Private_Variables HRTIM 私有变量
  * @{
  */
static const uint16_t REG_OFFSET_TAB_TIMER[] =
{
  0x00U,   /* 0: 主定时器  */
  0x80U,   /* 1: 定时器 A */
  0x100U,  /* 2: 定时器 B */
  0x180U,  /* 3: 定时器 C */
  0x200U,  /* 4: 定时器 D */
  0x280U,  /* 5: 定时器 E */
  0x300U,  /* 6: 定时器 F */
};

static const uint8_t REG_OFFSET_TAB_ADCER[] =
{
  0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_ADC1R */
  0x04U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_ADC2R */
  0x08U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_ADC3R */
  0x0CU,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_ADC4R */
  0x3CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCER */
  0x3CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCER */
  0x3CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCER */
  0x3CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCER */
  0x3CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCER */
  0x3CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
};

static const uint8_t REG_OFFSET_TAB_ADCUR[] =
{
  0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_CR1   */
  0x00U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_CR1   */
  0x00U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_CR1   */
  0x00U,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_CR1   */
  0x7CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCUR */
  0x7CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCUR */
  0x7CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCUR */
  0x7CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCUR */
  0x7CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCUR */
  0x7CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
};

static const uint8_t REG_SHIFT_TAB_ADCER[] =
{
  0,   /* LL_HRTIM_ADCTRIG_1  */
  0,   /* LL_HRTIM_ADCTRIG_2  */
  0,   /* LL_HRTIM_ADCTRIG_3  */
  0,   /* LL_HRTIM_ADCTRIG_4  */
  0,   /* LL_HRTIM_ADCTRIG_5  */
  5,   /* LL_HRTIM_ADCTRIG_6  */
  10,  /* LL_HRTIM_ADCTRIG_7  */
  16,  /* LL_HRTIM_ADCTRIG_8  */
  21,  /* LL_HRTIM_ADCTRIG_9  */
  26   /* LL_HRTIM_ADCTRIG_10 */
};

static const uint8_t REG_SHIFT_TAB_ADCUR[] =
{
  16,   /* LL_HRTIM_ADCTRIG_1  */
  19,   /* LL_HRTIM_ADCTRIG_2  */
  22,   /* LL_HRTIM_ADCTRIG_3  */
  25,   /* LL_HRTIM_ADCTRIG_4  */
  0,    /* LL_HRTIM_ADCTRIG_5  */
  4,    /* LL_HRTIM_ADCTRIG_6  */
  8,    /* LL_HRTIM_ADCTRIG_7  */
  12,   /* LL_HRTIM_ADCTRIG_8  */
  16,   /* LL_HRTIM_ADCTRIG_9  */
  20    /* LL_HRTIM_ADCTRIG_10 */
};

static const uint32_t REG_MASK_TAB_ADCER[] =
{
  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_1  */
  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_2  */
  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_3  */
  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_4  */
  0x0000001FU,   /* LL_HRTIM_ADCTRIG_5  */
  0x000003E0U,   /* LL_HRTIM_ADCTRIG_6  */
  0x00007C00U,   /* LL_HRTIM_ADCTRIG_7  */
  0x001F0000U,   /* LL_HRTIM_ADCTRIG_8  */
  0x03E00000U,   /* LL_HRTIM_ADCTRIG_9  */
  0x7C000000U    /* LL_HRTIM_ADCTRIG_10 */
};

static const uint32_t REG_MASK_TAB_ADCUR[] =
{
  0x00070000U,   /* LL_HRTIM_ADCTRIG_1  */
  0x00380000U,   /* LL_HRTIM_ADCTRIG_2  */
  0x01C00000U,   /* LL_HRTIM_ADCTRIG_3  */
  0x0E000000U,   /* LL_HRTIM_ADCTRIG_4  */
  0x00000007U,   /* LL_HRTIM_ADCTRIG_5  */
  0x00000070U,   /* LL_HRTIM_ADCTRIG_6  */
  0x00000700U,   /* LL_HRTIM_ADCTRIG_7  */
  0x00007000U,   /* LL_HRTIM_ADCTRIG_8  */
  0x00070000U,   /* LL_HRTIM_ADCTRIG_9  */
  0x00700000U    /* LL_HRTIM_ADCTRIG_10 */
};

static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
{
  0U,    /* 0: HRTIM_ADC1R  */
  6U,    /* 1: HRTIM_ADC2R  */
  12U,   /* 2: HRTIM_ADC3R  */
  18U,   /* 3: HRTIM_ADC4R  */
  24U,   /* 4: HRTIM_ADC5R  */
  32U,   /* 5: HRTIM_ADC6R  */
  38U,   /* 6: HRTIM_ADC7R  */
  44U,   /* 7: HRTIM_ADC8R  */
  50U,   /* 8: HRTIM_ADC9R  */
  56U    /* 9: HRTIM_ADC10R */
};

static const uint16_t REG_OFFSET_TAB_SETxR[] =
{
  0x00U,   /* 0: TA1 */
  0x08U,   /* 1: TA2 */
  0x80U,   /* 2: TB1 */
  0x88U,   /* 3: TB2 */
  0x100U,  /* 4: TC1 */
  0x108U,  /* 5: TC2 */
  0x180U,  /* 6: TD1 */
  0x188U,  /* 7: TD2 */
  0x200U,  /* 8: TE1 */
  0x208U,  /* 9: TE2 */
  0x280U,  /* 10: TF1 */
  0x288U   /* 11: TF2 */
};

static const uint16_t REG_OFFSET_TAB_OUTxR[] =
{
  0x00U,   /*  0: TA1 */
  0x00U,   /*  1: TA2 */
  0x80U,   /*  2: TB1 */
  0x80U,   /*  3: TB2 */
  0x100U,  /*  4: TC1 */
  0x100U,  /*  5: TC2 */
  0x180U,  /*  6: TD1 */
  0x180U,  /*  7: TD2 */
  0x200U,  /*  8: TE1 */
  0x200U,  /*  9: TE2 */
  0x280U,  /* 10: TF1 */
  0x280U   /* 11: TF2 */
};

static const uint8_t REG_OFFSET_TAB_EECR[] =
{
  0x00U, /* LL_HRTIM_EVENT_1 */
  0x00U, /* LL_HRTIM_EVENT_2 */
  0x00U, /* LL_HRTIM_EVENT_3 */
  0x00U, /* LL_HRTIM_EVENT_4 */
  0x00U, /* LL_HRTIM_EVENT_5 */
  0x04U, /* LL_HRTIM_EVENT_6 */
  0x04U, /* LL_HRTIM_EVENT_7 */
  0x04U, /* LL_HRTIM_EVENT_8 */
  0x04U, /* LL_HRTIM_EVENT_9 */
  0x04U  /* LL_HRTIM_EVENT_10 */