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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32G4xx_LL_DAC_H 00021 #define STM32G4xx_LL_DAC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32g4xx.h" 00029 00030 /** @addtogroup STM32G4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) 00035 00036 /** @defgroup DAC_LL DAC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 00043 /* Private constants ---------------------------------------------------------*/ 00044 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00045 * @{ 00046 */ 00047 00048 /* Internal masks for DAC channels definition */ 00049 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00050 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR */ 00051 /* - channel bits position into register SWTRIG */ 00052 /* - channel bits position into register SWTRIGB */ 00053 /* - channel register offset of data holding register DHRx */ 00054 /* - channel register offset of data output register DORx */ 00055 /* - channel register offset of sample-and-hold sample time register SHSRx */ 00056 /* - channel register offset of sawtooth register STRx */ 00057 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers 00058 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */ 00059 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers 00060 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */ 00061 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00062 00063 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 00064 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 00065 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00066 00067 #define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/ 00068 #define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/ 00069 #define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2) 00070 00071 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ 00072 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus 00073 DHR12Rx channel 1 (shifted left of 20 bits) */ 00074 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus 00075 DHR12Rx channel 1 (shifted left of 24 bits) */ 00076 00077 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus 00078 DHR12Rx channel 1 (shifted left of 28 bits) */ 00079 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus 00080 DHR12Rx channel 1 (shifted left of 20 bits) */ 00081 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus 00082 DHR12Rx channel 1 (shifted left of 24 bits) */ 00083 00084 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL 00085 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL 00086 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL 00087 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ 00088 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00089 00090 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ 00091 00092 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus 00093 DORx channel 2 (shifted left of 5 bits) */ 00094 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00095 00096 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ 00097 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus 00098 SHSRx channel 2 (shifted left of 6 bits) */ 00099 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) 00100 00101 #define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */ 00102 #define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus 00103 STRx channel 2 (shifted left of 7 bits) */ 00104 #define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET) 00105 00106 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, 00107 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 00108 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted 00109 to position 0 */ 00110 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted 00111 to position 0 */ 00112 #define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted 00113 to position 0 */ 00114 00115 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx 00116 channel 1 or 2 versus DHR12Rx channel 1 00117 (shifted left of 28 bits) */ 00118 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx 00119 channel 1 or 2 versus DHR12Rx channel 1 00120 (shifted left of 20 bits) */ 00121 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx 00122 channel 1 or 2 versus DHR12Rx channel 1 00123 (shifted left of 24 bits) */ 00124 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx 00125 channel 1 or 2 versus DORx channel 1 00126 (shifted left of 5 bits) */ 00127 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx 00128 channel 1 or 2 versus SHSRx channel 1 00129 (shifted left of 6 bits) */ 00130 #define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx 00131 channel 1 or 2 versus STRx channel 1 00132 (shifted left of 7 bits) */ 00133 00134 /* DAC registers bits positions */