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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 @verbatim 00018 ============================================================================== 00019 ##### How to use this driver ##### 00020 ============================================================================== 00021 [..] 00022 The LL CORTEX driver contains a set of generic APIs that can be 00023 used by user: 00024 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick 00025 functions 00026 (+) Low power mode configuration (SCB register of Cortex-MCU) 00027 (+) MPU API to configure and enable regions 00028 (+) API to access to MCU info (CPUID register) 00029 (+) API to enable fault handler (SHCSR accesses) 00030 00031 @endverbatim 00032 */ 00033 00034 /* Define to prevent recursive inclusion -------------------------------------*/ 00035 #ifndef __STM32G4xx_LL_CORTEX_H 00036 #define __STM32G4xx_LL_CORTEX_H 00037 00038 #ifdef __cplusplus 00039 extern "C" { 00040 #endif 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include "stm32g4xx.h" 00044 00045 /** @addtogroup STM32G4xx_LL_Driver 00046 * @{ 00047 */ 00048 00049 /** @defgroup CORTEX_LL CORTEX 00050 * @{ 00051 */ 00052 00053 /* Private types -------------------------------------------------------------*/ 00054 /* Private variables ---------------------------------------------------------*/ 00055 00056 /* Private constants ---------------------------------------------------------*/ 00057 00058 /* Private macros ------------------------------------------------------------*/ 00059 00060 /* Exported types ------------------------------------------------------------*/ 00061 /* Exported constants --------------------------------------------------------*/ 00062 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00063 * @{ 00064 */ 00065 00066 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00067 * @{ 00068 */ 00069 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00070 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00071 /** 00072 * @} 00073 */ 00074 00075 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00076 * @{ 00077 */ 00078 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00079 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00080 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00081 /** 00082 * @} 00083 */ 00084 00085 #if __MPU_PRESENT 00086 00087 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00088 * @{ 00089 */ 00090 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 00091 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00092 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00093 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00094 /** 00095 * @} 00096 */ 00097 00098 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00099 * @{ 00100 */ 00101 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 00102 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 00103 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 00104 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 00105 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 00106 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 00107 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 00108 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 00109 /** 00110 * @} 00111 */ 00112 00113 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00114 * @{ 00115 */ 00116 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00117 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00118 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00119 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00120 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00121 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00122 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00123 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00124 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00125 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00126 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00127 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00128 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00129 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00130 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00131 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00132 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00133 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00134 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00136