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STM32G474xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * Copyright (c) 2019 STMicroelectronics. 00027 * All rights reserved. 00028 * 00029 * This software is licensed under terms that can be found in the LICENSE file in 00030 * the root directory of this software component. 00031 * If no LICENSE file comes with this software, it is provided AS-IS. 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32G4xx_LL_BUS_H 00037 #define STM32G4xx_LL_BUS_H 00038 00039 #ifdef __cplusplus 00040 extern "C" { 00041 #endif 00042 00043 /* Includes ------------------------------------------------------------------*/ 00044 #include "stm32g4xx.h" 00045 00046 /** @addtogroup STM32G4xx_LL_Driver 00047 * @{ 00048 */ 00049 00050 #if defined(RCC) 00050 00052 /** @defgroup BUS_LL BUS 00053 * @{ 00054 */ 00055 00056 /* Private types -------------------------------------------------------------*/ 00057 /* Private variables ---------------------------------------------------------*/ 00058 00059 /* Private constants ---------------------------------------------------------*/ 00060 00062 /* Private macros ------------------------------------------------------------*/ 00063 00064 /* Exported types ------------------------------------------------------------*/ 00064 /* Exported constants --------------------------------------------------------*/ 00066 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00066 * @{ 00067 */ 00069 00070 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00071 * @{ 00072 */ 00072 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00073 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00074 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00075 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN 00076 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN 00077 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN 00078 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN 00079 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN 00080 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00081 /** 00082 * @} 00083 */ 00084 00086 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00087 * @{ 00088 */ 00089 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00090 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN 00091 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN 00092 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN 00093 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN 00094 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN 00095 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN 00096 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN 00097 #define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSRAMSMEN 00098 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN 00099 #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN 00100 #if defined(ADC345_COMMON) 00100 #define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN 00101 #endif /* ADC345_COMMON */ 00102 #define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN 00104 #if defined(DAC2) 00105 #define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN 00106 #endif /* DAC2 */ 00107 #define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN 00108 #if defined(DAC4) 00109 #define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN 00110 #endif /* DAC4 */ 00111 #if defined(AES) 00112 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00113 #endif /* AES */ 00114 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00115 /** 00116 * @} 00117 */ 00118 00119 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00120 * @{ 00121 */ 00122 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 00123 #if defined(FMC_Bank1_R) 00123 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00125 #endif /* FMC_Bank1_R */ 00126 #if defined(QUADSPI) 00127 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00128 #endif /* QUADSPI */ 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00134 * @{ 00135 */ 00136 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00137 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN 00138 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN 00139 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN 00140 #if defined(TIM5) 00141 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN 00142 #endif /* TIM5 */ 00143 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN 00144 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN 00145 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN 00146 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN 00147 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN