|
STM32G474xx HAL用户手册
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32G4xx_LL_ADC_H 00021 #define STM32G4xx_LL_ADC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32g4xx.h" 00029 00030 /** @addtogroup STM32G4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) 00035 00036 /** @defgroup ADC_LL ADC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 00043 /* Private constants ---------------------------------------------------------*/ 00044 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00045 * @{ 00046 */ 00047 00048 /* Internal mask for ADC group regular sequencer: */ 00049 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00050 /* - sequencer register offset */ 00051 /* - sequencer rank bits position into the selected register */ 00052 00053 /* Internal register offset for ADC group regular sequencer configuration */ 00054 /* (offset placed into a spare area of literal definition) */ 00055 #define ADC_SQR1_REGOFFSET (0x00000000UL) 00056 #define ADC_SQR2_REGOFFSET (0x00000100UL) 00057 #define ADC_SQR3_REGOFFSET (0x00000200UL) 00058 #define ADC_SQR4_REGOFFSET (0x00000300UL) 00059 00060 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ 00061 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00062 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/ 00063 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00064 00065 /* Definition of ADC group regular sequencer bits information to be inserted */ 00066 /* into ADC group regular sequencer ranks literals definition. */ 00067 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos) 00068 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos) 00069 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos) 00070 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos) 00071 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos) 00072 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos) 00073 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos) 00074 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos) 00075 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos) 00076 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos) 00077 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos) 00078 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos) 00079 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos) 00080 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos) 00081 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) 00082 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) 00083 00084 /* Internal mask for ADC group injected sequencer: */ 00085 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00086 /* - data register offset */ 00087 /* - sequencer rank bits position into the selected register */ 00088 00089 /* Internal register offset for ADC group injected data register */ 00090 /* (offset placed into a spare area of literal definition) */ 00091 #define ADC_JDR1_REGOFFSET (0x00000000UL) 00092 #define ADC_JDR2_REGOFFSET (0x00000100UL) 00093 #define ADC_JDR3_REGOFFSET (0x00000200UL) 00094 #define ADC_JDR4_REGOFFSET (0x00000300UL) 00095 00096 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ 00097 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00098 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00099 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/ 00100 00101 /* Definition of ADC group injected sequencer bits information to be inserted */ 00102 /* into ADC group injected sequencer ranks literals definition. */ 00103 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos) 00104 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos) 00105 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) 00106 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) 00107 00108 /* Internal mask for ADC group regular trigger: */ 00109 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 00110 /* - regular trigger source */ 00111 /* - regular trigger edge */ 00112 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for 00113 compatibility with some ADC on other STM32 series 00114 having this setting set by HW default value) */ 00115 00116 /* Mask containing trigger source masks for each of possible */ 00117 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00118 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00119 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ 00120 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ 00121 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ 00122 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) 00123 00124 /* Mask containing trigger edge masks for each of possible */ 00125 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00126 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00127 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ 00128 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ 00129 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ 00130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) 00131 00132 /* Definition of ADC group regular trigger bits information. */ 00133 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) 00134 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) 00135 00136 /* Internal mask for ADC group injected trigger: */ 00137 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 00138 /* - injected trigger source */