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STM32G474xx HAL用户手册
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32g4xx_ll_adc.c 00004 * @author MCD Application Team 00005 * @brief ADC LL module driver 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32g4xx_ll_adc.h" 00022 #include "stm32g4xx_ll_bus.h" 00023 00024 #ifdef USE_FULL_ASSERT 00025 #include "stm32_assert.h" 00026 #else 00027 #define assert_param(expr) ((void)0U) 00028 #endif /* USE_FULL_ASSERT */ 00029 00030 /** @addtogroup STM32G4xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) 00035 00036 /** @addtogroup ADC_LL ADC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /** @addtogroup ADC_LL_Private_Constants 00044 * @{ 00045 */ 00046 00047 /* Definitions of ADC hardware constraints delays */ 00048 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ 00049 /* not timeout values: */ 00050 /* Timeout values for ADC operations are dependent to device clock */ 00051 /* configuration (system clock versus ADC clock), */ 00052 /* and therefore must be defined in user application. */ 00053 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ 00054 /* values definition. */ 00055 /* Note: ADC timeout values are defined here in CPU cycles to be independent */ 00056 /* of device clock setting. */ 00057 /* In user application, ADC timeout values should be defined with */ 00058 /* temporal values, in function of device clock settings. */ 00059 /* Highest ratio CPU clock frequency vs ADC clock frequency: */ 00060 /* - ADC clock from synchronous clock with AHB prescaler 512, */ 00061 /* ADC prescaler 4. */ 00062 /* Ratio max = 512 *4 = 2048 */ 00063 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ 00064 /* Highest CPU clock PLL (PLLR). */ 00065 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ 00066 /* = 3968 */ 00067 /* Unit: CPU cycles. */ 00068 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL) 00069 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) 00070 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) 00071 00072 /** 00073 * @} 00074 */ 00075 00076 /* Private macros ------------------------------------------------------------*/ 00077 00078 /** @addtogroup ADC_LL_Private_Macros 00079 * @{ 00080 */ 00081 00082 /* Check of parameters for configuration of ADC hierarchical scope: */ 00083 /* common to several ADC instances. */ 00084 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 00085 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ 00086 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 00087 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 00088 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ 00089 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ 00090 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ 00091 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ 00092 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ 00093 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ 00094 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ 00095 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ 00096 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ 00097 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ 00098 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ 00099 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ 00100 ) 00101 00102 /* Check of parameters for configuration of ADC hierarchical scope: */ 00103 /* ADC instance. */ 00104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 00105 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 00106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 00107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 00108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ 00109 ) 00110 00111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ 00112 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ 00113 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ 00114 ) 00115 00116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ 00117 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ 00118 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ 00119 ) 00120 00121 /* Check of parameters for configuration of ADC hierarchical scope: */ 00122 /* ADC group regular */ 00123 #if defined(STM32G474xx) || defined(STM32G484xx) 00124 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ 00125 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ 00127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ 00128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ 00132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ 00133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ 00134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ 00136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ 00137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ 00138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ 00139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ 00140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ 00141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ 00142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \ 00143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \ 00144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \ 00145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \ 00146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \ 00147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \ 00148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ 00149 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ 00150 && ( \ 00151 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 00152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 00153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ 00155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 00156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ 00157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ 00158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 00159 ) \ 00160 ) \ 00161 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ 00162 && ( \ 00163 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ 00164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ 00165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ 00166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ 00167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ 00168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ 00169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \ 00170 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \ 00171 ) \ 00172 ) \ 00173 ) 00174 #elif defined(STM32G473xx) || defined(STM32G483xx) 00175 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ 00176 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00177 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ 00178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ 00179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00182 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00183 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ 00184 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ 00185 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ 00186 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00187 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ 00188 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ 00189